| /external/llvm/lib/CodeGen/ |
| LiveIntervalUnion.h | 124 Query(LiveInterval *VReg, LiveIntervalUnion *LIU):
125 LiveUnion(LIU), VirtReg(VReg), CheckedFirstInterference(false),
140 void init(unsigned UTag, LiveInterval *VReg, LiveIntervalUnion *LIU) {
141 assert(VReg && LIU && "Invalid arguments");
142 if (UserTag == UTag && VirtReg == VReg &&
149 VirtReg = VReg;
167 bool isSeenInterference(LiveInterval *VReg) const;
172 // Did collectInterferingVRegs encounter an unspillable vreg?
|
| LiveIntervalUnion.cpp | 150 LiveInterval *VReg = LiveUnionI.value();
151 if (VReg != RecentReg && !isSeenInterference(VReg)) {
152 RecentReg = VReg;
153 InterferingVRegs.push_back(VReg);
|
| MachineFunction.cpp | 393 unsigned VReg = MRI.getLiveInVirtReg(PReg);
394 if (VReg) {
395 assert(MRI.getRegClass(VReg) == RC && "Register class mismatch!");
396 return VReg;
398 VReg = MRI.createVirtualRegister(RC);
399 MRI.addLiveIn(PReg, VReg);
400 return VReg;
|
| LiveRangeEdit.cpp | 36 unsigned VReg = MRI.createVirtualRegister(MRI.getRegClass(OldReg));
38 VRM.setIsSplitFromReg(VReg, VRM.getOriginal(OldReg));
39 LiveInterval &LI = LIS.getOrCreateInterval(VReg);
|
| MachineRegisterInfo.cpp | 35 "Vreg use list non-empty still?");
122 // The back pointers for the vreg lists point into the previous vector.
195 /// getLiveInPhysReg - If VReg is a live-in virtual register, return the
197 unsigned MachineRegisterInfo::getLiveInPhysReg(unsigned VReg) const {
199 if (I->second == VReg)
|
| LiveIntervalAnalysis.cpp | 294 // done once for the vreg. We use an empty interval to detect the first
295 // time we see a vreg.
329 // Loop over all of the blocks that the vreg is defined in. There are
330 // two cases we have to handle here. The most common case is a vreg
412 // the result of two address elimination, then the vreg is one of the
[all...] |
| TailDuplication.cpp | 221 unsigned VReg = SSAUpdateVRs[i];
222 SSAUpdate.Initialize(VReg);
226 MachineInstr *DefMI = MRI->getVRegDef(VReg);
230 SSAUpdate.AddAvailableValue(DefBB, VReg);
235 SSAUpdateVals.find(VReg);
243 MachineRegisterInfo::use_iterator UI = MRI->use_begin(VReg);
[all...] |
| TwoAddressInstructionPass.cpp | [all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| InstrEmitter.cpp | 81 // If the node is only used by a CopyToReg and the dest reg is a vreg, use
82 // the CopyToReg'd destination register instead of creating a new vreg.
196 // is a vreg in the same register class, use the CopyToReg'd destination
197 // register instead of creating a new vreg.
251 unsigned VReg = getDstOfOnlyCopyToRegUse(Op.getNode(), Op.getResNo());
254 if (!VReg) {
256 VReg = MRI->createVirtualRegister(RC);
259 TII->get(TargetOpcode::IMPLICIT_DEF), VReg);
260 return VReg;
282 unsigned VReg = getVR(Op, VRBaseMap)
[all...] |
| InstrEmitter.h | 80 /// ConstrainForSubReg - Try to constrain VReg to a register class that
83 unsigned ConstrainForSubReg(unsigned VReg, unsigned SubIdx,
|
| /external/llvm/lib/Target/ARM/ |
| Thumb1RegisterInfo.cpp | 593 unsigned VReg = 0;
674 // register. The offset is already handled in the vreg value.
677 VReg = MF.getRegInfo().createVirtualRegister(ARM::tGPRRegisterClass);
682 emitThumbRegPlusImmInReg(MBB, II, dl, VReg, FrameReg,
685 emitLoadConstPool(MBB, II, dl, VReg, 0, Offset);
689 emitThumbRegPlusImmediate(MBB, II, dl, VReg, FrameReg, Offset, TII,
692 MI.getOperand(i).ChangeToRegister(VReg, false, false, true);
695 // register. The offset is already handled in the vreg value.
|
| ARMISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | [all...] |
| /external/llvm/include/llvm/CodeGen/ |
| MachineRegisterInfo.h | 25 /// registers, including vreg register classes, use/def chains for registers,
36 /// Each element in this list contains the register class of the vreg and the
309 void addLiveIn(unsigned Reg, unsigned vreg = 0) {
310 LiveIns.push_back(std::make_pair(Reg, vreg));
329 /// getLiveInPhysReg - If VReg is a live-in virtual register, return the
331 unsigned getLiveInPhysReg(unsigned VReg) const;
|
| /external/llvm/lib/Target/Sparc/ |
| SparcISelLowering.cpp | 212 unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
213 MF.getRegInfo().addLiveIn(VA.getLocReg(), VReg);
214 SDValue Arg = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
324 unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
325 MF.getRegInfo().addLiveIn(*CurArgReg, VReg);
326 SDValue Arg = DAG.getCopyFromReg(DAG.getRoot(), dl, VReg, MVT::i32);
[all...] |
| /external/llvm/lib/Target/SystemZ/ |
| SystemZISelLowering.cpp | 330 unsigned VReg = RegInfo.createVirtualRegister(RC);
331 RegInfo.addLiveIn(VA.getLocReg(), VReg);
332 ArgValue = DAG.getCopyFromReg(Chain, dl, VReg, LocVT);
817 // control-flow pattern. The incoming instruction knows the destination vreg
[all...] |
| /external/llvm/lib/Target/CellSPU/ |
| SPUISelLowering.cpp | 636 unsigned VReg = RegInfo.createVirtualRegister(&SPU::R32CRegClass);
647 the_chain = DAG.getCopyToReg(the_chain, dl, VReg, basePtr, Flag);
648 basePtr = DAG.getCopyFromReg(the_chain, dl, VReg, PtrVT);
[all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/Alpha/ |
| AlphaISelLowering.cpp | 42 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC);
43 MF.getRegInfo().addLiveIn(PReg, VReg);
44 return VReg;
[all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.cpp | 337 unsigned VReg =
339 RegInfo.addLiveIn(VA.getLocReg(), VReg);
340 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, VReg, RegVT);
[all...] |
| /external/webkit/Source/JavaScriptCore/jit/ |
| JIT.h | 536 void emitJumpSlowCaseIfNotJSCell(RegisterID, int VReg);
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsISelLowering.cpp | 695 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC);
696 MF.getRegInfo().addLiveIn(PReg, VReg);
697 return VReg;
724 // destination vreg to set, the condition code register to branch on, the
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86ISelLowering.cpp | [all...] |
