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    Searched refs:VirtReg (Results 1 - 14 of 14) sorted by null

  /external/llvm/lib/CodeGen/
LiveIntervalUnion.cpp 28 void LiveIntervalUnion::unify(LiveInterval &VirtReg) {
29 if (VirtReg.empty())
34 LiveInterval::iterator RegPos = VirtReg.begin();
35 LiveInterval::iterator RegEnd = VirtReg.end();
39 SegPos.insert(RegPos->start, RegPos->end, &VirtReg);
49 SegPos.insert(RegEnd->start, RegEnd->end, &VirtReg);
51 SegPos.insert(RegPos->start, RegPos->end, &VirtReg);
55 void LiveIntervalUnion::extract(LiveInterval &VirtReg) {
56 if (VirtReg.empty())
61 LiveInterval::iterator RegPos = VirtReg.begin()
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RegAllocBase.h 113 LiveIntervalUnion::Query &query(LiveInterval &VirtReg, unsigned PhysReg) {
114 Queries[PhysReg].init(UserTag, &VirtReg, &PhysReg2LiveUnion[PhysReg]);
133 /// enqueue - Add VirtReg to the priority queue of unassigned registers.
143 virtual unsigned selectOrSplit(LiveInterval &VirtReg,
152 unsigned checkPhysRegInterference(LiveInterval& VirtReg, unsigned PhysReg);
154 /// assign - Assign VirtReg to PhysReg.
156 void assign(LiveInterval &VirtReg, unsigned PhysReg);
158 /// unassign - Undo a previous assignment of VirtReg to PhysReg.
161 void unassign(LiveInterval &VirtReg, unsigned PhysReg);
166 bool spillInterferences(LiveInterval &VirtReg, unsigned PhysReg
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LiveIntervalUnion.h 92 void unify(LiveInterval &VirtReg);
95 void extract(LiveInterval &VirtReg);
112 LiveInterval *VirtReg;
113 LiveInterval::iterator VirtRegI; // current position in VirtReg
122 Query(): LiveUnion(), VirtReg(), Tag(0), UserTag(0) {}
125 LiveUnion(LIU), VirtReg(VReg), CheckedFirstInterference(false),
131 VirtReg = NULL;
142 if (UserTag == UTag && VirtReg == VReg &&
149 VirtReg = VReg;
154 LiveInterval &virtReg() const
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RegAllocBasic.cpp 125 virtual unsigned selectOrSplit(LiveInterval &VirtReg,
268 LiveInterval &VirtReg = *I->second;
270 PhysReg2LiveUnion[RegNum].unify(VirtReg);
272 enqueue(&VirtReg);
276 void RegAllocBase::assign(LiveInterval &VirtReg, unsigned PhysReg) {
277 DEBUG(dbgs() << "assigning " << PrintReg(VirtReg.reg, TRI)
279 assert(!VRM->hasPhys(VirtReg.reg) && "Duplicate VirtReg assignment");
280 VRM->assignVirt2Phys(VirtReg.reg, PhysReg);
282 PhysReg2LiveUnion[PhysReg].unify(VirtReg);
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AllocationOrder.h 34 /// AllocationOrder - Create a new AllocationOrder for VirtReg.
35 /// @param VirtReg Virtual register to allocate for.
39 AllocationOrder(unsigned VirtReg,
AllocationOrder.cpp 25 AllocationOrder::AllocationOrder(unsigned VirtReg,
29 const TargetRegisterClass *RC = VRM.getRegInfo().getRegClass(VirtReg);
31 VRM.getRegInfo().getRegAllocationHint(VirtReg);
RegAllocGreedy.cpp 138 LiveRangeStage getStage(const LiveInterval &VirtReg) const {
139 return ExtraRegInfo[VirtReg.reg].Stage;
142 void setStage(const LiveInterval &VirtReg, LiveRangeStage Stage) {
144 ExtraRegInfo[VirtReg.reg].Stage = Stage;
358 bool RAGreedy::LRE_CanEraseVirtReg(unsigned VirtReg) {
359 if (unsigned PhysReg = VRM->getPhys(VirtReg)) {
360 unassign(LIS->getInterval(VirtReg), PhysReg);
363 // Unassigned virtreg is probably in the priority queue.
368 void RAGreedy::LRE_WillShrinkVirtReg(unsigned VirtReg) {
369 unsigned PhysReg = VRM->getPhys(VirtReg);
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VirtRegRewriter.cpp 368 // VirtReg - The virtual register itself.
369 unsigned VirtReg;
374 AssignedPhysReg(apr), VirtReg(vreg) {}
396 unsigned VirtReg) {
403 AssignedPhysReg, VirtReg));
437 unsigned GetRegForReload(unsigned VirtReg, unsigned PhysReg, MachineInstr *MI,
445 const TargetRegisterClass* RC = MF.getRegInfo().getRegClass(VirtReg);
692 unsigned VirtReg = MO.getReg();
693 if (TargetRegisterInfo::isPhysicalRegister(VirtReg))
696 unsigned Phys = VRM.getPhys(VirtReg);
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RegAllocFast.cpp 111 // PhysRegState - One of the RegState enums, or a virtreg.
150 int getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC);
155 void killVirtReg(unsigned VirtReg);
157 void spillVirtReg(MachineBasicBlock::iterator MI, unsigned VirtReg);
165 unsigned VirtReg, unsigned Hint);
167 unsigned VirtReg, unsigned Hint);
176 int RAFast::getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC) {
178 int SS = StackSlotForVirtReg[VirtReg];
187 StackSlotForVirtReg[VirtReg] = FrameIdx;
223 /// killVirtReg - Mark virtreg as no longer available
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VirtRegMap.h 171 bool hasPhys(unsigned virtReg) const {
172 return getPhys(virtReg) != NO_PHYS_REG;
177 unsigned getPhys(unsigned virtReg) const {
178 assert(TargetRegisterInfo::isVirtualRegister(virtReg));
179 return Virt2PhysMap[virtReg];
184 void assignVirt2Phys(unsigned virtReg, unsigned physReg) {
185 assert(TargetRegisterInfo::isVirtualRegister(virtReg) &&
187 assert(Virt2PhysMap[virtReg] == NO_PHYS_REG &&
190 Virt2PhysMap[virtReg] = physReg;
195 void clearVirt(unsigned virtReg) {
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LiveDebugVariables.cpp 303 /// lookupVirtReg - Find the EC leader for VirtReg or null.
304 UserValue *lookupVirtReg(unsigned VirtReg);
335 void mapVirtReg(unsigned VirtReg, UserValue *EC);
429 void LDVImpl::mapVirtReg(unsigned VirtReg, UserValue *EC) {
430 assert(TargetRegisterInfo::isVirtualRegister(VirtReg) && "Only map VirtRegs");
431 UserValue *&Leader = virtRegToEqClass[VirtReg];
435 UserValue *LDVImpl::lookupVirtReg(unsigned VirtReg) {
436 if (UserValue *UV = virtRegToEqClass.lookup(VirtReg))
885 unsigned VirtReg = Loc.getReg();
886 if (VRM.isAssignedReg(VirtReg) &
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VirtRegMap.cpp 118 unsigned VirtRegMap::getRegAllocPref(unsigned virtReg) {
119 std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(virtReg);
129 int VirtRegMap::assignVirt2StackSlot(unsigned virtReg) {
130 assert(TargetRegisterInfo::isVirtualRegister(virtReg));
131 assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT &&
133 const TargetRegisterClass* RC = MF->getRegInfo().getRegClass(virtReg);
134 return Virt2StackSlotMap[virtReg] = createSpillSlot(RC);
137 void VirtRegMap::assignVirt2StackSlot(unsigned virtReg, int SS) {
138 assert(TargetRegisterInfo::isVirtualRegister(virtReg));
139 assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT &
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InlineSpiller.cpp 834 bool InlineSpiller::reMaterializeFor(LiveInterval &VirtReg,
837 VNInfo *ParentVNI = VirtReg.getVNInfoAt(UseIdx.getBaseIndex());
843 if (MO.isReg() && MO.isUse() && MO.getReg() == VirtReg.reg)
859 markValueUsed(&VirtReg, ParentVNI);
864 // If the instruction also writes VirtReg.reg, it had better not require the
868 tie(Reads, Writes) = MI->readsWritesVirtualRegister(VirtReg.reg, &Ops);
873 markValueUsed(&VirtReg, ParentVNI);
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PrologEpilogInserter.cpp 822 unsigned VirtReg = 0;
842 if (Reg != VirtReg) {
848 VirtReg = Reg;

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