| /external/llvm/lib/Target/CellSPU/ |
| SPUInstrBuilder.h | 36 return MIB.addImm(Offset).addFrameIndex(FI);
38 return MIB.addFrameIndex(FI).addImm(Offset);
|
| SPUFrameLowering.cpp | 124 BuildMI(MBB, MBBI, dl, TII.get(SPU::STQDr32), SPU::R0).addImm(16)
128 BuildMI(MBB, MBBI, dl, TII.get(SPU::STQDr32), SPU::R1).addImm(FrameSize)
132 .addImm(FrameSize);
137 .addImm(-16)
140 .addImm(FrameSize);
149 .addImm(16);
209 .addImm(FrameSize + LinkSlotOffset)
213 .addImm(FrameSize);
218 .addImm(16)
221 .addImm(FrameSize)
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCInstrBuilder.h | 36 return MIB.addImm(Offset).addFrameIndex(FI);
38 return MIB.addFrameIndex(FI).addImm(Offset);
|
| PPCFrameLowering.cpp | 138 .addImm(UsedRegMask);
142 .addImm(UsedRegMask);
147 .addImm(UsedRegMask >> 16);
151 .addImm(UsedRegMask >> 16);
156 .addImm(UsedRegMask >> 16);
160 .addImm(UsedRegMask >> 16);
164 .addImm(UsedRegMask & 0xFFFF);
318 .addImm(FPOffset/4)
324 .addImm(LROffset / 4)
333 .addImm(FPOffset
[all...] |
| PPCBranchSelector.cpp | 152 .addImm(PPC::InvertPredicate(Pred)).addReg(CRReg).addImm(2);
|
| PPCRegisterInfo.cpp | 299 addImm(CalleeAmt);
303 .addImm(CalleeAmt >> 16);
306 .addImm(CalleeAmt & 0xFFFF);
384 .addImm(FrameSize);
388 .addImm(0)
392 .addImm(0)
396 .addImm(0)
417 .addImm(maxCallFrameSize);
422 .addImm(maxCallFrameSize)
433 .addImm(maxCallFrameSize)
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86InstrBuilder.h | 94 return MIB.addReg(Reg).addImm(1).addReg(0).addImm(0).addReg(0);
100 return MIB.addImm(1).addReg(0).addImm(Offset).addReg(0);
118 return MIB.addReg(Reg1, getKillRegState(isKill1)).addImm(1)
119 .addReg(Reg2, getKillRegState(isKill2)).addImm(0).addReg(0);
134 MIB.addImm(AM.Scale).addReg(AM.IndexReg);
138 MIB.addImm(AM.Disp);
178 return MIB.addReg(GlobalBaseReg).addImm(1).addReg(0)
|
| /external/llvm/lib/Target/SystemZ/ |
| SystemZInstrBuilder.h | 62 return MIB.addReg(Reg).addImm(0).addReg(0);
67 return MIB.addImm(Offset).addReg(0);
85 return MIB.addReg(Reg1, getKillRegState(isKill1)).addImm(0)
98 return MIB.addImm(AM.Disp).addReg(AM.IndexReg);
|
| /external/llvm/lib/Target/Alpha/ |
| AlphaFrameLowering.cpp | 57 .addGlobalAddress(MF.getFunction()).addReg(Alpha::R27).addImm(++curgpdist);
59 .addGlobalAddress(MF.getFunction()).addReg(Alpha::R29).addImm(curgpdist);
82 BuildMI(MBB, MBBI, dl, TII.get(Alpha::LDA), Alpha::R30).addImm(NumBytes)
86 .addImm(getUpper16(NumBytes)).addReg(Alpha::R30);
88 .addImm(getLower16(NumBytes)).addReg(Alpha::R30);
96 .addReg(Alpha::R15).addImm(0).addReg(Alpha::R30);
127 .addImm(0).addReg(Alpha::R15);
132 BuildMI(MBB, MBBI, dl, TII.get(Alpha::LDA), Alpha::R30).addImm(NumBytes)
136 .addImm(getUpper16(NumBytes)).addReg(Alpha::R30);
138 .addImm(getLower16(NumBytes)).addReg(Alpha::R30)
[all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcFrameLowering.cpp | 56 .addReg(SP::O6).addImm(NumBytes);
61 BuildMI(MBB, MBBI, dl, TII.get(SP::SETHIi), SP::G1).addImm(OffHi);
64 .addReg(SP::G1).addImm(NumBytes & ((1 << 10)-1));
|
| SparcInstrInfo.cpp | 195 .addMBB(UnCondBrIter->getOperand(0).getMBB()).addImm(BranchCode);
237 BuildMI(&MBB, DL, get(SP::BCOND)).addMBB(TBB).addImm(CC);
239 BuildMI(&MBB, DL, get(SP::FBCOND)).addMBB(TBB).addImm(CC);
296 BuildMI(MBB, I, DL, get(SP::STri)).addFrameIndex(FI).addImm(0)
299 BuildMI(MBB, I, DL, get(SP::STFri)).addFrameIndex(FI).addImm(0)
302 BuildMI(MBB, I, DL, get(SP::STDFri)).addFrameIndex(FI).addImm(0)
317 BuildMI(MBB, I, DL, get(SP::LDri), DestReg).addFrameIndex(FI).addImm(0);
319 BuildMI(MBB, I, DL, get(SP::LDFri), DestReg).addFrameIndex(FI).addImm(0);
321 BuildMI(MBB, I, DL, get(SP::LDDFri), DestReg).addFrameIndex(FI).addImm(0);
|
| /external/llvm/lib/Target/Blackfin/ |
| BlackfinInstrInfo.cpp | 113 .addImm(0);
121 BuildMI(MBB, I, DL, get(BF::BITTGL), DestReg).addReg(DestReg).addImm(0);
134 .addReg(SrcReg, getKillRegState(KillSrc)).addImm(0);
183 .addImm(0);
191 .addImm(0);
199 .addImm(0);
228 .addImm(0);
235 .addImm(0);
242 .addImm(0);
|
| BlackfinRegisterInfo.cpp | 99 .addImm(delta);
128 BuildMI(MBB, I, DL, TII.get(BF::LOADimm7), Reg).addImm(value);
133 BuildMI(MBB, I, DL, TII.get(BF::LOADuimm16), Reg).addImm(value);
138 BuildMI(MBB, I, DL, TII.get(BF::LOADimm16), Reg).addImm(value);
145 .addImm((value >> 16) & 0xffff)
149 .addImm(value & 0xffff)
288 .addReg(ScratchReg).addImm(0);
319 .addImm(0);
|
| /external/llvm/lib/Target/Mips/ |
| MipsEmitGPRestore.cpp | 68 .addImm(0);
81 .addImm(0);
|
| /external/llvm/lib/Target/XCore/ |
| XCoreRegisterInfo.cpp | 149 .addImm(Amount);
154 .addImm(Amount);
262 .addImm(Offset);
268 .addImm(Offset);
273 .addImm(Offset);
290 .addImm(Offset);
296 .addImm(Offset);
301 .addImm(Offset);
320 BuildMI(MBB, I, dl, TII.get(Opcode), DstReg).addImm(Value);
|
| XCoreInstrInfo.cpp | 344 .addImm(0);
349 BuildMI(MBB, I, DL, get(XCore::LDAWSP_ru6), DestReg).addImm(0);
373 .addImm(0);
386 .addImm(0);
394 .addFrameIndex(FrameIx).addImm(0).addImm(Offset).addMetadata(MDPtr);
|
| XCoreFrameLowering.cpp | 56 .addImm(Offset);
72 .addImm(Offset);
136 BuildMI(MBB, MBBI, dl, TII.get(Opcode)).addImm(FrameSize);
186 .addImm(0);
265 BuildMI(MBB, MBBI, dl, TII.get(Opcode)).addImm(FrameSize);
269 BuildMI(MBB, MBBI, dl, TII.get(Opcode), XCore::SP).addImm(FrameSize);
|
| /external/llvm/lib/Target/ARM/ |
| Thumb2RegisterInfo.cpp | 50 .addConstantPoolIndex(Idx).addImm((int64_t)ARMCC::AL).addReg(0)
|
| Thumb1InstrInfo.cpp | 70 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
98 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
|
| ARMExpandPseudoInsts.cpp | 588 MIB.addImm(Lane);
667 LO16 = LO16.addImm(SOImmValV1);
668 HI16 = HI16.addImm(SOImmValV2);
[all...] |
| Thumb2InstrInfo.cpp | 140 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
167 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
191 .addImm(NumBytes)
192 .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags);
198 .addImm(NumBytes >> 16)
199 .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags);
208 .addImm((unsigned)Pred).addReg(PredReg).addReg(0)
214 .addImm((unsigned)Pred).addReg(PredReg).addReg(0)
239 .addReg(BaseReg).addImm(ThisVal/4).setMIFlags(MIFlags));
279 .addImm(ThisVal)).setMIFlags(MIFlags)
[all...] |
| ARMFastISel.cpp | 363 .addImm(Imm));
367 .addImm(Imm));
409 .addImm(Imm));
414 .addImm(Imm));
430 .addImm(Imm));
433 .addImm(Imm));
449 .addImm(Imm1).addImm(Imm2));
452 .addImm(Imm1).addImm(Imm2))
[all...] |
| /external/llvm/lib/Target/MBlaze/ |
| MBlazeFrameLowering.cpp | 258 .addFrameIndex(FI).addImm(0);
266 .addFrameIndex(R17FI).addImm(0);
269 .addFrameIndex(R18FI).addImm(0);
277 .addFrameIndex(MSRFI).addImm(0);
280 .addFrameIndex(MSRFI).addImm(0);
287 .addFrameIndex(R18FI).addImm(0);
290 .addFrameIndex(R17FI).addImm(0);
296 .addFrameIndex(VFI[--i]).addImm(0);
368 .addReg(MBlaze::R1).addImm(-StackSize);
373 .addReg(MBlaze::R15).addReg(MBlaze::R1).addImm(RAOffset)
[all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430RegisterInfo.cpp | 125 .addReg(MSP430::SPW).addImm(Amount);
134 .addReg(MSP430::SPW).addImm(Amount);
152 MSP430::SPW).addReg(MSP430::SPW).addImm(CalleeAmt);
210 .addReg(DstReg).addImm(-Offset);
213 .addReg(DstReg).addImm(Offset);
|
| MSP430InstrInfo.cpp | 54 .addFrameIndex(FrameIdx).addImm(0)
58 .addFrameIndex(FrameIdx).addImm(0)
83 .addReg(DestReg).addFrameIndex(FrameIdx).addImm(0).addMemOperand(MMO);
86 .addReg(DestReg).addFrameIndex(FrameIdx).addImm(0).addMemOperand(MMO);
284 BuildMI(&MBB, DL, get(MSP430::JCC)).addMBB(TBB).addImm(Cond[0].getImm());
|
