| /external/llvm/lib/Target/SystemZ/ |
| SystemZInstrBuilder.h | 62 return MIB.addReg(Reg).addImm(0).addReg(0);
67 return MIB.addImm(Offset).addReg(0);
77 return addOffset(MIB.addReg(Reg, getKillRegState(isKill)), Offset);
85 return MIB.addReg(Reg1, getKillRegState(isKill1)).addImm(0)
86 .addReg(Reg2, getKillRegState(isKill2));
92 MIB.addReg(AM.Base.Reg);
98 return MIB.addImm(AM.Disp).addReg(AM.IndexReg);
|
| SystemZFrameLowering.cpp | 87 .addReg(SystemZ::R15D).addImm(isSub ? -ThisVal : ThisVal);
131 .addReg(SystemZ::R15D);
269 MIB.addReg(SystemZ::R15D).addImm(StartOffset);
271 MIB.addReg(0);
272 MIB.addReg(LowReg, RegState::Kill);
274 MIB.addReg(HighReg, RegState::Kill);
282 MIB.addReg(Reg, RegState::ImplicitKill);
333 MIB.addReg(LowReg, RegState::Define);
335 MIB.addReg(HighReg, RegState::Define);
337 MIB.addReg(hasFP(MF) ? SystemZ::R11D : SystemZ::R15D)
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86InstrBuilder.h | 94 return MIB.addReg(Reg).addImm(1).addReg(0).addImm(0).addReg(0);
100 return MIB.addImm(1).addReg(0).addImm(Offset).addReg(0);
110 return addOffset(MIB.addReg(Reg, getKillRegState(isKill)), Offset);
118 return MIB.addReg(Reg1, getKillRegState(isKill1)).addImm(1)
119 .addReg(Reg2, getKillRegState(isKill2)).addImm(0).addReg(0);
128 MIB.addReg(AM.Base.Reg)
[all...] |
| /external/llvm/lib/Target/Alpha/ |
| AlphaLLRP.cpp | 78 .addReg(Alpha::R31)
79 .addReg(Alpha::R31);
90 .addReg(Alpha::R31)
91 .addReg(Alpha::R31);
93 .addReg(Alpha::R31)
94 .addReg(Alpha::R31);
104 .addReg(Alpha::R31).addReg(Alpha::R31);
106 .addReg(Alpha::R31).addReg(Alpha::R31)
[all...] |
| AlphaFrameLowering.cpp | 57 .addGlobalAddress(MF.getFunction()).addReg(Alpha::R27).addImm(++curgpdist);
59 .addGlobalAddress(MF.getFunction()).addReg(Alpha::R29).addImm(curgpdist);
83 .addReg(Alpha::R30);
86 .addImm(getUpper16(NumBytes)).addReg(Alpha::R30);
88 .addImm(getLower16(NumBytes)).addReg(Alpha::R30);
96 .addReg(Alpha::R15).addImm(0).addReg(Alpha::R30);
99 .addReg(Alpha::R30).addReg(Alpha::R30);
123 BuildMI(MBB, MBBI, dl, TII.get(Alpha::BISr), Alpha::R30).addReg(Alpha::R15
[all...] |
| AlphaInstrInfo.cpp | 103 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
106 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
113 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
116 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
127 .addReg(SrcReg)
128 .addReg(SrcReg, getKillRegState(KillSrc));
131 .addReg(SrcReg)
132 .addReg(SrcReg, getKillRegState(KillSrc));
135 .addReg(SrcReg)
136 .addReg(SrcReg, getKillRegState(KillSrc))
[all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcFrameLowering.cpp | 56 .addReg(SP::O6).addImm(NumBytes);
64 .addReg(SP::G1).addImm(NumBytes & ((1 << 10)-1));
66 .addReg(SP::O6).addReg(SP::G1);
78 BuildMI(MBB, MBBI, dl, TII.get(SP::RESTORErr), SP::G0).addReg(SP::G0)
79 .addReg(SP::G0);
|
| /external/llvm/lib/Target/CellSPU/ |
| SPUFrameLowering.cpp | 125 .addReg(SPU::R1);
129 .addReg(SPU::R1);
131 BuildMI(MBB, MBBI, dl, TII.get(SPU::AIr32), SPU::R1).addReg(SPU::R1)
138 .addReg(SPU::R1);
142 .addReg(SPU::R2)
143 .addReg(SPU::R1);
145 .addReg(SPU::R1)
146 .addReg(SPU::R2);
148 .addReg(SPU::R2)
151 .addReg(SPU::R2
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCFrameLowering.cpp | 137 .addReg(SrcReg)
141 .addReg(SrcReg, RegState::Kill)
146 .addReg(SrcReg)
150 .addReg(SrcReg, RegState::Kill)
155 .addReg(SrcReg)
159 .addReg(SrcReg, RegState::Kill)
163 .addReg(DstReg, RegState::Kill)
317 .addReg(PPC::X31)
319 .addReg(PPC::X1);
323 .addReg(PPC::X0
[all...] |
| PPCRegisterInfo.cpp | 298 BuildMI(MBB, I, dl, TII.get(ADDIInstr), StackReg).addReg(StackReg).
305 .addReg(TmpReg, RegState::Kill)
308 .addReg(StackReg)
309 .addReg(StackReg)
310 .addReg(TmpReg);
383 .addReg(PPC::R31)
389 .addReg(PPC::X1);
393 .addReg(PPC::X1);
397 .addReg(PPC::R1);
405 .addReg(Reg, RegState::Kill
[all...] |
| PPCInstrInfo.cpp | 150 .addReg(Reg0, RegState::Define | getDeadRegState(Reg0IsDead))
151 .addReg(Reg2, getKillRegState(Reg2IsKill))
152 .addReg(Reg1, getKillRegState(Reg1IsKill))
299 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
305 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
333 .addReg(SrcReg).addReg(SrcReg, getKillRegState(KillSrc));
335 BuildMI(MBB, I, DL, MCID, DestReg).addReg(SrcReg, getKillRegState(KillSrc));
348 .addReg(SrcReg,
357 .addReg(PPC::R11
[all...] |
| /external/llvm/lib/Target/ARM/ |
| Thumb2RegisterInfo.cpp | 49 .addReg(DestReg, getDefRegState(true), SubIdx)
50 .addConstantPoolIndex(Idx).addImm((int64_t)ARMCC::AL).addReg(0)
|
| ARMExpandPseudoInsts.cpp | 425 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead))
426 .addReg(D1, RegState::Define | getDeadRegState(DstIsDead));
428 MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead));
430 MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead));
461 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));
498 MIB.addReg(D0).addReg(D1);
500 MIB.addReg(D2);
502 MIB.addReg(D3);
552 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead))
[all...] |
| MLxExpansionPass.cpp | 226 .addReg(Src1Reg, getKillRegState(Src1Kill))
227 .addReg(Src2Reg, getKillRegState(Src2Kill));
230 MIB.addImm(Pred).addReg(PredReg);
233 .addReg(DstReg, getDefRegState(true) | getDeadRegState(DstDead));
237 MIB.addReg(TmpReg, getKillRegState(true))
238 .addReg(AccReg, getKillRegState(AccKill));
240 MIB.addReg(AccReg).addReg(TmpReg, getKillRegState(true));
242 MIB.addImm(Pred).addReg(PredReg);
|
| ARMFastISel.cpp | 295 .addReg(Op0, Op0IsKill * RegState::Kill));
298 .addReg(Op0, Op0IsKill * RegState::Kill));
301 .addReg(II.ImplicitDefs[0]));
315 .addReg(Op0, Op0IsKill * RegState::Kill)
316 .addReg(Op1, Op1IsKill * RegState::Kill));
319 .addReg(Op0, Op0IsKill * RegState::Kill)
320 .addReg(Op1, Op1IsKill * RegState::Kill));
323 .addReg(II.ImplicitDefs[0]));
338 .addReg(Op0, Op0IsKill * RegState::Kill)
339 .addReg(Op1, Op1IsKill * RegState::Kill
[all...] |
| Thumb2InstrInfo.cpp | 116 .addReg(SrcReg, getKillRegState(KillSrc)));
139 .addReg(SrcReg, getKillRegState(isKill))
192 .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags);
197 .addReg(DestReg)
199 .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags);
206 .addReg(BaseReg, RegState::Kill)
207 .addReg(DestReg, RegState::Kill)
208 .addImm((unsigned)Pred).addReg(PredReg).addReg(0)
212 .addReg(DestReg, RegState::Kill
[all...] |
| Thumb1FrameLowering.cpp | 170 .addReg(ARM::SP, RegState::Kill));
173 .addReg(ARM::R4, RegState::Kill)
177 .addReg(ARM::R4, RegState::Kill)
180 .addReg(ARM::R4, RegState::Kill));
191 .addReg(ARM::SP));
272 .addReg(ARM::R4));
276 .addReg(FramePtr));
299 .addReg(ARM::R3, RegState::Define);
304 .addReg(ARM::R3, RegState::Kill));
343 MIB.addReg(Reg, getKillRegState(isKill))
[all...] |
| /external/llvm/lib/Target/Blackfin/ |
| BlackfinInstrInfo.cpp | 106 .addReg(SrcReg, getKillRegState(KillSrc));
112 .addReg(SrcReg, getKillRegState(KillSrc))
120 .addReg(SrcReg, getKillRegState(KillSrc));
121 BuildMI(MBB, I, DL, get(BF::BITTGL), DestReg).addReg(DestReg).addImm(0);
126 .addReg(SrcReg, getKillRegState(KillSrc));
134 .addReg(SrcReg, getKillRegState(KillSrc)).addImm(0);
139 .addReg(SrcReg, getKillRegState(KillSrc));
147 .addReg(SrcReg, getKillRegState(KillSrc));
153 .addReg(SrcReg, getKillRegState(KillSrc));
181 .addReg(SrcReg, getKillRegState(isKill)
[all...] |
| BlackfinFrameLowering.cpp | 80 .addReg(BF::RETS, RegState::Kill);
82 .addReg(BF::FP, RegState::Kill);
84 .addReg(BF::SP);
87 .addReg(BF::SP, RegState::Kill)
88 .addReg(BF::P1, RegState::Kill);
|
| BlackfinRegisterInfo.cpp | 98 .addReg(Reg) // No kill on two-addr operand
109 .addReg(Reg, RegState::Kill)
110 .addReg(ScratchReg, RegState::Kill);
116 .addReg(Reg, RegState::Kill)
117 .addReg(ScratchReg, RegState::Kill);
146 .addReg(Reg, RegState::ImplicitDefine);
150 .addReg(Reg, RegState::ImplicitKill)
151 .addReg(Reg, RegState::ImplicitDefine);
271 .addReg(ScratchReg, RegState::Kill)
272 .addReg(BaseReg)
[all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreRegisterInfo.cpp | 240 .addReg(FrameReg)
241 .addReg(ScratchReg, RegState::Kill);
245 .addReg(Reg, getKillRegState(isKill))
246 .addReg(FrameReg)
247 .addReg(ScratchReg, RegState::Kill);
251 .addReg(FrameReg)
252 .addReg(ScratchReg, RegState::Kill);
261 .addReg(FrameReg)
266 .addReg(Reg, getKillRegState(isKill))
267 .addReg(FrameReg
[all...] |
| /external/llvm/lib/CodeGen/ |
| ScheduleDAGEmit.cpp | 55 .addReg(VRI->second);
64 .addReg(I->getReg());
|
| /external/llvm/lib/Target/MSP430/ |
| MSP430FrameLowering.cpp | 67 .addReg(MSP430::FPW, RegState::Kill);
71 .addReg(MSP430::SPW);
99 .addReg(MSP430::SPW).addImm(NumBytes);
157 TII.get(MSP430::MOV16rr), MSP430::SPW).addReg(MSP430::FPW);
162 .addReg(MSP430::SPW).addImm(CSSize);
171 .addReg(MSP430::SPW).addImm(NumBytes);
200 .addReg(Reg, RegState::Kill);
|
| /external/llvm/lib/Target/Mips/ |
| MipsFrameLowering.cpp | 130 BuildMI(MBB, I, DL, TII->get(Mips::ADDu), Mips::AT).addReg(OrigReg)
131 .addReg(Mips::AT);
170 .addReg(RegInfo->getPICCallReg());
184 .addReg(NewReg).addImm(NewImm);
245 .addReg(Mips::SP).addReg(Mips::ZERO);
293 .addReg(Mips::FP).addReg(Mips::ZERO);
301 .addReg(NewReg).addImm(NewImm);
|
| MipsExpandPseudo.cpp | 97 BuildMI(MBB, I, dl, Mtc1Tdd, *SubReg).addReg(LoReg);
98 BuildMI(MBB, I, dl, Mtc1Tdd, *(SubReg + 1)).addReg(HiReg);
110 BuildMI(MBB, I, dl, Mfc1Tdd, DstReg).addReg(*(SubReg + N));
|
