| /external/llvm/lib/Target/X86/InstPrinter/ |
| X86InstComments.cpp | 37 Src1Name = getRegName(MI->getOperand(1).getReg());
38 Src2Name = getRegName(MI->getOperand(2).getReg());
39 DecodeINSERTPSMask(MI->getOperand(3).getImm(), ShuffleMask);
43 Src2Name = getRegName(MI->getOperand(2).getReg());
44 Src1Name = getRegName(MI->getOperand(0).getReg());
49 Src2Name = getRegName(MI->getOperand(2).getReg());
50 Src1Name = getRegName(MI->getOperand(0).getReg());
55 Src1Name = getRegName(MI->getOperand(1).getReg());
58 DestName = getRegName(MI->getOperand(0).getReg());
59 DecodePSHUFMask(4, MI->getOperand(MI->getNumOperands()-1).getImm()
[all...] |
| X86ATTInstPrinter.cpp | 61 switch (MI->getOperand(Op).getImm()) {
80 const MCOperand &Op = MI->getOperand(OpNo);
92 const MCOperand &Op = MI->getOperand(OpNo);
110 const MCOperand &BaseReg = MI->getOperand(Op);
111 const MCOperand &IndexReg = MI->getOperand(Op+2);
112 const MCOperand &DispSpec = MI->getOperand(Op+3);
113 const MCOperand &SegReg = MI->getOperand(Op+4);
138 unsigned ScaleVal = MI->getOperand(Op+1).getImm();
|
| X86IntelInstPrinter.cpp | 51 switch (MI->getOperand(Op).getImm()) {
68 const MCOperand &Op = MI->getOperand(OpNo);
84 const MCOperand &Op = MI->getOperand(OpNo);
97 const MCOperand &BaseReg = MI->getOperand(Op);
98 unsigned ScaleVal = MI->getOperand(Op+1).getImm();
99 const MCOperand &IndexReg = MI->getOperand(Op+2);
100 const MCOperand &DispSpec = MI->getOperand(Op+3);
101 const MCOperand &SegReg = MI->getOperand(Op+4);
|
| /external/llvm/lib/Transforms/InstCombine/ |
| InstCombineVectorOps.cpp | 26 Constant *Op0 = C->getOperand(0);
28 if (C->getOperand(i) != Op0)
38 isa<ConstantInt>(I->getOperand(2)))
44 (CheapToScalarize(BO->getOperand(0), isConstant) ||
45 CheapToScalarize(BO->getOperand(1), isConstant)))
49 (CheapToScalarize(CI->getOperand(0), isConstant) ||
50 CheapToScalarize(CI->getOperand(1), isConstant)))
60 if (isa<ConstantAggregateZero>(SVI->getOperand(2)))
62 if (isa<UndefValue>(SVI->getOperand(2)))
66 const ConstantVector *CP = cast<ConstantVector>(SVI->getOperand(2))
[all...] |
| InstCombineSelect.cpp | 32 LHS = ICI->getOperand(0);
33 RHS = ICI->getOperand(1);
36 if (SI->getTrueValue() == ICI->getOperand(0) &&
37 SI->getFalseValue() == ICI->getOperand(1)) {
52 if (SI->getTrueValue() == ICI->getOperand(1) &&
53 SI->getFalseValue() == ICI->getOperand(0)) {
130 if (TI->getOperand(0)->getType() != FI->getOperand(0)->getType())
137 Value *NewSI = Builder->CreateSelect(SI.getCondition(), TI->getOperand(0),
138 FI->getOperand(0), SI.getName()+".v")
[all...] |
| InstCombineCasts.cpp | 42 if (ConstantInt *RHS = dyn_cast<ConstantInt>(I->getOperand(1))) {
47 return I->getOperand(0);
54 return I->getOperand(0);
62 DecomposeSimpleLinearExpr(I->getOperand(0), SubScale, Offset);
111 DecomposeSimpleLinearExpr(AI.getOperand(0), ArraySizeScale, ArrayOffset);
181 Value *LHS = EvaluateInDifferentType(I->getOperand(0), Ty, isSigned);
182 Value *RHS = EvaluateInDifferentType(I->getOperand(1), Ty, isSigned);
192 if (I->getOperand(0)->getType() == Ty)
193 return I->getOperand(0);
197 Res = CastInst::CreateIntegerCast(I->getOperand(0), Ty
[all...] |
| InstCombineShifts.cpp | 23 assert(I.getOperand(1)->getType() == I.getOperand(0)->getType());
24 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1);
92 if (MaskedValueIsZero(I->getOperand(0),
95 return CanEvaluateTruncated(I->getOperand(0), Ty);
112 return CanEvaluateShifted(I->getOperand(0), NumBits, isLeftShift, IC) &&
113 CanEvaluateShifted(I->getOperand(1), NumBits, isLeftShift, IC);
117 CI = dyn_cast<ConstantInt>(I->getOperand(1));
132 if (MaskedValueIsZero(I->getOperand(0)
[all...] |
| InstCombineSimplifyDemanded.cpp | 33 ConstantInt *OpC = dyn_cast<ConstantInt>(I->getOperand(OpNo));
159 ComputeMaskedBits(I->getOperand(1), DemandedMask,
161 ComputeMaskedBits(I->getOperand(0), DemandedMask & ~RHSKnownZero,
169 return I->getOperand(0);
172 return I->getOperand(1);
183 ComputeMaskedBits(I->getOperand(1), DemandedMask,
185 ComputeMaskedBits(I->getOperand(0), DemandedMask & ~RHSKnownOne,
193 return I->getOperand(0);
196 return I->getOperand(1);
202 return I->getOperand(0)
[all...] |
| InstCombineAndOrXor.cpp | 198 Value *X = Op->getOperand(0);
322 Value *ShVal = Op->getOperand(0);
412 !isa<ConstantInt>(LHSI->getOperand(1))) return 0;
414 ConstantInt *N = cast<ConstantInt>(LHSI->getOperand(1));
449 return Builder->CreateSub(LHSI->getOperand(0), RHS, "fold");
450 return Builder->CreateAdd(LHSI->getOperand(0), RHS, "fold");
572 if (LHS->getOperand(0)->getType() != RHS->getOperand(0)->getType()) return 0;
574 if (LHS->getOperand(0)->getType()->isVectorTy()) return 0;
582 Value *L1 = LHS->getOperand(0)
[all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreISelDAGToDAG.cpp | 100 if ((FIN = dyn_cast<FrameIndexSDNode>(Addr.getOperand(0)))
101 && (CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1)))
115 Base = Addr.getOperand(0);
121 if ((Addr.getOperand(0).getOpcode() == XCoreISD::DPRelativeWrapper)
122 && (CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1)))
125 Base = Addr.getOperand(0).getOperand(0);
136 Base = Addr.getOperand(0);
142 if ((Addr.getOperand(0).getOpcode() == XCoreISD::CPRelativeWrapper)
143 && (CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))
[all...] |
| /external/llvm/lib/CodeGen/ |
| AntiDepBreaker.h | 64 if (MI && MI->getOperand(0).isReg() && MI->getOperand(0).getReg() == OldReg)
65 MI->getOperand(0).setReg(NewReg);
|
| /external/llvm/lib/Target/PTX/ |
| PTXRegisterInfo.cpp | 48 while (!MI.getOperand(Index).isFI()) {
54 int FrameIndex = MI.getOperand(Index).getIndex();
71 //MI.getOperand(Index).ChangeToRegister(Reg, false);
72 MI.getOperand(Index).ChangeToImmediate(FrameIndex);
73 //MI.getOperand(Index) = ESOp;
|
| PTXMCInstLower.cpp | 27 const MachineOperand &MO = MI->getOperand(i);
|
| /external/llvm/lib/VMCore/ |
| IntrinsicInst.cpp | 37 return CE->getOperand(0);
58 return MD->getOperand(0);
68 return cast<MDNode>(getArgOperand(0))->getOperand(0);
72 return cast<MDNode>(getArgOperand(0))->getOperand(0);
|
| /external/llvm/lib/Target/CellSPU/ |
| SPUAsmPrinter.cpp | 64 const MachineOperand &MO = MI->getOperand(OpNo);
85 unsigned int value = MI->getOperand(OpNo).getImm();
93 char value = MI->getOperand(OpNo).getImm();
103 O << (short) MI->getOperand(OpNo).getImm();
109 O << (unsigned short)MI->getOperand(OpNo).getImm();
117 const MachineOperand &MO = MI->getOperand(OpNo);
125 unsigned int value = MI->getOperand(OpNo).getImm();
133 short value = (short) (((int) MI->getOperand(OpNo).getImm() << 16)
143 short value = (short) (((int) MI->getOperand(OpNo).getImm() << 16)
152 assert(MI->getOperand(OpNo).isImm() &
[all...] |
| /external/llvm/lib/Target/PowerPC/InstPrinter/ |
| PPCInstPrinter.cpp | 38 unsigned char SH = MI->getOperand(2).getImm();
39 unsigned char MB = MI->getOperand(3).getImm();
40 unsigned char ME = MI->getOperand(4).getImm();
61 MI->getOperand(1).getReg() == MI->getOperand(2).getReg()) {
71 unsigned char SH = MI->getOperand(2).getImm();
72 unsigned char ME = MI->getOperand(3).getImm();
94 unsigned Code = MI->getOperand(OpNo).getImm();
119 char Value = MI->getOperand(OpNo).getImm();
126 unsigned char Value = MI->getOperand(OpNo).getImm()
[all...] |
| /external/llvm/lib/Target/ARM/InstPrinter/ |
| ARMInstPrinter.cpp | 60 const MCOperand &Dst = MI->getOperand(0);
61 const MCOperand &MO1 = MI->getOperand(1);
62 const MCOperand &MO2 = MI->getOperand(2);
63 const MCOperand &MO3 = MI->getOperand(3);
80 const MCOperand &Dst = MI->getOperand(0);
81 const MCOperand &MO1 = MI->getOperand(1);
82 const MCOperand &MO2 = MI->getOperand(2);
104 MI->getOperand(0).getReg() == ARM::SP) {
114 if (Opcode == ARM::STR_PRE_IMM && MI->getOperand(2).getReg() == ARM::SP &&
115 MI->getOperand(3).getImm() == -4)
[all...] |
| /external/llvm/lib/Target/Alpha/ |
| AlphaLLRP.cpp | 70 if (MI->getOperand(2).getReg() == Alpha::R30) {
72 prev[0]->getOperand(2).getReg() == MI->getOperand(2).getReg()&&
73 prev[0]->getOperand(1).getImm() == MI->getOperand(1).getImm()){
83 && prev[1]->getOperand(2).getReg() ==
84 MI->getOperand(2).getReg()
85 && prev[1]->getOperand(1).getImm() ==
86 MI->getOperand(1).getImm()) {
98 && prev[2]->getOperand(2).getReg() ==
[all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcISelDAGToDAG.cpp | 85 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) {
88 dyn_cast<FrameIndexSDNode>(Addr.getOperand(0))) {
92 Base = Addr.getOperand(0);
98 if (Addr.getOperand(0).getOpcode() == SPISD::Lo) {
99 Base = Addr.getOperand(1);
100 Offset = Addr.getOperand(0).getOperand(0);
103 if (Addr.getOperand(1).getOpcode() == SPISD::Lo) {
104 Base = Addr.getOperand(0);
105 Offset = Addr.getOperand(1).getOperand(0)
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| DAGCombiner.cpp | 390 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1))
393 return isNegatibleForFree(Op.getOperand(1), LegalOperations, Depth+1);
406 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1))
409 return isNegatibleForFree(Op.getOperand(1), LegalOperations, Depth+1);
414 return isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1);
423 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0);
441 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1))
443 GetNegatedExpression(Op.getOperand(0), DAG,
445 Op.getOperand(1));
448 GetNegatedExpression(Op.getOperand(1), DAG
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsISelDAGToDAG.cpp | 128 Offset = Addr.getOperand(0);
144 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1));
149 (Addr.getOperand(0)))
152 Base = Addr.getOperand(0);
169 if ((Addr.getOperand(0).getOpcode() == MipsISD::Hi ||
170 Addr.getOperand(0).getOpcode() == ISD::LOAD) &&
171 Addr.getOperand(1).getOpcode() == MipsISD::Lo) {
172 SDValue LoVal = Addr.getOperand(1);
173 if (isa<ConstantPoolSDNode>(LoVal.getOperand(0)) ||
174 isa<GlobalAddressSDNode>(LoVal.getOperand(0)))
[all...] |
| /external/llvm/lib/MC/MCDisassembler/ |
| EDOperand.cpp | 138 result = Inst.Inst->getOperand(MCOpIndex).getImm();
142 unsigned reg = Inst.Inst->getOperand(MCOpIndex).getReg();
147 int64_t displacement = Inst.Inst->getOperand(MCOpIndex).getImm();
162 unsigned baseReg = Inst.Inst->getOperand(MCOpIndex).getReg();
163 uint64_t scaleAmount = Inst.Inst->getOperand(MCOpIndex+1).getImm();
164 unsigned indexReg = Inst.Inst->getOperand(MCOpIndex+2).getReg();
165 int64_t displacement = Inst.Inst->getOperand(MCOpIndex+3).getImm();
169 unsigned segmentReg = Inst.Inst->getOperand(MCOpIndex+4).getReg();
210 if (!Inst.Inst->getOperand(MCOpIndex).isImm())
213 result = Inst.Inst->getOperand(MCOpIndex).getImm()
[all...] |
| /external/llvm/lib/MC/ |
| MCInstrAnalysis.cpp | 19 int64_t Imm = Inst.getOperand(0).getImm();
|
| /external/llvm/include/llvm/Support/ |
| GetElementPtrTypeIterator.h | 59 return CT->getTypeAtIndex(getOperand());
66 Value *getOperand() const { return *OpIt; }
70 CurTy = CT->getTypeAtIndex(getOperand());
86 return gep_type_iterator::begin(GEP->getOperand(0)->getType(),
93 return gep_type_iterator::begin(GEP.getOperand(0)->getType(),
|
| /external/llvm/lib/Target/MSP430/InstPrinter/ |
| MSP430InstPrinter.cpp | 36 const MCOperand &Op = MI->getOperand(OpNo);
48 const MCOperand &Op = MI->getOperand(OpNo);
62 const MCOperand &Base = MI->getOperand(OpNo);
63 const MCOperand &Disp = MI->getOperand(OpNo+1);
90 unsigned CC = MI->getOperand(OpNo).getImm();
|
