| /external/llvm/lib/Target/PTX/ |
| PTXMFInfoExtract.cpp | 58 const TargetRegisterClass *TRC = MRI.getRegClass(Reg);
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| PTXInstrInfo.cpp | 53 //assert(MRI.getRegClass(SrcReg) == MRI.getRegClass(DstReg) &&
57 if (map[i].cls == MRI.getRegClass(DstReg)) {
166 if (!MO.isReg() || RI.getRegClass(MO.getReg()) != &PTX::RegPredRegClass)
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| /external/llvm/lib/CodeGen/ |
| AllocationOrder.cpp | 29 const TargetRegisterClass *RC = VRM.getRegInfo().getRegClass(VirtReg);
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| RegisterCoalescer.cpp | 273 Dst = TRI.getMatchingSuperReg(Dst, SrcSub, MRI.getRegClass(Src));
276 } else if (!MRI.getRegClass(Src)->contains(Dst)) {
289 const TargetRegisterClass *SrcRC = MRI.getRegClass(Src);
290 const TargetRegisterClass *DstRC = MRI.getRegClass(Dst);
306 const TargetRegisterClass *SrcRC = MRI.getRegClass(Src);
307 const TargetRegisterClass *DstRC = MRI.getRegClass(Dst);
717 !MRI->constrainRegClass(IntB.reg, MRI->getRegClass(IntA.reg)))
826 const TargetRegisterClass *RC = TII->getRegClass(MCID, 0, TRI);
828 if (MRI->getRegClass(DstReg) != RC)
[all...] |
| MachineRegisterInfo.cpp | 54 const TargetRegisterClass *OldRC = getRegClass(Reg);
69 const TargetRegisterClass *OldRC = getRegClass(Reg);
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| Spiller.cpp | 88 const TargetRegisterClass *trc = mri->getRegClass(li->reg);
222 const TargetRegisterClass *RC = mf->getRegInfo().getRegClass(LRE.getReg());
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| MachineSink.cpp | 121 const TargetRegisterClass *SRC = MRI->getRegClass(SrcReg);
122 const TargetRegisterClass *DRC = MRI->getRegClass(DstReg);
469 if (!TII->isSafeToMoveRegClassDefs(MRI->getRegClass(Reg)))
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| PeepholeOptimizer.cpp | 235 const TargetRegisterClass *RC = MRI->getRegClass(SrcReg);
319 if (MRI->getRegClass(SrcSrc) != MRI->getRegClass(Def))
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| VirtRegMap.cpp | 133 const TargetRegisterClass* RC = MF->getRegInfo().getRegClass(virtReg);
365 << MRI.getRegClass(Reg)->getName() << "\n";
373 << "] " << MRI.getRegClass(Reg)->getName() << "\n";
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| CalcSpillWeights.cpp | 79 const TargetRegisterClass *rc = mri.getRegClass(reg);
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| OptimizePHIs.cpp | 169 if (!MRI->constrainRegClass(SingleValReg, MRI->getRegClass(OldReg)))
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| LiveRangeEdit.cpp | 36 unsigned VReg = MRI.createVirtualRegister(MRI.getRegClass(OldReg));
327 << MRI.getRegClass(LI.reg)->getName() << '\n');
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| RegAllocBasic.cpp | 318 << MRI->getRegClass(VirtReg->reg)->getName()
339 RegClassInfo.getOrder(MRI->getRegClass(VirtReg->reg)).front());
489 RegClassInfo.getOrder(MRI->getRegClass(VirtReg.reg));
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| TwoAddressInstructionPass.cpp | [all...] |
| TargetInstrInfoImpl.cpp | 248 const TargetRegisterClass *RC = MRI.getRegClass(FoldReg);
253 if (RC->hasSubClassEq(MRI.getRegClass(LiveReg)))
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| UnreachableBlockElim.cpp | 201 MRI.constrainRegClass(Input, MRI.getRegClass(Output));
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| InlineSpiller.cpp | 726 MRI.getRegClass(SVI.SpillReg), &TRI);
[all...] |
| /external/llvm/lib/Target/Blackfin/ |
| BlackfinISelDAGToDAG.cpp | 157 TII.getRegClass(DefMCID, UI.getUse().getResNo(), TRI);
163 TII.getRegClass(UseMCID, UseMCID.getNumDefs()+UI.getOperandNo(), TRI);
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| /external/llvm/lib/Target/ |
| TargetInstrInfo.cpp | 31 TargetInstrInfo::getRegClass(const MCInstrDesc &MCID, unsigned OpNum,
45 return TRI->getRegClass(RegClass);
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| TargetRegisterInfo.cpp | 118 return getRegClass(Base + CountTrailingZeros_32(Common));
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| InstrEmitter.cpp | 118 RC = TII->getRegClass(II, i+II.getNumDefs(), TRI);
142 DstRC = MRI->getRegClass(VRBase);
199 const TargetRegisterClass *RC = TII->getRegClass(II, i, TRI);
217 const TargetRegisterClass *RegRC = MRI->getRegClass(Reg);
296 DstRC = TII->getRegClass(*II, IIOpNum, TRI);
402 const TargetRegisterClass *VRC = MRI->getRegClass(VReg);
509 if (VRBase == 0 || !SRC->hasSubClassEq(MRI->getRegClass(VRBase)))
549 const TargetRegisterClass *DstRC = TRI->getRegClass(DstRCIdx);
566 const TargetRegisterClass *RC = TRI->getRegClass(DstRCIdx);
579 const TargetRegisterClass *TRC = MRI->getRegClass(SubReg)
[all...] |
| /external/llvm/include/llvm/MC/ |
| MCRegisterInfo.h | 297 /// getRegClass - Returns the register class associated with the enumeration
299 const MCRegisterClass getRegClass(unsigned i) const {
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| /external/llvm/utils/TableGen/ |
| CodeGenTarget.h | 111 return *getRegBank().getRegClass(R);
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| CodeGenRegisters.h | 278 CodeGenRegisterClass *getRegClass(Record*);
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| /external/llvm/include/llvm/CodeGen/ |
| MachineRegisterInfo.h | 178 /// constrainRegClass(ToReg, getRegClass(FromReg))
217 /// getRegClass - Return the register class of the specified virtual register.
219 const TargetRegisterClass *getRegClass(unsigned Reg) const {
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