1 //===- EDEmitter.cpp - Generate instruction descriptions for ED -*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This tablegen backend is responsible for emitting a description of each 11 // instruction in a format that the enhanced disassembler can use to tokenize 12 // and parse instructions. 13 // 14 //===----------------------------------------------------------------------===// 15 16 #include "EDEmitter.h" 17 18 #include "AsmWriterInst.h" 19 #include "CodeGenTarget.h" 20 21 #include "llvm/TableGen/Record.h" 22 #include "llvm/MC/EDInstInfo.h" 23 #include "llvm/Support/ErrorHandling.h" 24 #include "llvm/Support/Format.h" 25 #include "llvm/Support/raw_ostream.h" 26 27 #include <string> 28 #include <vector> 29 30 using namespace llvm; 31 32 /////////////////////////////////////////////////////////// 33 // Support classes for emitting nested C data structures // 34 /////////////////////////////////////////////////////////// 35 36 namespace { 37 38 class EnumEmitter { 39 private: 40 std::string Name; 41 std::vector<std::string> Entries; 42 public: 43 EnumEmitter(const char *N) : Name(N) { 44 } 45 int addEntry(const char *e) { 46 Entries.push_back(std::string(e)); 47 return Entries.size() - 1; 48 } 49 void emit(raw_ostream &o, unsigned int &i) { 50 o.indent(i) << "enum " << Name.c_str() << " {" << "\n"; 51 i += 2; 52 53 unsigned int index = 0; 54 unsigned int numEntries = Entries.size(); 55 for (index = 0; index < numEntries; ++index) { 56 o.indent(i) << Entries[index]; 57 if (index < (numEntries - 1)) 58 o << ","; 59 o << "\n"; 60 } 61 62 i -= 2; 63 o.indent(i) << "};" << "\n"; 64 } 65 66 void emitAsFlags(raw_ostream &o, unsigned int &i) { 67 o.indent(i) << "enum " << Name.c_str() << " {" << "\n"; 68 i += 2; 69 70 unsigned int index = 0; 71 unsigned int numEntries = Entries.size(); 72 unsigned int flag = 1; 73 for (index = 0; index < numEntries; ++index) { 74 o.indent(i) << Entries[index] << " = " << format("0x%x", flag); 75 if (index < (numEntries - 1)) 76 o << ","; 77 o << "\n"; 78 flag <<= 1; 79 } 80 81 i -= 2; 82 o.indent(i) << "};" << "\n"; 83 } 84 }; 85 86 class ConstantEmitter { 87 public: 88 virtual ~ConstantEmitter() { } 89 virtual void emit(raw_ostream &o, unsigned int &i) = 0; 90 }; 91 92 class LiteralConstantEmitter : public ConstantEmitter { 93 private: 94 bool IsNumber; 95 union { 96 int Number; 97 const char* String; 98 }; 99 public: 100 LiteralConstantEmitter(int number = 0) : 101 IsNumber(true), 102 Number(number) { 103 } 104 void set(const char *string) { 105 IsNumber = false; 106 Number = 0; 107 String = string; 108 } 109 bool is(const char *string) { 110 return !strcmp(String, string); 111 } 112 void emit(raw_ostream &o, unsigned int &i) { 113 if (IsNumber) 114 o << Number; 115 else 116 o << String; 117 } 118 }; 119 120 class CompoundConstantEmitter : public ConstantEmitter { 121 private: 122 unsigned int Padding; 123 std::vector<ConstantEmitter *> Entries; 124 public: 125 CompoundConstantEmitter(unsigned int padding = 0) : Padding(padding) { 126 } 127 CompoundConstantEmitter &addEntry(ConstantEmitter *e) { 128 Entries.push_back(e); 129 130 return *this; 131 } 132 ~CompoundConstantEmitter() { 133 while (Entries.size()) { 134 ConstantEmitter *entry = Entries.back(); 135 Entries.pop_back(); 136 delete entry; 137 } 138 } 139 void emit(raw_ostream &o, unsigned int &i) { 140 o << "{" << "\n"; 141 i += 2; 142 143 unsigned int index; 144 unsigned int numEntries = Entries.size(); 145 146 unsigned int numToPrint; 147 148 if (Padding) { 149 if (numEntries > Padding) { 150 fprintf(stderr, "%u entries but %u padding\n", numEntries, Padding); 151 llvm_unreachable("More entries than padding"); 152 } 153 numToPrint = Padding; 154 } else { 155 numToPrint = numEntries; 156 } 157 158 for (index = 0; index < numToPrint; ++index) { 159 o.indent(i); 160 if (index < numEntries) 161 Entries[index]->emit(o, i); 162 else 163 o << "-1"; 164 165 if (index < (numToPrint - 1)) 166 o << ","; 167 o << "\n"; 168 } 169 170 i -= 2; 171 o.indent(i) << "}"; 172 } 173 }; 174 175 class FlagsConstantEmitter : public ConstantEmitter { 176 private: 177 std::vector<std::string> Flags; 178 public: 179 FlagsConstantEmitter() { 180 } 181 FlagsConstantEmitter &addEntry(const char *f) { 182 Flags.push_back(std::string(f)); 183 return *this; 184 } 185 void emit(raw_ostream &o, unsigned int &i) { 186 unsigned int index; 187 unsigned int numFlags = Flags.size(); 188 if (numFlags == 0) 189 o << "0"; 190 191 for (index = 0; index < numFlags; ++index) { 192 o << Flags[index].c_str(); 193 if (index < (numFlags - 1)) 194 o << " | "; 195 } 196 } 197 }; 198 } 199 200 EDEmitter::EDEmitter(RecordKeeper &R) : Records(R) { 201 } 202 203 /// populateOperandOrder - Accepts a CodeGenInstruction and generates its 204 /// AsmWriterInst for the desired assembly syntax, giving an ordered list of 205 /// operands in the order they appear in the printed instruction. Then, for 206 /// each entry in that list, determines the index of the same operand in the 207 /// CodeGenInstruction, and emits the resulting mapping into an array, filling 208 /// in unused slots with -1. 209 /// 210 /// @arg operandOrder - The array that will be populated with the operand 211 /// mapping. Each entry will contain -1 (invalid index 212 /// into the operands present in the AsmString) or a number 213 /// representing an index in the operand descriptor array. 214 /// @arg inst - The instruction to use when looking up the operands 215 /// @arg syntax - The syntax to use, according to LLVM's enumeration 216 void populateOperandOrder(CompoundConstantEmitter *operandOrder, 217 const CodeGenInstruction &inst, 218 unsigned syntax) { 219 unsigned int numArgs = 0; 220 221 AsmWriterInst awInst(inst, syntax, -1, -1); 222 223 std::vector<AsmWriterOperand>::iterator operandIterator; 224 225 for (operandIterator = awInst.Operands.begin(); 226 operandIterator != awInst.Operands.end(); 227 ++operandIterator) { 228 if (operandIterator->OperandType == 229 AsmWriterOperand::isMachineInstrOperand) { 230 operandOrder->addEntry( 231 new LiteralConstantEmitter(operandIterator->CGIOpNo)); 232 numArgs++; 233 } 234 } 235 } 236 237 ///////////////////////////////////////////////////// 238 // Support functions for handling X86 instructions // 239 ///////////////////////////////////////////////////// 240 241 #define SET(flag) { type->set(flag); return 0; } 242 243 #define REG(str) if (name == str) SET("kOperandTypeRegister"); 244 #define MEM(str) if (name == str) SET("kOperandTypeX86Memory"); 245 #define LEA(str) if (name == str) SET("kOperandTypeX86EffectiveAddress"); 246 #define IMM(str) if (name == str) SET("kOperandTypeImmediate"); 247 #define PCR(str) if (name == str) SET("kOperandTypeX86PCRelative"); 248 249 /// X86TypeFromOpName - Processes the name of a single X86 operand (which is 250 /// actually its type) and translates it into an operand type 251 /// 252 /// @arg flags - The type object to set 253 /// @arg name - The name of the operand 254 static int X86TypeFromOpName(LiteralConstantEmitter *type, 255 const std::string &name) { 256 REG("GR8"); 257 REG("GR8_NOREX"); 258 REG("GR16"); 259 REG("GR16_NOAX"); 260 REG("GR32"); 261 REG("GR32_NOAX"); 262 REG("GR32_NOREX"); 263 REG("GR32_TC"); 264 REG("FR32"); 265 REG("RFP32"); 266 REG("GR64"); 267 REG("GR64_NOAX"); 268 REG("GR64_TC"); 269 REG("FR64"); 270 REG("VR64"); 271 REG("RFP64"); 272 REG("RFP80"); 273 REG("VR128"); 274 REG("VR256"); 275 REG("RST"); 276 REG("SEGMENT_REG"); 277 REG("DEBUG_REG"); 278 REG("CONTROL_REG"); 279 280 IMM("i8imm"); 281 IMM("i16imm"); 282 IMM("i16i8imm"); 283 IMM("i32imm"); 284 IMM("i32i8imm"); 285 IMM("u32u8imm"); 286 IMM("i64imm"); 287 IMM("i64i8imm"); 288 IMM("i64i32imm"); 289 IMM("SSECC"); 290 291 // all R, I, R, I, R 292 MEM("i8mem"); 293 MEM("i8mem_NOREX"); 294 MEM("i16mem"); 295 MEM("i32mem"); 296 MEM("i32mem_TC"); 297 MEM("f32mem"); 298 MEM("ssmem"); 299 MEM("opaque32mem"); 300 MEM("opaque48mem"); 301 MEM("i64mem"); 302 MEM("i64mem_TC"); 303 MEM("f64mem"); 304 MEM("sdmem"); 305 MEM("f80mem"); 306 MEM("opaque80mem"); 307 MEM("i128mem"); 308 MEM("i256mem"); 309 MEM("f128mem"); 310 MEM("f256mem"); 311 MEM("opaque512mem"); 312 313 // all R, I, R, I 314 LEA("lea32mem"); 315 LEA("lea64_32mem"); 316 LEA("lea64mem"); 317 318 // all I 319 PCR("i16imm_pcrel"); 320 PCR("i32imm_pcrel"); 321 PCR("i64i32imm_pcrel"); 322 PCR("brtarget8"); 323 PCR("offset8"); 324 PCR("offset16"); 325 PCR("offset32"); 326 PCR("offset64"); 327 PCR("brtarget"); 328 PCR("uncondbrtarget"); 329 PCR("bltarget"); 330 331 // all I, ARM mode only, conditional/unconditional 332 PCR("br_target"); 333 PCR("bl_target"); 334 return 1; 335 } 336 337 #undef REG 338 #undef MEM 339 #undef LEA 340 #undef IMM 341 #undef PCR 342 343 #undef SET 344 345 /// X86PopulateOperands - Handles all the operands in an X86 instruction, adding 346 /// the appropriate flags to their descriptors 347 /// 348 /// @operandFlags - A reference the array of operand flag objects 349 /// @inst - The instruction to use as a source of information 350 static void X86PopulateOperands( 351 LiteralConstantEmitter *(&operandTypes)[EDIS_MAX_OPERANDS], 352 const CodeGenInstruction &inst) { 353 if (!inst.TheDef->isSubClassOf("X86Inst")) 354 return; 355 356 unsigned int index; 357 unsigned int numOperands = inst.Operands.size(); 358 359 for (index = 0; index < numOperands; ++index) { 360 const CGIOperandList::OperandInfo &operandInfo = inst.Operands[index]; 361 Record &rec = *operandInfo.Rec; 362 363 if (X86TypeFromOpName(operandTypes[index], rec.getName()) && 364 !rec.isSubClassOf("PointerLikeRegClass")) { 365 errs() << "Operand type: " << rec.getName().c_str() << "\n"; 366 errs() << "Operand name: " << operandInfo.Name.c_str() << "\n"; 367 errs() << "Instruction name: " << inst.TheDef->getName().c_str() << "\n"; 368 llvm_unreachable("Unhandled type"); 369 } 370 } 371 } 372 373 /// decorate1 - Decorates a named operand with a new flag 374 /// 375 /// @operandFlags - The array of operand flag objects, which don't have names 376 /// @inst - The CodeGenInstruction, which provides a way to translate 377 /// between names and operand indices 378 /// @opName - The name of the operand 379 /// @flag - The name of the flag to add 380 static inline void decorate1( 381 FlagsConstantEmitter *(&operandFlags)[EDIS_MAX_OPERANDS], 382 const CodeGenInstruction &inst, 383 const char *opName, 384 const char *opFlag) { 385 unsigned opIndex; 386 387 opIndex = inst.Operands.getOperandNamed(std::string(opName)); 388 389 operandFlags[opIndex]->addEntry(opFlag); 390 } 391 392 #define DECORATE1(opName, opFlag) decorate1(operandFlags, inst, opName, opFlag) 393 394 #define MOV(source, target) { \ 395 instType.set("kInstructionTypeMove"); \ 396 DECORATE1(source, "kOperandFlagSource"); \ 397 DECORATE1(target, "kOperandFlagTarget"); \ 398 } 399 400 #define BRANCH(target) { \ 401 instType.set("kInstructionTypeBranch"); \ 402 DECORATE1(target, "kOperandFlagTarget"); \ 403 } 404 405 #define PUSH(source) { \ 406 instType.set("kInstructionTypePush"); \ 407 DECORATE1(source, "kOperandFlagSource"); \ 408 } 409 410 #define POP(target) { \ 411 instType.set("kInstructionTypePop"); \ 412 DECORATE1(target, "kOperandFlagTarget"); \ 413 } 414 415 #define CALL(target) { \ 416 instType.set("kInstructionTypeCall"); \ 417 DECORATE1(target, "kOperandFlagTarget"); \ 418 } 419 420 #define RETURN() { \ 421 instType.set("kInstructionTypeReturn"); \ 422 } 423 424 /// X86ExtractSemantics - Performs various checks on the name of an X86 425 /// instruction to determine what sort of an instruction it is and then adds 426 /// the appropriate flags to the instruction and its operands 427 /// 428 /// @arg instType - A reference to the type for the instruction as a whole 429 /// @arg operandFlags - A reference to the array of operand flag object pointers 430 /// @arg inst - A reference to the original instruction 431 static void X86ExtractSemantics( 432 LiteralConstantEmitter &instType, 433 FlagsConstantEmitter *(&operandFlags)[EDIS_MAX_OPERANDS], 434 const CodeGenInstruction &inst) { 435 const std::string &name = inst.TheDef->getName(); 436 437 if (name.find("MOV") != name.npos) { 438 if (name.find("MOV_V") != name.npos) { 439 // ignore (this is a pseudoinstruction) 440 } else if (name.find("MASK") != name.npos) { 441 // ignore (this is a masking move) 442 } else if (name.find("r0") != name.npos) { 443 // ignore (this is a pseudoinstruction) 444 } else if (name.find("PS") != name.npos || 445 name.find("PD") != name.npos) { 446 // ignore (this is a shuffling move) 447 } else if (name.find("MOVS") != name.npos) { 448 // ignore (this is a string move) 449 } else if (name.find("_F") != name.npos) { 450 // TODO handle _F moves to ST(0) 451 } else if (name.find("a") != name.npos) { 452 // TODO handle moves to/from %ax 453 } else if (name.find("CMOV") != name.npos) { 454 MOV("src2", "dst"); 455 } else if (name.find("PC") != name.npos) { 456 MOV("label", "reg") 457 } else { 458 MOV("src", "dst"); 459 } 460 } 461 462 if (name.find("JMP") != name.npos || 463 name.find("J") == 0) { 464 if (name.find("FAR") != name.npos && name.find("i") != name.npos) { 465 BRANCH("off"); 466 } else { 467 BRANCH("dst"); 468 } 469 } 470 471 if (name.find("PUSH") != name.npos) { 472 if (name.find("CS") != name.npos || 473 name.find("DS") != name.npos || 474 name.find("ES") != name.npos || 475 name.find("FS") != name.npos || 476 name.find("GS") != name.npos || 477 name.find("SS") != name.npos) { 478 instType.set("kInstructionTypePush"); 479 // TODO add support for fixed operands 480 } else if (name.find("F") != name.npos) { 481 // ignore (this pushes onto the FP stack) 482 } else if (name.find("A") != name.npos) { 483 // ignore (pushes all GP registoers onto the stack) 484 } else if (name[name.length() - 1] == 'm') { 485 PUSH("src"); 486 } else if (name.find("i") != name.npos) { 487 PUSH("imm"); 488 } else { 489 PUSH("reg"); 490 } 491 } 492 493 if (name.find("POP") != name.npos) { 494 if (name.find("POPCNT") != name.npos) { 495 // ignore (not a real pop) 496 } else if (name.find("CS") != name.npos || 497 name.find("DS") != name.npos || 498 name.find("ES") != name.npos || 499 name.find("FS") != name.npos || 500 name.find("GS") != name.npos || 501 name.find("SS") != name.npos) { 502 instType.set("kInstructionTypePop"); 503 // TODO add support for fixed operands 504 } else if (name.find("F") != name.npos) { 505 // ignore (this pops from the FP stack) 506 } else if (name.find("A") != name.npos) { 507 // ignore (pushes all GP registoers onto the stack) 508 } else if (name[name.length() - 1] == 'm') { 509 POP("dst"); 510 } else { 511 POP("reg"); 512 } 513 } 514 515 if (name.find("CALL") != name.npos) { 516 if (name.find("ADJ") != name.npos) { 517 // ignore (not a call) 518 } else if (name.find("SYSCALL") != name.npos) { 519 // ignore (doesn't go anywhere we know about) 520 } else if (name.find("VMCALL") != name.npos) { 521 // ignore (rather different semantics than a regular call) 522 } else if (name.find("FAR") != name.npos && name.find("i") != name.npos) { 523 CALL("off"); 524 } else { 525 CALL("dst"); 526 } 527 } 528 529 if (name.find("RET") != name.npos) { 530 RETURN(); 531 } 532 } 533 534 #undef MOV 535 #undef BRANCH 536 #undef PUSH 537 #undef POP 538 #undef CALL 539 #undef RETURN 540 541 ///////////////////////////////////////////////////// 542 // Support functions for handling ARM instructions // 543 ///////////////////////////////////////////////////// 544 545 #define SET(flag) { type->set(flag); return 0; } 546 547 #define REG(str) if (name == str) SET("kOperandTypeRegister"); 548 #define IMM(str) if (name == str) SET("kOperandTypeImmediate"); 549 550 #define MISC(str, type) if (name == str) SET(type); 551 552 /// ARMFlagFromOpName - Processes the name of a single ARM operand (which is 553 /// actually its type) and translates it into an operand type 554 /// 555 /// @arg type - The type object to set 556 /// @arg name - The name of the operand 557 static int ARMFlagFromOpName(LiteralConstantEmitter *type, 558 const std::string &name) { 559 REG("GPR"); 560 REG("rGPR"); 561 REG("GPRnopc"); 562 REG("GPRsp"); 563 REG("tcGPR"); 564 REG("cc_out"); 565 REG("s_cc_out"); 566 REG("tGPR"); 567 REG("DPR"); 568 REG("DPR_VFP2"); 569 REG("DPR_8"); 570 REG("SPR"); 571 REG("QPR"); 572 REG("QQPR"); 573 REG("QQQQPR"); 574 REG("VecListOneD"); 575 576 IMM("i32imm"); 577 IMM("i32imm_hilo16"); 578 IMM("bf_inv_mask_imm"); 579 IMM("lsb_pos_imm"); 580 IMM("width_imm"); 581 IMM("jtblock_operand"); 582 IMM("nohash_imm"); 583 IMM("p_imm"); 584 IMM("c_imm"); 585 IMM("coproc_option_imm"); 586 IMM("imod_op"); 587 IMM("iflags_op"); 588 IMM("cpinst_operand"); 589 IMM("setend_op"); 590 IMM("cps_opt"); 591 IMM("vfp_f64imm"); 592 IMM("vfp_f32imm"); 593 IMM("memb_opt"); 594 IMM("msr_mask"); 595 IMM("neg_zero"); 596 IMM("imm0_31"); 597 IMM("imm0_31_m1"); 598 IMM("imm1_16"); 599 IMM("imm1_32"); 600 IMM("nModImm"); 601 IMM("nImmSplatI8"); 602 IMM("nImmSplatI16"); 603 IMM("nImmSplatI32"); 604 IMM("nImmSplatI64"); 605 IMM("nImmVMOVI32"); 606 IMM("imm0_7"); 607 IMM("imm0_15"); 608 IMM("imm0_255"); 609 IMM("imm0_4095"); 610 IMM("imm0_65535"); 611 IMM("imm0_65535_expr"); 612 IMM("imm24b"); 613 IMM("pkh_lsl_amt"); 614 IMM("pkh_asr_amt"); 615 IMM("jt2block_operand"); 616 IMM("t_imm0_1020s4"); 617 IMM("t_imm0_508s4"); 618 IMM("pclabel"); 619 IMM("adrlabel"); 620 IMM("t_adrlabel"); 621 IMM("t2adrlabel"); 622 IMM("shift_imm"); 623 IMM("t2_shift_imm"); 624 IMM("neon_vcvt_imm32"); 625 IMM("shr_imm8"); 626 IMM("shr_imm16"); 627 IMM("shr_imm32"); 628 IMM("shr_imm64"); 629 IMM("t2ldrlabel"); 630 IMM("postidx_imm8"); 631 IMM("postidx_imm8s4"); 632 IMM("imm_sr"); 633 IMM("imm1_31"); 634 IMM("VectorIndex8"); 635 IMM("VectorIndex16"); 636 IMM("VectorIndex32"); 637 638 MISC("brtarget", "kOperandTypeARMBranchTarget"); // ? 639 MISC("uncondbrtarget", "kOperandTypeARMBranchTarget"); // ? 640 MISC("t_brtarget", "kOperandTypeARMBranchTarget"); // ? 641 MISC("t_bcctarget", "kOperandTypeARMBranchTarget"); // ? 642 MISC("t_cbtarget", "kOperandTypeARMBranchTarget"); // ? 643 MISC("bltarget", "kOperandTypeARMBranchTarget"); // ? 644 645 MISC("br_target", "kOperandTypeARMBranchTarget"); // ? 646 MISC("bl_target", "kOperandTypeARMBranchTarget"); // ? 647 MISC("blx_target", "kOperandTypeARMBranchTarget"); // ? 648 649 MISC("t_bltarget", "kOperandTypeARMBranchTarget"); // ? 650 MISC("t_blxtarget", "kOperandTypeARMBranchTarget"); // ? 651 MISC("so_reg_imm", "kOperandTypeARMSoRegReg"); // R, R, I 652 MISC("so_reg_reg", "kOperandTypeARMSoRegImm"); // R, R, I 653 MISC("shift_so_reg_reg", "kOperandTypeARMSoRegReg"); // R, R, I 654 MISC("shift_so_reg_imm", "kOperandTypeARMSoRegImm"); // R, R, I 655 MISC("t2_so_reg", "kOperandTypeThumb2SoReg"); // R, I 656 MISC("so_imm", "kOperandTypeARMSoImm"); // I 657 MISC("rot_imm", "kOperandTypeARMRotImm"); // I 658 MISC("t2_so_imm", "kOperandTypeThumb2SoImm"); // I 659 MISC("so_imm2part", "kOperandTypeARMSoImm2Part"); // I 660 MISC("pred", "kOperandTypeARMPredicate"); // I, R 661 MISC("it_pred", "kOperandTypeARMPredicate"); // I 662 MISC("addrmode_imm12", "kOperandTypeAddrModeImm12"); // R, I 663 MISC("ldst_so_reg", "kOperandTypeLdStSOReg"); // R, R, I 664 MISC("postidx_reg", "kOperandTypeARMAddrMode3Offset"); // R, I 665 MISC("addrmode2", "kOperandTypeARMAddrMode2"); // R, R, I 666 MISC("am2offset_reg", "kOperandTypeARMAddrMode2Offset"); // R, I 667 MISC("am2offset_imm", "kOperandTypeARMAddrMode2Offset"); // R, I 668 MISC("addrmode3", "kOperandTypeARMAddrMode3"); // R, R, I 669 MISC("am3offset", "kOperandTypeARMAddrMode3Offset"); // R, I 670 MISC("ldstm_mode", "kOperandTypeARMLdStmMode"); // I 671 MISC("addrmode5", "kOperandTypeARMAddrMode5"); // R, I 672 MISC("addrmode6", "kOperandTypeARMAddrMode6"); // R, R, I, I 673 MISC("am6offset", "kOperandTypeARMAddrMode6Offset"); // R, I, I 674 MISC("addrmode6dup", "kOperandTypeARMAddrMode6"); // R, R, I, I 675 MISC("addrmode6oneL32", "kOperandTypeARMAddrMode6"); // R, R, I, I 676 MISC("addrmodepc", "kOperandTypeARMAddrModePC"); // R, I 677 MISC("addr_offset_none", "kOperandTypeARMAddrMode7"); // R 678 MISC("reglist", "kOperandTypeARMRegisterList"); // I, R, ... 679 MISC("dpr_reglist", "kOperandTypeARMDPRRegisterList"); // I, R, ... 680 MISC("spr_reglist", "kOperandTypeARMSPRRegisterList"); // I, R, ... 681 MISC("it_mask", "kOperandTypeThumbITMask"); // I 682 MISC("t2addrmode_reg", "kOperandTypeThumb2AddrModeReg"); // R 683 MISC("t2addrmode_posimm8", "kOperandTypeThumb2AddrModeImm8"); // R, I 684 MISC("t2addrmode_negimm8", "kOperandTypeThumb2AddrModeImm8"); // R, I 685 MISC("t2addrmode_imm8", "kOperandTypeThumb2AddrModeImm8"); // R, I 686 MISC("t2am_imm8_offset", "kOperandTypeThumb2AddrModeImm8Offset");//I 687 MISC("t2addrmode_imm12", "kOperandTypeThumb2AddrModeImm12"); // R, I 688 MISC("t2addrmode_so_reg", "kOperandTypeThumb2AddrModeSoReg"); // R, R, I 689 MISC("t2addrmode_imm8s4", "kOperandTypeThumb2AddrModeImm8s4"); // R, I 690 MISC("t2addrmode_imm0_1020s4", "kOperandTypeThumb2AddrModeImm8s4"); // R, I 691 MISC("t2am_imm8s4_offset", "kOperandTypeThumb2AddrModeImm8s4Offset"); 692 // R, I 693 MISC("tb_addrmode", "kOperandTypeARMTBAddrMode"); // I 694 MISC("t_addrmode_rrs1", "kOperandTypeThumbAddrModeRegS1"); // R, R 695 MISC("t_addrmode_rrs2", "kOperandTypeThumbAddrModeRegS2"); // R, R 696 MISC("t_addrmode_rrs4", "kOperandTypeThumbAddrModeRegS4"); // R, R 697 MISC("t_addrmode_is1", "kOperandTypeThumbAddrModeImmS1"); // R, I 698 MISC("t_addrmode_is2", "kOperandTypeThumbAddrModeImmS2"); // R, I 699 MISC("t_addrmode_is4", "kOperandTypeThumbAddrModeImmS4"); // R, I 700 MISC("t_addrmode_rr", "kOperandTypeThumbAddrModeRR"); // R, R 701 MISC("t_addrmode_sp", "kOperandTypeThumbAddrModeSP"); // R, I 702 MISC("t_addrmode_pc", "kOperandTypeThumbAddrModePC"); // R, I 703 MISC("addrmode_tbb", "kOperandTypeThumbAddrModeRR"); // R, R 704 MISC("addrmode_tbh", "kOperandTypeThumbAddrModeRR"); // R, R 705 706 return 1; 707 } 708 709 #undef REG 710 #undef MEM 711 #undef MISC 712 713 #undef SET 714 715 /// ARMPopulateOperands - Handles all the operands in an ARM instruction, adding 716 /// the appropriate flags to their descriptors 717 /// 718 /// @operandFlags - A reference the array of operand flag objects 719 /// @inst - The instruction to use as a source of information 720 static void ARMPopulateOperands( 721 LiteralConstantEmitter *(&operandTypes)[EDIS_MAX_OPERANDS], 722 const CodeGenInstruction &inst) { 723 if (!inst.TheDef->isSubClassOf("InstARM") && 724 !inst.TheDef->isSubClassOf("InstThumb")) 725 return; 726 727 unsigned int index; 728 unsigned int numOperands = inst.Operands.size(); 729 730 if (numOperands > EDIS_MAX_OPERANDS) { 731 errs() << "numOperands == " << numOperands << " > " << 732 EDIS_MAX_OPERANDS << '\n'; 733 llvm_unreachable("Too many operands"); 734 } 735 736 for (index = 0; index < numOperands; ++index) { 737 const CGIOperandList::OperandInfo &operandInfo = inst.Operands[index]; 738 Record &rec = *operandInfo.Rec; 739 740 if (ARMFlagFromOpName(operandTypes[index], rec.getName())) { 741 errs() << "Operand type: " << rec.getName() << '\n'; 742 errs() << "Operand name: " << operandInfo.Name << '\n'; 743 errs() << "Instruction name: " << inst.TheDef->getName() << '\n'; 744 llvm_unreachable("Unhandled type"); 745 } 746 } 747 } 748 749 #define BRANCH(target) { \ 750 instType.set("kInstructionTypeBranch"); \ 751 DECORATE1(target, "kOperandFlagTarget"); \ 752 } 753 754 /// ARMExtractSemantics - Performs various checks on the name of an ARM 755 /// instruction to determine what sort of an instruction it is and then adds 756 /// the appropriate flags to the instruction and its operands 757 /// 758 /// @arg instType - A reference to the type for the instruction as a whole 759 /// @arg operandTypes - A reference to the array of operand type object pointers 760 /// @arg operandFlags - A reference to the array of operand flag object pointers 761 /// @arg inst - A reference to the original instruction 762 static void ARMExtractSemantics( 763 LiteralConstantEmitter &instType, 764 LiteralConstantEmitter *(&operandTypes)[EDIS_MAX_OPERANDS], 765 FlagsConstantEmitter *(&operandFlags)[EDIS_MAX_OPERANDS], 766 const CodeGenInstruction &inst) { 767 const std::string &name = inst.TheDef->getName(); 768 769 if (name == "tBcc" || 770 name == "tB" || 771 name == "t2Bcc" || 772 name == "Bcc" || 773 name == "tCBZ" || 774 name == "tCBNZ") { 775 BRANCH("target"); 776 } 777 778 if (name == "tBLr9" || 779 name == "BLr9_pred" || 780 name == "tBLXi_r9" || 781 name == "tBLXr_r9" || 782 name == "BLXr9" || 783 name == "t2BXJ" || 784 name == "BXJ") { 785 BRANCH("func"); 786 787 unsigned opIndex; 788 opIndex = inst.Operands.getOperandNamed("func"); 789 if (operandTypes[opIndex]->is("kOperandTypeImmediate")) 790 operandTypes[opIndex]->set("kOperandTypeARMBranchTarget"); 791 } 792 } 793 794 #undef BRANCH 795 796 /// populateInstInfo - Fills an array of InstInfos with information about each 797 /// instruction in a target 798 /// 799 /// @arg infoArray - The array of InstInfo objects to populate 800 /// @arg target - The CodeGenTarget to use as a source of instructions 801 static void populateInstInfo(CompoundConstantEmitter &infoArray, 802 CodeGenTarget &target) { 803 const std::vector<const CodeGenInstruction*> &numberedInstructions = 804 target.getInstructionsByEnumValue(); 805 806 unsigned int index; 807 unsigned int numInstructions = numberedInstructions.size(); 808 809 for (index = 0; index < numInstructions; ++index) { 810 const CodeGenInstruction& inst = *numberedInstructions[index]; 811 812 CompoundConstantEmitter *infoStruct = new CompoundConstantEmitter; 813 infoArray.addEntry(infoStruct); 814 815 LiteralConstantEmitter *instType = new LiteralConstantEmitter; 816 infoStruct->addEntry(instType); 817 818 LiteralConstantEmitter *numOperandsEmitter = 819 new LiteralConstantEmitter(inst.Operands.size()); 820 infoStruct->addEntry(numOperandsEmitter); 821 822 CompoundConstantEmitter *operandTypeArray = new CompoundConstantEmitter; 823 infoStruct->addEntry(operandTypeArray); 824 825 LiteralConstantEmitter *operandTypes[EDIS_MAX_OPERANDS]; 826 827 CompoundConstantEmitter *operandFlagArray = new CompoundConstantEmitter; 828 infoStruct->addEntry(operandFlagArray); 829 830 FlagsConstantEmitter *operandFlags[EDIS_MAX_OPERANDS]; 831 832 for (unsigned operandIndex = 0; 833 operandIndex < EDIS_MAX_OPERANDS; 834 ++operandIndex) { 835 operandTypes[operandIndex] = new LiteralConstantEmitter; 836 operandTypeArray->addEntry(operandTypes[operandIndex]); 837 838 operandFlags[operandIndex] = new FlagsConstantEmitter; 839 operandFlagArray->addEntry(operandFlags[operandIndex]); 840 } 841 842 unsigned numSyntaxes = 0; 843 844 // We don't need to do anything for pseudo-instructions, as we'll never 845 // see them here. We'll only see real instructions. 846 // We still need to emit null initializers for everything. 847 if (!inst.isPseudo) { 848 if (target.getName() == "X86") { 849 X86PopulateOperands(operandTypes, inst); 850 X86ExtractSemantics(*instType, operandFlags, inst); 851 numSyntaxes = 2; 852 } 853 else if (target.getName() == "ARM") { 854 ARMPopulateOperands(operandTypes, inst); 855 ARMExtractSemantics(*instType, operandTypes, operandFlags, inst); 856 numSyntaxes = 1; 857 } 858 } 859 860 CompoundConstantEmitter *operandOrderArray = new CompoundConstantEmitter; 861 862 infoStruct->addEntry(operandOrderArray); 863 864 for (unsigned syntaxIndex = 0; 865 syntaxIndex < EDIS_MAX_SYNTAXES; 866 ++syntaxIndex) { 867 CompoundConstantEmitter *operandOrder = 868 new CompoundConstantEmitter(EDIS_MAX_OPERANDS); 869 870 operandOrderArray->addEntry(operandOrder); 871 872 if (syntaxIndex < numSyntaxes) { 873 populateOperandOrder(operandOrder, inst, syntaxIndex); 874 } 875 } 876 877 infoStruct = NULL; 878 } 879 } 880 881 static void emitCommonEnums(raw_ostream &o, unsigned int &i) { 882 EnumEmitter operandTypes("OperandTypes"); 883 operandTypes.addEntry("kOperandTypeNone"); 884 operandTypes.addEntry("kOperandTypeImmediate"); 885 operandTypes.addEntry("kOperandTypeRegister"); 886 operandTypes.addEntry("kOperandTypeX86Memory"); 887 operandTypes.addEntry("kOperandTypeX86EffectiveAddress"); 888 operandTypes.addEntry("kOperandTypeX86PCRelative"); 889 operandTypes.addEntry("kOperandTypeARMBranchTarget"); 890 operandTypes.addEntry("kOperandTypeARMSoRegReg"); 891 operandTypes.addEntry("kOperandTypeARMSoRegImm"); 892 operandTypes.addEntry("kOperandTypeARMSoImm"); 893 operandTypes.addEntry("kOperandTypeARMRotImm"); 894 operandTypes.addEntry("kOperandTypeARMSoImm2Part"); 895 operandTypes.addEntry("kOperandTypeARMPredicate"); 896 operandTypes.addEntry("kOperandTypeAddrModeImm12"); 897 operandTypes.addEntry("kOperandTypeLdStSOReg"); 898 operandTypes.addEntry("kOperandTypeARMAddrMode2"); 899 operandTypes.addEntry("kOperandTypeARMAddrMode2Offset"); 900 operandTypes.addEntry("kOperandTypeARMAddrMode3"); 901 operandTypes.addEntry("kOperandTypeARMAddrMode3Offset"); 902 operandTypes.addEntry("kOperandTypeARMLdStmMode"); 903 operandTypes.addEntry("kOperandTypeARMAddrMode5"); 904 operandTypes.addEntry("kOperandTypeARMAddrMode6"); 905 operandTypes.addEntry("kOperandTypeARMAddrMode6Offset"); 906 operandTypes.addEntry("kOperandTypeARMAddrMode7"); 907 operandTypes.addEntry("kOperandTypeARMAddrModePC"); 908 operandTypes.addEntry("kOperandTypeARMRegisterList"); 909 operandTypes.addEntry("kOperandTypeARMDPRRegisterList"); 910 operandTypes.addEntry("kOperandTypeARMSPRRegisterList"); 911 operandTypes.addEntry("kOperandTypeARMTBAddrMode"); 912 operandTypes.addEntry("kOperandTypeThumbITMask"); 913 operandTypes.addEntry("kOperandTypeThumbAddrModeImmS1"); 914 operandTypes.addEntry("kOperandTypeThumbAddrModeImmS2"); 915 operandTypes.addEntry("kOperandTypeThumbAddrModeImmS4"); 916 operandTypes.addEntry("kOperandTypeThumbAddrModeRegS1"); 917 operandTypes.addEntry("kOperandTypeThumbAddrModeRegS2"); 918 operandTypes.addEntry("kOperandTypeThumbAddrModeRegS4"); 919 operandTypes.addEntry("kOperandTypeThumbAddrModeRR"); 920 operandTypes.addEntry("kOperandTypeThumbAddrModeSP"); 921 operandTypes.addEntry("kOperandTypeThumbAddrModePC"); 922 operandTypes.addEntry("kOperandTypeThumb2AddrModeReg"); 923 operandTypes.addEntry("kOperandTypeThumb2SoReg"); 924 operandTypes.addEntry("kOperandTypeThumb2SoImm"); 925 operandTypes.addEntry("kOperandTypeThumb2AddrModeImm8"); 926 operandTypes.addEntry("kOperandTypeThumb2AddrModeImm8Offset"); 927 operandTypes.addEntry("kOperandTypeThumb2AddrModeImm12"); 928 operandTypes.addEntry("kOperandTypeThumb2AddrModeSoReg"); 929 operandTypes.addEntry("kOperandTypeThumb2AddrModeImm8s4"); 930 operandTypes.addEntry("kOperandTypeThumb2AddrModeImm8s4Offset"); 931 operandTypes.emit(o, i); 932 933 o << "\n"; 934 935 EnumEmitter operandFlags("OperandFlags"); 936 operandFlags.addEntry("kOperandFlagSource"); 937 operandFlags.addEntry("kOperandFlagTarget"); 938 operandFlags.emitAsFlags(o, i); 939 940 o << "\n"; 941 942 EnumEmitter instructionTypes("InstructionTypes"); 943 instructionTypes.addEntry("kInstructionTypeNone"); 944 instructionTypes.addEntry("kInstructionTypeMove"); 945 instructionTypes.addEntry("kInstructionTypeBranch"); 946 instructionTypes.addEntry("kInstructionTypePush"); 947 instructionTypes.addEntry("kInstructionTypePop"); 948 instructionTypes.addEntry("kInstructionTypeCall"); 949 instructionTypes.addEntry("kInstructionTypeReturn"); 950 instructionTypes.emit(o, i); 951 952 o << "\n"; 953 } 954 955 void EDEmitter::run(raw_ostream &o) { 956 unsigned int i = 0; 957 958 CompoundConstantEmitter infoArray; 959 CodeGenTarget target(Records); 960 961 populateInstInfo(infoArray, target); 962 963 emitCommonEnums(o, i); 964 965 o << "namespace {\n"; 966 967 o << "llvm::EDInstInfo instInfo" << target.getName().c_str() << "[] = "; 968 infoArray.emit(o, i); 969 o << ";" << "\n"; 970 971 o << "}\n"; 972 } 973
