| /external/llvm/lib/Target/XCore/ |
| XCoreISelLowering.cpp | 43 getTargetNodeName(unsigned Opcode) const
45 switch (Opcode)
730 unsigned Opcode = (N->getOpcode() == ISD::ADD) ? XCoreISD::LADD :
733 SDValue Carry = DAG.getNode(Opcode, dl, DAG.getVTList(MVT::i32, MVT::i32),
737 SDValue Ignored = DAG.getNode(Opcode, dl, DAG.getVTList(MVT::i32, MVT::i32),
[all...] |
| /external/llvm/lib/Transforms/InstCombine/ |
| InstCombineAndOrXor.cpp | 138 /// opcode and two operands into either a constant true or false, or a brand
161 /// opcode and two operands into either a FCmp instruction. isordered is passed
[all...] |
| InstructionCombining.cpp | 124 Instruction::BinaryOps Opcode = I.getOpcode();
125 if (Opcode != Instruction::Add &&
126 Opcode != Instruction::Sub) {
141 if (Opcode == Instruction::Add) {
172 Instruction::BinaryOps Opcode = I.getOpcode();
188 if (Op0 && Op0->getOpcode() == Opcode) {
194 if (Value *V = SimplifyBinOp(Opcode, B, C, TD)) {
217 if (Op1 && Op1->getOpcode() == Opcode) {
223 if (Value *V = SimplifyBinOp(Opcode, A, B, TD)) {
239 if (Op0 && Op0->getOpcode() == Opcode) {
[all...] |
| /external/llvm/lib/Transforms/Scalar/ |
| IndVarSimplify.cpp | [all...] |
| /external/llvm/bindings/ocaml/llvm/ |
| llvm.ml | 136 module Opcode = struct
228 | Instruction of Opcode.t
381 external constexpr_opcode : llvalue -> Opcode.t = "llvm_constexpr_get_opcode"
[all...] |
| llvm.mli | 186 module Opcode : sig
280 | Instruction of Opcode.t
667 val constexpr_opcode : llvalue -> Opcode.t
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeIntegerTypes.cpp | 457 unsigned Opcode = N->getOpcode() == ISD::SADDO ? ISD::ADD : ISD::SUB;
458 SDValue Res = DAG.getNode(Opcode, dl, NVT, LHS, RHS);
620 unsigned Opcode = N->getOpcode() == ISD::UADDO ? ISD::ADD : ISD::SUB;
621 SDValue Res = DAG.getNode(Opcode, dl, NVT, LHS, RHS);
[all...] |
| LegalizeVectorTypes.cpp | [all...] |
| ScheduleDAGRRList.cpp | 282 /// opcode to determine what register class is being generated.
294 unsigned Opcode = Node->getMachineOpcode();
296 if (Opcode == TargetOpcode::REG_SEQUENCE) {
305 const MCInstrDesc Desc = TII->get(Opcode);
[all...] |
| SelectionDAGBuilder.cpp | [all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsISelLowering.cpp | 50 const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const {
51 switch (Opcode) {
700 // Get fp branch code (not opcode) from condition code.
725 // true/false values to select between, and a branch opcode to use.
[all...] |
| /external/v8/src/arm/ |
| constants-arm.h | 191 enum Opcode {
635 return static_cast<Opcode>(Bits(24, 21));
637 inline Opcode OpcodeField() const {
638 return static_cast<Opcode>(BitField(24, 21));
|
| /external/v8/src/mips/ |
| constants-mips.h | 198 enum Opcode {
557 inline Opcode OpcodeValue() const {
558 return static_cast<Opcode>(
618 inline Opcode OpcodeFieldRaw() const {
619 return static_cast<Opcode>(InstructionBits() & kOpcodeMask);
653 // Get the secondary field according to the opcode.
655 Opcode op = OpcodeFieldRaw();
|
| /external/clang/lib/CodeGen/ |
| CGExprScalar.cpp | 47 BinaryOperator::Opcode Opcode; // Opcode of BinOp to perform
[all...] |
| /dalvik/libdex/ |
| DexOpcodes.h | 18 * Dalvik opcode information.
21 * automatically by the opcode-gen tool. Any edits to the generated
24 * See the file opcode-gen/README.txt for information about updating
34 * kMaxOpcodeValue: the highest possible raw (unpacked) opcode value
36 * kNumPackedOpcodes: the highest possible packed opcode value of a
37 * valid Dalvik opcode, plus one
42 // BEGIN(libdex-maximum-values); GENERATED AUTOMATICALLY BY opcode-gen
45 // END(libdex-maximum-values); GENERATED AUTOMATICALLY BY opcode-gen
58 * associated with each is the corresponding packed opcode number.
59 * This is different than the opcode value from the Dalvik bytecod
[all...] |
| /external/clang/include/clang/AST/ |
| Expr.h | [all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/X86/ |
| X86ISelLowering.cpp | 13188 unsigned opcode; local
[all...] |
