| /external/llvm/lib/Target/PowerPC/ |
| PPCSubtarget.h | 127 /// hasLazyResolverStub - Return true if accesses to the specified global have
|
| /external/llvm/test/Transforms/LICM/ |
| scalar_promote.ll | 97 ; Should have promoted 'handle2' accesses.
|
| /external/oprofile/events/arm/armv7/ |
| events | 21 event:0x50 counters:1,2,3,4 um:zero minimum:500 name:L1_INST : Any L1 instruction cache access, excluding CP15 cache accesses
|
| /external/oprofile/events/i386/nehalem/ |
| events | 55 event:0x4F counters:0,1,2,3 um:ept minimum:6000 name:EPT : Counts Extended Page Directory Entry accesses. The Extended Page Directory cache is used by Virtual Machine operating systems while the guest operating systems use the standard TLB caches.
62 event:0x80 counters:0,1,2,3 um:l1i minimum:6000 name:L1I : Counts L1i instruction cache accesses.
64 event:0x82 counters:0,1,2,3 um:large_itlb minimum:6000 name:LARGE_ITLB : Counts number of large ITLB accesses
81 event:0xBA counters:0,1,2,3 um:pic_accesses minimum:6000 name:PIC_ACCESSES : Counts number of TPR accesses
|
| /external/oprofile/events/ppc/7450/ |
| events | 25 event:0x29 counters:0 um:zero minimum:3000 name:L1_ICACHE_ACCESSES : L1 Instruction Cache Accesses
|
| /external/oprofile/events/ppc64/pa6t/ |
| events | 27 event:0x25 counters:5 um:zero minimum:2000 name:GRP2_ICACHE_ACC : Icache accesses
|
| /external/qemu/android/utils/ |
| mapfile.h | 95 * accesses are permitted to the data being mapped. This parameter has the
|
| /external/qemu/ |
| bswap.h | 135 /* unaligned versions (optimized for frequent unaligned accesses)*/
|
| ioport.c | 95 /* default is to make two byte accesses */
|
| /external/srec/tools/thirdparty/OpenFst/fst/lib/ |
| randgen.h | 60 // Assumes Weight::Value() accesses the floating point
|
| /external/v8/src/ |
| bignum.h | 128 // A vector backed by bigits_buffer_. This way accesses to the array are
|
| /external/valgrind/main/include/ |
| pub_tool_replacemalloc.h | 44 /* If a tool uses deferred freeing (e.g. memcheck to catch accesses to
|
| /external/valgrind/unittest/ |
| bigtest.cc | 250 // Write accesses
288 // Read accesses
571 // Thread accesses heap
587 // Thread accesses stack
|
| /external/webkit/Source/WebCore/bindings/generic/ |
| BindingSecurity.h | 90 // The subject is detached from a frame, deny accesses.
|
| /external/webkit/Source/WebCore/platform/sql/ |
| SQLiteDatabase.h | 127 // Set this flag to allow access from multiple threads. Not all multi-threaded accesses are safe!
|
| /external/webkit/Source/WebCore/webaudio/ |
| AudioNodeInput.h | 75 // Rendering code accesses its version of the current connections here.
|
| /frameworks/base/docs/html/guide/practices/design/ |
| performance.jd | 148 <p>On devices without a JIT, caching field accesses is about 20% faster than
206 the integer value 42 directly, and accesses to <code>strVal</code> will
298 (<code>Foo$Inner</code>) that directly accesses a private method and a private
321 accesses, so this is an example of a certain language idiom resulting in an
|
| /libcore/luni/src/main/java/java/nio/ |
| MappedByteBuffer.java | 66 * loaded in RAM, meaning that accesses will not cause a page fault. It is impossible to give
|
| /ndk/sources/host-tools/ndk-stack/elff/ |
| mapfile.h | 95 * accesses are permitted to the data being mapped. This parameter has the
|
| /ndk/sources/host-tools/sed-4.2.1/lib/ |
| memchr.c | 158 memory accesses, just by looking at the tmp result from the last loop
|
| /external/oprofile/events/ia64/itanium2/ |
| events | 85 event:0xc0 counters:1 um:zero minimum:5000 name:L1DTLB_TRANSFER : L1DTLB misses that hit in the L2DTLB for accesses counted in L1D_READS
116 #event:0xb6 counters:0,1,2,3 um:zero minimum:5000 name:L2_GOT_RECIRC_OZQ_ACC : Counts number of OZQ accesses recirculated back to L1D
123 #event:0xb0 counters:0,1,2,3 um:l2_l3_access_cancel minimum:5000 name:L2_L3ACCESS_CANCEL : Canceled L3 accesses
166 event:0xb0 counters:0 um:l2_l3_access_cancel minimum:5000 name:L2_L3ACCESS_CANCEL : Canceled L3 accesses
176 #event:0xb6 counters:0,1,2,3 um:zero minimum:5000 name:L2_GOT_RECIRC_OZQ_ACC : Counts number of OZQ accesses recirculated back to L1D
222 #event:0xc0 counters:1 um:zero minimum:5000 name:L1DTLB_TRANSFER : L1DTLB misses that hit in the L2DTLB for accesses counted in L1D_READS
264 event:0x20 counters:0,1,2,3 um:rse_references_retired minimum:500 name:RSE_REFERENCES_RETIRED : RSE Accesses
|
| /external/valgrind/main/helgrind/ |
| helgrind.h | 439 accesses done by T1 before the ..BEFORE.. call as happening-before
440 all memory accesses done by T2 after the ..AFTER.. call. Hence
441 Helgrind won't complain about races if T2's accesses afterwards are
442 to the same locations as T1's accesses before.
471 subsequent accesses to this memory.
605 /* Start ignoring all memory accesses (reads and writes). */
612 /* Stop ignoring all memory accesses. */
|
| /prebuilt/linux-x86/toolchain/i686-linux-glibc2.7-4.4.3/sysroot/usr/include/alsa/ |
| iatomic.h | 229 * memory accesses are ordered.
359 * accesses are visible before all subsequent
360 * accesses and vice versa. This is also known as
364 * accesses to memory mapped I/O registers. For that, mf.a needs to
663 * The sync instruction guarantees that all memory accesses initiated
|
| /external/clang/lib/Sema/ |
| SemaExprMember.cpp | 441 assert(BaseExpr && "cannot happen with implicit member accesses");
620 // Implicit member accesses.
629 // Explicit member accesses.
681 // accesses an anonymous struct/union that's a static member of
[all...] |
| /external/valgrind/main/callgrind/docs/ |
| cl-manual.xml | [all...] |
