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  /external/webkit/LayoutTests/dom/xhtml/level2/html/
HTMLScriptElement06.js 78 htmlFor is described as for future use. Test accesses the value, but makes no assertions about its value.
HTMLScriptElement07.js 78 event is described as for future use. Test accesses the value, but makes no assertions about its value.
  /external/webkit/Source/JavaScriptCore/wtf/
HashTable.cpp 48 printf("%d accesses\n", numAccesses);
  /frameworks/base/native/graphics/jni/
bitmap.cpp 92 // bitmaps. Note that this will slow down read-only accesses to the
  /prebuilt/linux-x86/toolchain/i686-linux-glibc2.7-4.4.3/i686-linux/include/c++/4.4.3/ext/
atomicity.h 104 // that the compiler doesn't reorder memory accesses across the
  /prebuilt/ndk/android-ndk-r5/sources/cxx-stl/gnu-libstdc++/include/ext/
atomicity.h 104 // that the compiler doesn't reorder memory accesses across the
  /prebuilt/ndk/android-ndk-r6/sources/cxx-stl/gnu-libstdc++/include/ext/
atomicity.h 104 // that the compiler doesn't reorder memory accesses across the
  /external/valgrind/main/docs/html/
hg-manual.html 316 usually able to show both accesses involved in a race. At least
349 constraints upon the order in which memory accesses can
422 accesses to memory locations. If a location -- in this example,
425 two accesses are ordered by the happens-before relation. If so,
443 <p>What does it mean to say that two accesses from different
446 cause those accesses to happen in a particular order, irrespective of
454 immediately) locked by thread T2, then the memory accesses in T1
462 on the same CV, then the memory accesses in T1 prior to the
482 That is, all memory accesses performed by the parent prior to
483 creating the child are regarded as happening-before all the accesses
    [all...]
  /external/valgrind/main/helgrind/docs/
hg-manual.xml 345 usually able to show both accesses involved in a race. At least
384 constraints upon the order in which memory accesses can
468 accesses to memory locations. If a location -- in this example,
471 two accesses are ordered by the happens-before relation. If so,
492 <para>What does it mean to say that two accesses from different
495 cause those accesses to happen in a particular order, irrespective of
505 immediately) locked by thread T2, then the memory accesses in T1
515 on the same CV, then the memory accesses in T1 prior to the
539 That is, all memory accesses performed by the parent prior to
540 creating the child are regarded as happening-before all the accesses
    [all...]
  /external/elfutils/
TODO 38 All accesses to the debug sections should make sure the offsets are
39 valid. This is currently especially a problem with leb128 accesses.
  /external/llvm/include/llvm/Analysis/
LoopDependenceAnalysis.h 11 // accesses in loops.
100 /// memory and at least one of those accesses is a write.
  /external/llvm/test/Analysis/LoopDependenceAnalysis/
siv-weak-crossing.ll 90 ;; // accesses in all iterations are within bounds. while this example's first
91 ;; // (ZIV-)subscript is (0, 1), accesses are dependent.
  /external/oprofile/events/mips/1004K/
events 24 event:0x5 counters:0 um:zero minimum:500 name:ITLB_ACCESSES : 5-0 Instruction micro-TLB accesses
25 event:0x6 counters:0 um:zero minimum:500 name:DTLB_ACCESSES : 6-0 Data micro-TLB accesses
26 event:0x7 counters:0 um:zero minimum:500 name:JTLB_INSN_ACCESSES : 7-0 Joint TLB instruction accesses
27 event:0x8 counters:0 um:zero minimum:500 name:JTLB_DATA_ACCESSES : 8-0 Joint TLB data (non-instruction) accesses
28 event:0x9 counters:0 um:zero minimum:500 name:ICACHE_ACCESSES : 9-0 Instruction cache accesses
29 event:0xa counters:0 um:zero minimum:500 name:DCACHE_ACCESSES : 10-0 Data cache accesses
40 event:0x16 counters:0 um:zero minimum:500 name:L2_CACHE_MISSES : 22-0 L2 cache accesses that missed in the cache
119 event:0x415 counters:1 um:zero minimum:500 name:L2_CACHE_ACCESSES : 21-1 Accesses to the L2 cache
  /external/oprofile/events/mips/34K/
events 24 event:0x5 counters:0 um:zero minimum:500 name:ITLB_ACCESSES : 5-0 Instruction micro-TLB accesses
25 event:0x6 counters:0 um:zero minimum:500 name:DTLB_ACCESSES : 6-0 Data micro-TLB accesses
26 event:0x7 counters:0 um:zero minimum:500 name:JTLB_INSN_ACCESSES : 7-0 Joint TLB instruction accesses
27 event:0x8 counters:0 um:zero minimum:500 name:JTLB_DATA_ACCESSES : 8-0 Joint TLB data (non-instruction) accesses
28 event:0x9 counters:0 um:zero minimum:500 name:ICACHE_ACCESSES : 9-0 Instruction cache accesses
29 event:0xa counters:0 um:zero minimum:500 name:DCACHE_ACCESSES : 10-0 Data cache accesses
40 event:0x16 counters:0 um:zero minimum:500 name:L2_CACHE_MISSES : 22-0 L2 cache accesses that missed in the cache
111 event:0x415 counters:1 um:zero minimum:500 name:L2_CACHE_ACCESSES : 21-1 Accesses to the L2 cache
  /external/qemu/
cpu-defs.h 87 bit TARGET_PAGE_BITS-1..4 : Nonzero for accesses that should not
95 /* Addend to virtual address to get host address. IO accesses
  /external/valgrind/main/
glibc-2.X-drd.supp 34 # that triggers conflicting memory accesses. See also
138 # Unfortunately many statements in libgomp trigger conflicting accesses. It is
  /frameworks/base/tools/layoutlib/create/tests/com/android/tools/layoutlib/create/
DelegateClassAdapterTest.java 343 * Accesses {@link OuterClass#get} or {@link InnerClass#get}via reflection.
354 * Accesses the "_Original" methods for {@link OuterClass#get}
366 * Accesses the any declared method that takes no parameter via reflection.
387 * Accesses {@link ClassWithNative#add(int, int)} via reflection.
398 * Accesses {@link ClassWithNative#callNativeInstance(int, double, Object[])}
  /external/valgrind/main/drd/docs/
drd-manual.xml 57 accesses via locking. E.g. the POSIX threads library, the Qt library
157 Which source code statements generate which memory accesses depends on
269 conflicting memory accesses are ordered by synchronization
287 many conflicting memory accesses in such applications and although such
295 algorithm is to verify whether all shared memory accesses follow a consistent
297 whether all interthread memory accesses are ordered by synchronization
373 memory accesses that occur after memory has been freed but might cause
597 There are always at least two memory accesses involved in a data
598 race. Memory accesses involved in a data race are called
599 <emphasis>conflicting memory accesses</emphasis>. DRD prints
    [all...]
  /dalvik/docs/
verifier.html 181 optimizer, which will convert many field/method/class accesses into a
182 simpler form after performing the access check. However, not all accesses
183 can be optimized (e.g. accesses to classes unknown at dexopt time),
  /dalvik/vm/native/
java_lang_System.cpp 24 * The VM makes guarantees about the atomicity of accesses to primitive
26 * In particular, 8-bit, 16-bit, and 32-bit accesses must be atomic and
27 * must not cause "word tearing". Accesses to 64-bit array elements must
  /frameworks/base/core/java/android/util/
LruCache.java 352 int accesses = hitCount + missCount; local
353 int hitPercent = accesses != 0 ? (100 * hitCount / accesses) : 0;
  /frameworks/support/v4/java/android/support/v4/util/
LruCache.java 318 int accesses = hitCount + missCount; local
319 int hitPercent = accesses != 0 ? (100 * hitCount / accesses) : 0;
  /dalvik/vm/mterp/cstubs/
stubdefs.cpp 22 * Redefine what used to be local variable accesses into Thread struct
  /external/chromium/chrome/browser/chromeos/
external_metrics.h 23 // flock() to synchronize accesses to the file.
  /external/chromium/chrome/browser/content_settings/
content_settings_policy_provider.h 73 // Used around accesses to the managed_default_content_settings_ object to

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