| /external/llvm/test/Transforms/IndVarSimplify/ |
| lftr-other-uses.ll | 10 %struct.macroblock = type { i32, i32, i32, %struct.macroblock*, %struct.macroblock*, i32, [2 x [4 x [4 x [2 x i32]]]], i32, i64, i64, i32, i32, [4 x i32], [4 x i32], i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }
|
| /external/llvm/test/Transforms/ObjCARC/ |
| contract.ll | 65 define void @test3(i8* %x, i64 %n) {
83 define void @test4(i8* %x, i64 %n) {
|
| /external/llvm/test/Transforms/ScalarRepl/ |
| 2009-12-11-NeonTypes.ll | 4 target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:32-n32"
69 %struct._NSRange = type { i64 }
|
| memset-aggregate.ll | 6 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64"
8 %struct.bar = type { %struct.foo, i64, double }
|
| /external/llvm/docs/CommandGuide/ |
| FileCheck.pod | 80 define void @inc4(i64* %p) {
84 %0 = tail call i64 @llvm.atomic.load.add.i64.p0i64(i64* %p, i64 1)
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | 96 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal);
101 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal);
110 setOperationAction(ISD::SREM, MVT::i64, Expand);
111 setOperationAction(ISD::UREM, MVT::i64, Expand);
116 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
117 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
120 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
121 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
150 setOperationAction(ISD::BSWAP, MVT::i64 , Expand);
151 setOperationAction(ISD::CTPOP, MVT::i64 , Expand)
[all...] |
| /cts/tests/tests/renderscript/src/android/renderscript/cts/ |
| ElementTest.java | 90 assertTrue(Element.I64(mRS) != null);
195 Element[] I64 = { Element.I64(mRS) };
239 F32_3, F32_4, F64, I16, I32, I64, I8,
294 eb.add(Element.I64(mRS), "I64", arraySize);
360 assertFalse(Element.I64(mRS).isComplex());
|
| /external/llvm/lib/Target/CellSPU/ |
| SPUNodes.td | 65 // "marker" type for i64 operators that need a shuffle mask
135 // i64 markers: supplies extra operands used to generate the i64 operator
|
| SPUSubtarget.h | 86 return "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128"
|
| /external/llvm/lib/VMCore/ |
| ValueTypes.cpp | 109 case MVT::i64: return "i64";
159 case MVT::i64: return Type::getInt64Ty(Context);
|
| /external/llvm/test/CodeGen/ARM/ |
| 2009-06-04-MissingLiveIn.ll | 5 %struct.cab_file = type { i32, i16, i64, i8*, i32, i32, i32, %struct.cab_folder*, %struct.cab_file*, %struct.cab_archive*, %struct.cab_state* }
6 %struct.cab_folder = type { i16, i16, %struct.cab_archive*, i64, %struct.cab_folder* }
13 define fastcc i32 @qtm_decompress(%struct.qtm_stream* %qtm, i64 %out_bytes) nounwind {
|
| vext.ll | 139 define arm_aapcscc void @test_elem_mismatch(<2 x i64>* nocapture %src, <4 x i16>* nocapture %dest) nounwind {
142 %tmp0 = load <2 x i64>* %src, align 16
143 %tmp1 = bitcast <2 x i64> %tmp0 to <4 x i32>
|
| 2007-05-07-tailmerge-1.ll | 7 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64"
|
| 2007-05-09-tailmerge-2.ll | 7 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64"
|
| 2007-05-22-tailmerge-3.ll | 9 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64"
|
| 2009-06-15-RegScavengerAssert.ll | 136 br i1 undef, label %bb1.i64.i.preheader, label %bb5.i179
141 bb1.i64.i.preheader: ; preds = %bb1.i81.i.preheader
144 bb.i9.i: ; preds = %bb1.i64.i.preheader
147 dfg_DeleteProofList.exit.i: ; preds = %bb1.i64.i.preheader
|
| /external/llvm/test/CodeGen/Thumb2/ |
| 2009-08-07-NeonFPBug.ll | 3 %struct.FILE = type { i8*, i32, i32, i16, i16, %struct.__sbuf, i32, i8*, i32 (i8*)*, i32 (i8*, i8*, i32)*, i64 (i8*, i64, i32)*, i32 (i8*, i8*, i32)*, %struct.__sbuf, %struct.__sFILEX*, i32, [3 x i8], [1 x i8], %struct.__sbuf, i32, i64 }
|
| /external/llvm/test/Transforms/LICM/ |
| sinking.ll | 120 %dead = getelementptr %Ty* @X2, i64 0, i32 0
127 ; CHECK-NEXT: %dead = getelementptr %Ty* @X2, i64 0, i32 0
240 %dead = getelementptr %Ty* @X2, i64 0, i32 0
|
| /external/qemu/target-i386/ |
| ops_sse_header.h | 120 DEF_HELPER_2(glue(movq_mm_T0, SUFFIX), void, Reg, i64)
164 DEF_HELPER_2(cvtsq2ss, void, XMMReg, i64)
165 DEF_HELPER_2(cvtsq2sd, void, XMMReg, i64)
|
| /external/llvm/lib/Target/X86/ |
| X86InstrInfo.td | 285 def i8mem_NOREX : Operand<i64> {
309 def i64mem_TC : Operand<i64> {
323 def offset8 : Operand<i64>;
324 def offset16 : Operand<i64>;
325 def offset32 : Operand<i64>;
326 def offset64 : Operand<i64>;
408 def i64i32imm : Operand<i64> {
415 def i64i32imm_pcrel : Operand<i64> {
422 def i64i8imm : Operand<i64> {
447 def lea64addr : ComplexPattern<i64, 5, "SelectLEAAddr"
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeDAG.cpp | 351 (VT == MVT::f64) ? MVT::i64 : MVT::i32);
733 if (TLI.isTypeLegal(MVT::i64)) {
735 zextOrTrunc(64), MVT::i64);
[all...] |
| /external/clang/test/CodeGen/ |
| exprs.c | 129 // CHECK: [[Xaddr:%[^ ]+]] = alloca i64, align 8
|
| sse-builtins.c | 102 // CHECK: load i64* {{.*}}, align 1{{$}}
|
| /external/clang/test/CodeGenCXX/ |
| conditional-gnu-ext.cpp | 8 // CHECK: call i32 (...)* @printf({{.*}}, i8* inttoptr (i64 3735928559 to i8*))
|
| for-range.cpp | 45 // CHECK: getelementptr {{.*}}, i64 5
|
