| /external/llvm/lib/CodeGen/SelectionDAG/ |
| SelectionDAG.cpp | 213 ISD::CondCode ISD::getSetCCSwappedOperands(ISD::CondCode Operation) {
218 return ISD::CondCode((Operation & ~6) | // Keep the N, U, E bits
225 ISD::CondCode ISD::getSetCCInverse(ISD::CondCode Op, bool isInteger) {
235 return ISD::CondCode(Operation);
242 static int isSignedOp(ISD::CondCode Opcode) {
262 ISD::CondCode ISD::getSetCCOrOperation(ISD::CondCode Op1, ISD::CondCode Op2
[all...] |
| TargetLowering.cpp | 523 static void InitCmpLibcallCCs(ISD::CondCode *CCs) {
524 memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL);
[all...] |
| DAGCombiner.cpp | 232 SDValue N3, ISD::CondCode CC,
234 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond,
[all...] |
| LegalizeIntegerTypes.cpp | [all...] |
| LegalizeDAG.cpp | [all...] |
| SelectionDAGBuilder.cpp | [all...] |
| SelectionDAGISel.cpp | [all...] |
| /external/llvm/include/llvm/CodeGen/ |
| SelectionDAGNodes.h | [all...] |
| /external/llvm/lib/Target/X86/ |
| X86ISelLowering.cpp | [all...] |
| X86ISelLowering.h | [all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/CellSPU/ |
| SPUISelLowering.cpp | [all...] |
