| /external/llvm/lib/Target/ARM/ |
| ARMISelDAGToDAG.cpp | 209 /// 1, 2, 3 or 4. The opcode arrays specify the instructions used for
217 /// be 1, 2, 3 or 4. The opcode arrays specify the instructions used for
225 /// be 2, 3 or 4. The opcode arrays specify the instructions used for
232 /// should be 2, 3 or 4. The opcode array specifies the instructions used
305 // opcode and that it has a immediate integer right operand.
357 unsigned Opcode = MCID.getOpcode();
358 if (Opcode == ARM::VMOVRS || Opcode == ARM::VMOVRRD)
373 return TII->isFpMLxInstruction(Opcode);
726 unsigned Opcode = Op->getOpcode()
[all...] |
| MLxExpansionPass.cpp | 144 unsigned Opcode = MCID.getOpcode();
145 if (Opcode == ARM::VMOVRS || Opcode == ARM::VMOVRRD)
|
| ARMBaseInstrInfo.cpp | 55 unsigned MLxOpc; // MLA / MLS opcode
56 unsigned MulOpc; // Expanded multiplication opcode
57 unsigned AddSubOpc; // Expanded add / sub opcode
[all...] |
| /external/clang/lib/StaticAnalyzer/Core/ |
| SValBuilder.cpp | 41 NonLoc SValBuilder::makeNonLoc(const SymExpr *lhs, BinaryOperator::Opcode op,
50 NonLoc SValBuilder::makeNonLoc(const SymExpr *lhs, BinaryOperator::Opcode op,
165 SVal SValBuilder::evalBinOp(const ProgramState *state, BinaryOperator::Opcode op,
|
| /external/javassist/src/main/javassist/bytecode/ |
| Opcode.java | 26 public interface Opcode {
440 0, // wide, 196 depends on the following opcode
|
| /external/javassist/src/main/javassist/expr/ |
| Cast.java | 153 bytecode.addOpcode(Opcode.CHECKCAST);
|
| Instanceof.java | 157 bytecode.addOpcode(Opcode.INSTANCEOF);
|
| Expr.java | 35 import javassist.bytecode.Opcode;
44 public abstract class Expr implements Opcode {
|
| /external/llvm/lib/MC/ |
| MCDwarf.cpp | 35 // First special line opcode - leave room for the standard opcodes.
40 // Minimum line offset in a special line info. opcode. This value
44 // Range of line offsets in a special line info. opcode.
249 // Standard opcode lengths
346 uint64_t Temp, Opcode;
371 // If the line increment is out of range of a special opcode, we must encode
385 // Use DW_LNS_copy instead of a "line +0, addr +0" special opcode.
391 // Bias the opcode by the special opcode base.
396 // Try using a special opcode
[all...] |
| /external/llvm/lib/Target/Alpha/ |
| AlphaISelLowering.h | 54 /// OPC is the branch opcode to use (e.g. Alpha::BEQ),
82 const char *getTargetNodeName(unsigned Opcode) const;
|
| AlphaInstrInfo.cpp | 71 static bool isAlphaIntCondCode(unsigned Opcode) {
72 switch (Opcode) {
195 static unsigned AlphaRevCondCode(unsigned Opcode) {
196 switch (Opcode) {
212 llvm_unreachable("Unknown opcode");
329 assert(Cond.size() == 2 && "Invalid Alpha branch opcode!");
|
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelDAGToDAG.cpp | 336 unsigned Opcode = 0;
339 Opcode = MSP430::MOV8rm_POST;
342 Opcode = MSP430::MOV16rm_POST;
348 return CurDAG->getMachineNode(Opcode, N->getDebugLoc(),
|
| /external/llvm/lib/Target/PTX/ |
| PTXInstrInfo.cpp | 37 const int opcode; member in struct:map_entry
58 const MCInstrDesc &MCID = get(map[i].opcode);
80 const MCInstrDesc &MCID = get(map[i].opcode);
198 DEBUG(dbgs() << "AnalyzeBranch: opcode: " << instLast1.getOpcode() << "\n");
319 GetPTXMachineNode(SelectionDAG *DAG, unsigned Opcode,
324 return DAG->getMachineNode(Opcode, dl, VT, ops, array_lengthof(ops));
328 GetPTXMachineNode(SelectionDAG *DAG, unsigned Opcode,
333 return DAG->getMachineNode(Opcode, dl, VT, ops, array_lengthof(ops));
|
| /external/llvm/lib/Target/Sparc/ |
| SparcInstrInfo.cpp | 166 unsigned Opcode = I->getOpcode();
167 if (Opcode != SP::BCOND && Opcode != SP::FBCOND)
168 return true; //Unknown Opcode
194 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(Opcode))
|
| /external/llvm/utils/TableGen/ |
| DAGISelMatcher.cpp | 145 OS.indent(indent) << "CheckOpcode " << Opcode.getEnumName() << '\n';
279 return HashString(Opcode.getEnumName());
308 // to ensure that the nodes are for the same opcode.
309 return cast<CheckOpcodeMatcher>(M)->Opcode.getEnumName() ==
310 Opcode.getEnumName();
360 // to ensure that the nodes are for the same opcode.
368 // If checking for a result the opcode doesn't have, it can't match.
|
| /external/v8/src/mips/ |
| assembler-mips.h | 430 // Takes a branch opcode (cc) and a label (L) and generates
479 // Difference between address of current opcode and target address offset.
508 // Difference between address of current opcode and value read from pc
922 void GenInstrRegister(Opcode opcode,
929 void GenInstrRegister(Opcode opcode,
936 void GenInstrRegister(Opcode opcode,
943 void GenInstrRegister(Opcode opcode
[all...] |
| /external/javassist/src/main/javassist/compiler/ |
| MemberCodeGen.java | 106 b.addOpcode(Opcode.GOTO);
111 protected boolean doit(Bytecode b, int opcode) {
112 switch (opcode) {
113 case Opcode.RETURN :
159 protected boolean doit(Bytecode b, int opcode) {
160 switch (opcode) {
161 case Opcode.RETURN :
182 b.addOpcode(Opcode.GOTO);
210 bc.addOpcode(Opcode.GOTO);
236 bc.addOpcode(Opcode.GOTO)
[all...] |
| CodeGen.java | 28 public abstract class CodeGen extends Visitor implements Opcode, TokenId {
61 protected abstract boolean doit(Bytecode b, int opcode);
294 bytecode.addOpcode(Opcode.RETURN);
396 bytecode.addOpcode(Opcode.GOTO);
423 bytecode.addOpcode(Opcode.GOTO);
485 bytecode.addOpcode(Opcode.GOTO);
579 bytecode.addOpcode(Opcode.GOTO);
595 op = Opcode.RETURN;
657 protected boolean doit(Bytecode b, int opcode) {
673 bc.addOpcode(Opcode.GOTO)
[all...] |
| /external/llvm/lib/Target/ARM/InstPrinter/ |
| ARMInstPrinter.h | 29 virtual StringRef getOpcodeName(unsigned Opcode) const;
32 static const char *getInstructionName(unsigned Opcode);
|
| /external/llvm/lib/Target/MBlaze/ |
| MBlazeISelDAGToDAG.cpp | 190 unsigned Opcode = Node->getOpcode();
201 switch (Opcode) {
|
| /external/llvm/lib/Target/MBlaze/MCTargetDesc/ |
| MBlazeMCCodeEmitter.cpp | 182 unsigned Opcode = MI.getOpcode();
183 const MCInstrDesc &Desc = MCII.get(Opcode);
|
| /external/webkit/Source/WebCore/xml/ |
| XPathParser.cpp | 157 Token Parser::makeTokenAndAdvance(int code, NumericOp::Opcode val, int advance)
163 Token Parser::makeTokenAndAdvance(int code, EqTestOp::Opcode val, int advance)
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| FastISel.cpp | 319 /// which has an opcode which directly corresponds to the given ISD opcode.
413 // Target-specific code wasn't able to find a machine opcode for
414 // the given ISD opcode and type. Halt "fast" selection and bail.
664 bool FastISel::SelectCast(const User *I, unsigned Opcode) {
690 Opcode,
739 // If the reg-reg copy failed, select a BITCAST opcode.
880 FastISel::SelectOperator(const User *I, unsigned Opcode) {
881 switch (Opcode) {
[all...] |
| /external/clang/include/clang/AST/ |
| Expr.h | [all...] |
| /external/llvm/lib/Target/ARM/AsmParser/ |
| ARMAsmParser.cpp | 167 bool cvtT2LdrdPre(MCInst &Inst, unsigned Opcode,
169 bool cvtT2StrdPre(MCInst &Inst, unsigned Opcode,
171 bool cvtLdWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode,
173 bool cvtStWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode,
175 bool cvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
177 bool cvtLdWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
179 bool cvtStWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
181 bool cvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
183 bool cvtStWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
185 bool cvtLdExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
[all...] |
