| /external/expat/bcb5/ |
| expatw.mak | 147 .PATH.RC = $(PATHRC)
181 .rc.res:
|
| expatw_static.mak | 148 .PATH.RC = $(PATHRC)
184 .rc.res:
|
| outline.mak | 146 .PATH.RC = $(PATHRC)
180 .rc.res:
|
| xmlwf.mak | 147 .PATH.RC = $(PATHRC)
181 .rc.res:
|
| /external/llvm/lib/CodeGen/ |
| PHIElimination.cpp | 227 const TargetRegisterClass *RC = MF.getRegInfo().getRegClass(DestReg);
228 entry = IncomingReg = MF.getRegInfo().createVirtualRegister(RC);
|
| PeepholeOptimizer.cpp | 235 const TargetRegisterClass *RC = MRI->getRegClass(SrcReg);
243 unsigned NewVR = MRI->createVirtualRegister(RC);
|
| StrongPHIElimination.cpp | 692 const TargetRegisterClass *RC = MRI->getRegClass(SrcReg);
693 CopyReg = MRI->createVirtualRegister(RC);
764 const TargetRegisterClass *RC = MRI->getRegClass(DestReg);
765 unsigned CopyReg = MRI->createVirtualRegister(RC);
[all...] |
| TailDuplication.cpp | 386 const TargetRegisterClass *RC = MRI->getRegClass(DefReg);
391 unsigned NewDef = MRI->createVirtualRegister(RC);
423 const TargetRegisterClass *RC = MRI->getRegClass(Reg);
424 unsigned NewReg = MRI->createVirtualRegister(RC);
[all...] |
| MachineLICM.cpp | 671 const TargetRegisterClass *RC = MRI->getRegClass(Reg);
672 EVT VT = *RC->vt_begin();
674 RCId = RC->getID();
[all...] |
| TwoAddressInstructionPass.cpp | 90 bool isProfitableToReMat(unsigned Reg, const TargetRegisterClass *RC,
307 const TargetRegisterClass *RC,
1175 const TargetRegisterClass *rc = MRI->getRegClass(regB); local
[all...] |
| RegisterCoalescer.cpp | 826 const TargetRegisterClass *RC = TII->getRegClass(MCID, 0, TRI);
828 if (MRI->getRegClass(DstReg) != RC)
830 } else if (!RC->contains(DstReg))
[all...] |
| RegAllocPBQP.cpp | 499 const TargetRegisterClass *RC = mri->getRegClass(spilled->reg);
500 LiveInterval &stackInterval = lss->getOrCreateInterval(stackSlot, RC);
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| TargetLowering.cpp | 703 bool TargetLowering::isLegalRC(const TargetRegisterClass *RC) const {
704 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
715 TargetLowering::hasLegalSuperRegRegClasses(const TargetRegisterClass *RC) const{
716 if (*RC->superregclasses_begin() == 0)
718 for (TargetRegisterInfo::regclass_iterator I = RC->superregclasses_begin(),
719 E = RC->superregclasses_end(); I != E; ++I) {
731 const TargetRegisterClass *RC = RegClassForVT[VT.getSimpleVT().SimpleTy];
732 if (!RC)
733 return std::make_pair(RC, 0)
[all...] |
| ScheduleDAGRRList.cpp | 298 const TargetRegisterClass *RC = TRI->getRegClass(DstRCIdx);
299 RegClass = RC->getID();
306 const TargetRegisterClass *RC = TII->getRegClass(Desc, Idx, TRI);
307 RegClass = RC->getID();
[all...] |
| /external/llvm/lib/Target/PTX/ |
| PTXInstrInfo.cpp | 303 const TargetRegisterClass *RC,
311 const TargetRegisterClass *RC,
|
| /external/llvm/lib/Target/ARM/ |
| ARMBaseInstrInfo.cpp | 704 const TargetRegisterClass *RC,
719 switch (RC->getSize()) {
721 if (ARM::GPRRegClass.hasSubClassEq(RC)) {
725 } else if (ARM::SPRRegClass.hasSubClassEq(RC)) {
733 if (ARM::DPRRegClass.hasSubClassEq(RC)) {
741 if (ARM::QPRRegClass.hasSubClassEq(RC)) {
757 if (ARM::QQPRRegClass.hasSubClassEq(RC)) {
779 if (ARM::QQQQPRRegClass.hasSubClassEq(RC)) {
856 const TargetRegisterClass *RC,
870 switch (RC->getSize())
[all...] |
| Thumb1RegisterInfo.cpp | 49 Thumb1RegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC)
51 if (ARM::tGPRRegClass.hasSubClassEq(RC))
53 return ARMBaseRegisterInfo::getLargestLegalSuperClass(RC);
551 const TargetRegisterClass *RC,
|
| ARMFrameLowering.cpp | [all...] |
| /external/llvm/lib/Target/Blackfin/ |
| BlackfinISelLowering.cpp | 186 TargetRegisterClass *RC = VA.getLocReg() == BF::P0 ?
188 assert(RC->contains(VA.getLocReg()) && "Unexpected regclass in CCState");
189 assert(RC->hasType(RegVT) && "Unexpected regclass in CCState");
191 unsigned Reg = MF.getRegInfo().createVirtualRegister(RC);
|
| /external/llvm/utils/TableGen/ |
| DAGISelMatcherGen.cpp | 31 for (unsigned rc = 0, e = RCs.size(); rc != e; ++rc) {
32 const CodeGenRegisterClass &RC = *RCs[rc];
33 if (!RC.contains(Reg))
38 VT = RC.getValueTypeNum(0);
43 assert(VT == RC.getValueTypeNum(0));
[all...] |
| AsmMatcherEmitter.cpp | [all...] |
| /frameworks/base/media/libstagefright/rtsp/ |
| ARTPConnection.cpp | 597 size_t RC = data[0] & 0x1f;
599 if (size < (7 + RC * 6) * 4) {
|
| /external/llvm/include/llvm/CodeGen/ |
| MachineFunction.h | 284 unsigned addLiveIn(unsigned PReg, const TargetRegisterClass *RC);
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCFrameLowering.cpp | 778 const TargetRegisterClass *RC = isPPC64 ? G8RC : GPRC;
779 RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
780 RC->getAlignment(),
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86FrameLowering.cpp | [all...] |
