| /external/llvm/lib/Target/MSP430/ |
| MSP430InstrInfo.h | 64 const TargetRegisterClass *RC,
69 const TargetRegisterClass *RC,
|
| MSP430InstrInfo.cpp | 38 const TargetRegisterClass *RC,
52 if (RC == &MSP430::GR16RegClass)
56 else if (RC == &MSP430::GR8RegClass)
67 const TargetRegisterClass *RC,
81 if (RC == &MSP430::GR16RegClass)
84 else if (RC == &MSP430::GR8RegClass)
|
| /external/llvm/lib/Target/Sparc/ |
| SparcInstrInfo.h | 86 const TargetRegisterClass *RC,
92 const TargetRegisterClass *RC,
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| /external/llvm/lib/Target/SystemZ/ |
| SystemZInstrInfo.h | 77 const TargetRegisterClass *RC,
82 const TargetRegisterClass *RC,
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| SystemZInstrInfo.cpp | 46 const TargetRegisterClass *RC,
52 if (RC == &SystemZ::GR32RegClass ||
53 RC == &SystemZ::ADDR32RegClass)
55 else if (RC == &SystemZ::GR64RegClass ||
56 RC == &SystemZ::ADDR64RegClass) {
58 } else if (RC == &SystemZ::FP32RegClass) {
60 } else if (RC == &SystemZ::FP64RegClass) {
62 } else if (RC == &SystemZ::GR64PRegClass) {
64 } else if (RC == &SystemZ::GR128RegClass) {
76 const TargetRegisterClass *RC,
[all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreInstrInfo.h | 72 const TargetRegisterClass *RC,
78 const TargetRegisterClass *RC,
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| XCoreFrameLowering.cpp | 296 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
298 it->getFrameIdx(), RC, TRI);
322 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
324 RC, TRI);
345 const TargetRegisterClass *RC = XCore::GRRegsRegisterClass;
354 FrameIdx = MFI->CreateFixedObject(RC->getSize(), 0, true);
356 FrameIdx = MFI->CreateStackObject(RC->getSize(), RC->getAlignment(),
364 RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
365 RC->getAlignment()
[all...] |
| /external/llvm/lib/Target/Blackfin/ |
| BlackfinISelDAGToDAG.cpp | 119 static inline bool isCC(const TargetRegisterClass *RC) {
120 return BF::AnyCCRegClass.hasSubClassEq(RC);
123 static inline bool isDCC(const TargetRegisterClass *RC) {
124 return BF::DRegClass.hasSubClassEq(RC) || isCC(RC);
|
| BlackfinFrameLowering.cpp | 122 const TargetRegisterClass *RC = BF::DPRegisterClass;
126 RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
127 RC->getAlignment(),
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| /external/llvm/include/llvm/Support/ |
| IRBuilder.h | 503 if (Constant *RC = dyn_cast<Constant>(RHS))
504 return Insert(Folder.CreateAdd(LC, RC, HasNUW, HasNSW), Name);
516 if (Constant *RC = dyn_cast<Constant>(RHS))
517 return Insert(Folder.CreateFAdd(LC, RC), Name);
523 if (Constant *RC = dyn_cast<Constant>(RHS))
524 return Insert(Folder.CreateSub(LC, RC), Name);
536 if (Constant *RC = dyn_cast<Constant>(RHS))
537 return Insert(Folder.CreateFSub(LC, RC), Name);
543 if (Constant *RC = dyn_cast<Constant>(RHS))
544 return Insert(Folder.CreateMul(LC, RC), Name)
[all...] |
| /external/clang/test/SemaCXX/ |
| nested-name-spec.cpp | 71 struct RC;
77 struct A2::RC {
101 void f6(int A2::RC::x); // expected-error{{parameter declarator cannot be qualified}}
103 int A2::RC::x; // expected-error{{non-static data member defined out-of-line}}
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| InstrEmitter.cpp | 116 const TargetRegisterClass *RC = 0;
118 RC = TII->getRegClass(II, i+II.getNumDefs(), TRI);
120 UseRC = RC;
121 else if (RC) {
123 TRI->getCommonSubClass(UseRC, RC);
199 const TargetRegisterClass *RC = TII->getRegClass(II, i, TRI);
218 if (RegRC == RC) {
230 assert(RC && "Isn't a register operand!");
231 VRBase = MRI->createVirtualRegister(RC);
255 const TargetRegisterClass *RC = TLI->getRegClassFor(Op.getValueType())
[all...] |
| /external/llvm/utils/TableGen/ |
| CodeGenIntrinsics.h | 86 std::vector<CodeGenIntrinsic> LoadIntrinsics(const RecordKeeper &RC,
|
| CodeGenRegisters.h | 138 // Returns true if RC is a subclass.
139 // RC is a sub-class of this class if it is a valid replacement for any
143 // 1. All RC registers are also in this.
144 // 2. The RC spill size must not be smaller than our spill size.
145 // 3. RC spill alignment must be compatible with ours.
147 bool hasSubClass(const CodeGenRegisterClass *RC) const {
148 return SubClasses.test(RC->EnumValue);
204 Key(const CodeGenRegisterClass &RC)
205 : Members(&RC.getMembers()),
206 SpillSize(RC.SpillSize)
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsInstrInfo.h | 165 const TargetRegisterClass *RC,
171 const TargetRegisterClass *RC,
|
| MipsInstrInfo.cpp | 168 const TargetRegisterClass *RC,
174 if (RC == Mips::CPURegsRegisterClass)
176 else if (RC == Mips::CPU64RegsRegisterClass)
178 else if (RC == Mips::FGR32RegisterClass)
180 else if (RC == Mips::AFGR64RegisterClass)
182 else if (RC == Mips::FGR64RegisterClass)
193 const TargetRegisterClass *RC,
200 if (RC == Mips::CPURegsRegisterClass)
202 else if (RC == Mips::CPU64RegsRegisterClass)
204 else if (RC == Mips::FGR32RegisterClass
[all...] |
| /external/llvm/lib/CodeGen/ |
| MachineRegisterInfo.cpp | 46 MachineRegisterInfo::setRegClass(unsigned Reg, const TargetRegisterClass *RC) {
47 VRegInfo[Reg].first = RC;
52 const TargetRegisterClass *RC,
55 if (OldRC == RC)
56 return RC;
57 const TargetRegisterClass *NewRC = TRI->getCommonSubClass(OldRC, RC);
|
| ExecutionDepsFix.cpp | 110 const TargetRegisterClass *const RC;
123 ExeDepsFix(const TargetRegisterClass *rc)
124 : MachineFunctionPass(ID), RC(rc), NumRegs(RC->getNumRegs()) {}
457 assert(NumRegs == RC->getNumRegs() && "Bad regclass");
462 for (TargetRegisterClass::const_iterator I = RC->begin(), E = RC->end();
472 // Given a PhysReg, AliasMap[PhysReg] is either the relevant index into RC,
475 for (unsigned i = 0, e = RC->getNumRegs(); i != e; ++i
[all...] |
| TargetInstrInfoImpl.cpp | 248 const TargetRegisterClass *RC = MRI.getRegClass(FoldReg);
251 return RC->contains(LiveOp.getReg()) ? RC : 0;
253 if (RC->hasSubClassEq(MRI.getRegClass(LiveReg)))
254 return RC;
313 const TargetRegisterClass *RC = canFoldCopy(MI, Ops[0]);
314 if (!RC)
322 storeRegToStackSlot(*MBB, Pos, MO.getReg(), MO.isKill(), FI, RC, TRI);
324 loadRegFromStackSlot(*MBB, Pos, MO.getReg(), FI, RC, TRI);
|
| VirtRegMap.cpp | 103 unsigned VirtRegMap::createSpillSlot(const TargetRegisterClass *RC) {
104 int SS = MF->getFrameInfo()->CreateSpillStackObject(RC->getSize(),
105 RC->getAlignment());
133 const TargetRegisterClass* RC = MF->getRegInfo().getRegClass(virtReg);
134 return Virt2StackSlotMap[virtReg] = createSpillSlot(RC);
162 int VirtRegMap::getEmergencySpillSlot(const TargetRegisterClass *RC) {
164 EmergencySpillSlots.find(RC);
167 return EmergencySpillSlots[RC] = createSpillSlot(RC);
|
| /external/llvm/lib/Target/ARM/ |
| Thumb2InstrInfo.cpp | 122 const TargetRegisterClass *RC,
124 if (RC == ARM::GPRRegisterClass || RC == ARM::tGPRRegisterClass ||
125 RC == ARM::tcGPRRegisterClass || RC == ARM::rGPRRegisterClass ||
126 RC == ARM::GPRnopcRegisterClass) {
144 ARMBaseInstrInfo::storeRegToStackSlot(MBB, I, SrcReg, isKill, FI, RC, TRI);
150 const TargetRegisterClass *RC,
152 if (RC == ARM::GPRRegisterClass || RC == ARM::tGPRRegisterClass |
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCInstrInfo.cpp | 342 const TargetRegisterClass *RC,
345 if (PPC::GPRCRegisterClass->hasSubClassEq(RC)) {
361 } else if (PPC::G8RCRegisterClass->hasSubClassEq(RC)) {
377 } else if (PPC::F8RCRegisterClass->hasSubClassEq(RC)) {
382 } else if (PPC::F4RCRegisterClass->hasSubClassEq(RC)) {
387 } else if (PPC::CRRCRegisterClass->hasSubClassEq(RC)) {
425 } else if (PPC::CRBITRCRegisterClass->hasSubClassEq(RC)) {
459 } else if (PPC::VRRCRegisterClass->hasSubClassEq(RC)) {
482 const TargetRegisterClass *RC,
487 if (StoreRegToStackSlot(MF, SrcReg, isKill, FrameIdx, RC, NewMIs))
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86InstrInfo.h | 228 const TargetRegisterClass *RC,
233 const TargetRegisterClass *RC,
241 const TargetRegisterClass *RC,
246 const TargetRegisterClass *RC,
330 bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const;
|
| /external/llvm/lib/Target/Alpha/ |
| AlphaInstrInfo.cpp | 146 const TargetRegisterClass *RC,
155 if (RC == Alpha::F4RCRegisterClass)
159 else if (RC == Alpha::F8RCRegisterClass)
163 else if (RC == Alpha::GPRCRegisterClass)
175 const TargetRegisterClass *RC,
182 if (RC == Alpha::F4RCRegisterClass)
185 else if (RC == Alpha::F8RCRegisterClass)
188 else if (RC == Alpha::GPRCRegisterClass)
|
| /external/llvm/lib/Target/PTX/ |
| PTXInstrInfo.h | 105 const TargetRegisterClass* RC,
110 const TargetRegisterClass *RC,
|
