| /external/llvm/lib/Target/Sparc/ |
| SparcInstrInfo.cpp | 289 const TargetRegisterClass *RC,
295 if (RC == SP::IntRegsRegisterClass)
298 else if (RC == SP::FPRegsRegisterClass)
301 else if (RC == SP::DFPRegsRegisterClass)
311 const TargetRegisterClass *RC,
316 if (RC == SP::IntRegsRegisterClass)
318 else if (RC == SP::FPRegsRegisterClass)
320 else if (RC == SP::DFPRegsRegisterClass)
|
| /external/llvm/lib/Target/X86/ |
| X86FastISel.cpp | 180 const TargetRegisterClass *RC = NULL;
186 RC = X86::GR8RegisterClass;
190 RC = X86::GR16RegisterClass;
194 RC = X86::GR32RegisterClass;
199 RC = X86::GR64RegisterClass;
204 RC = X86::FR32RegisterClass;
207 RC = X86::RFP32RegisterClass;
213 RC = X86::FR64RegisterClass;
216 RC = X86::RFP64RegisterClass;
224 ResultReg = createResultReg(RC);
[all...] |
| X86RegisterInfo.cpp | 115 X86RegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC,
123 return X86GenRegisterInfo::getSubClassWithSubReg(RC, Idx);
248 X86RegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC) const{
257 if (RC == X86::GR8_NOREXRegisterClass)
258 return RC;
260 const TargetRegisterClass *Super = RC;
261 TargetRegisterClass::sc_iterator I = RC->getSuperClasses();
277 if (Super->getSize() == RC->getSize())
282 return RC;
307 X86RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const
[all...] |
| X86InstrInfo.cpp | [all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMFastISel.cpp | 110 const TargetRegisterClass *RC);
112 const TargetRegisterClass *RC,
115 const TargetRegisterClass *RC,
119 const TargetRegisterClass *RC,
124 const TargetRegisterClass *RC,
128 const TargetRegisterClass *RC,
132 const TargetRegisterClass *RC,
137 const TargetRegisterClass *RC,
140 const TargetRegisterClass *RC,
279 const TargetRegisterClass* RC) {
[all...] |
| ARMBaseRegisterInfo.cpp | 237 ARMBaseRegisterInfo::canCombineSubRegIndices(const TargetRegisterClass *RC,
241 unsigned Size = RC->getSize() * 8;
353 ARMBaseRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC)
355 const TargetRegisterClass *Super = RC;
356 TargetRegisterClass::sc_iterator I = RC->getSuperClasses();
369 return RC;
378 ARMBaseRegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
379 if (RC == &ARM::CCRRegClass)
381 return RC;
385 ARMBaseRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| Passes.h | 233 /// The pass will examine instructions using and defining registers in RC.
235 FunctionPass *createExecutionDependencyFixPass(const TargetRegisterClass *RC);
|
| LiveStackAnalysis.h | 57 LiveInterval &getOrCreateInterval(int Slot, const TargetRegisterClass *RC);
|
| RegisterScavenging.h | 103 BitVector getRegsAvailable(const TargetRegisterClass *RC);
|
| /external/llvm/lib/CodeGen/ |
| CriticalAntiDepBreaker.h | 106 const TargetRegisterClass *RC);
|
| VirtRegRewriter.cpp | 417 unsigned GetRegForReload(const TargetRegisterClass *RC, unsigned PhysReg,
445 const TargetRegisterClass* RC = MF.getRegInfo().getRegClass(VirtReg);
446 return GetRegForReload(RC, PhysReg, MF, MI, Spills, MaybeDeadStores,
705 static unsigned findSuperReg(const TargetRegisterClass *RC, unsigned SubReg,
707 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end();
787 const TargetRegisterClass* RC = TRI->getMinimalPhysRegClass(Reg);
791 if (!TII->isSafeToMoveRegClassDefs(RC))
[all...] |
| RegAllocLinearScan.cpp | 267 const TargetRegisterClass *RC);
354 const TargetRegisterClass *RC,
361 unsigned getFirstNonReservedPhysReg(const TargetRegisterClass *RC) {
362 ArrayRef<unsigned> O = RegClassInfo.getOrder(RC);
489 const TargetRegisterClass *RC = mri_->getRegClass(cur.reg);
490 if (!RC->contains(CandReg))
773 const TargetRegisterClass *RC) {
784 RC->contains(*as)) {
[all...] |
| PrologEpilogInserter.cpp | 253 const TargetRegisterClass *RC = RegInfo->getMinimalPhysRegClass(Reg);
270 unsigned Align = RC->getAlignment();
277 FrameIdx = MFI->CreateStackObject(RC->getSize(), Align, true);
282 FrameIdx = MFI->CreateFixedObject(RC->getSize(), FixedSlot->Offset, true);
321 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
323 CSI[i].getFrameIdx(), RC, TRI);
348 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
351 RC, TRI);
396 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
400 RC, TRI)
[all...] |
| RegAllocFast.cpp | 150 int getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC);
176 int RAFast::getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC) {
183 int FrameIdx = MF->getFrameInfo()->CreateSpillStackObject(RC->getSize(),
184 RC->getAlignment());
266 const TargetRegisterClass *RC = MRI->getRegClass(LRI->first);
267 int FI = getStackSpaceFor(LRI->first, RC);
269 TII->storeRegToStackSlot(*MBB, MI, LR.PhysReg, SpillKill, FI, RC, TRI);
485 const TargetRegisterClass *RC = MRI->getRegClass(VirtReg);
489 !RC->contains(Hint) || !RegClassInfo.isAllocatable(Hint)))
503 ArrayRef<unsigned> AO = RegClassInfo.getOrder(RC);
[all...] |
| StackSlotColoring.cpp | 142 unsigned Reg, const TargetRegisterClass *RC,
275 const TargetRegisterClass *RC = LS->getIntervalRegClass(RSS);
278 if (!RC) {
282 unsigned Reg = VRM->getFirstUnusedRegister(RC);
421 const TargetRegisterClass *RC = LS->getIntervalRegClass(SS);
430 UnfoldAndRewriteInstruction(RefMIs[i], SS, NewFI, RC, Defs, MF);
524 const TargetRegisterClass *RC = TII->getRegClass(MCID, i, TRI);
525 if (RC && !RC->contains(NewReg))
586 const TargetRegisterClass *RC = TII->getRegClass(MCID, i, TRI)
[all...] |
| AggressiveAntiDepBreaker.h | 44 /// RC - The register class
45 const TargetRegisterClass *RC;
|
| VirtRegMap.h | 138 /// createSpillSlot - Allocate a spill slot for RC from MFI.
139 unsigned createSpillSlot(const TargetRegisterClass *RC);
427 int getEmergencySpillSlot(const TargetRegisterClass *RC);
501 unsigned getFirstUnusedRegister(const TargetRegisterClass *RC) {
504 if (allocatableRCRegs[RC][Reg])
|
| AggressiveAntiDepBreaker.cpp | 405 const TargetRegisterClass *RC = NULL;
407 RC = TII->getRegClass(MI->getDesc(), i, TRI);
408 AggressiveAntiDepState::RegisterReference RR = { &MO, RC };
480 const TargetRegisterClass *RC = NULL;
482 RC = TII->getRegClass(MI->getDesc(), i, TRI);
483 AggressiveAntiDepState::RegisterReference RR = { &MO, RC };
529 const TargetRegisterClass *RC = Q->second.RC;
530 if (RC == NULL) continue;
532 BitVector RCBV = TRI->getAllocatableSet(MF, RC);
[all...] |
| CriticalAntiDepBreaker.cpp | 386 const TargetRegisterClass *RC)
388 ArrayRef<unsigned> Order = RegClassInfo.getOrder(RC);
597 const TargetRegisterClass *RC = AntiDepReg != 0 ? Classes[AntiDepReg] : 0;
598 assert((AntiDepReg == 0 || RC != NULL) &&
600 if (RC == reinterpret_cast<TargetRegisterClass *>(-1))
614 RC)) {
|
| /external/dropbear/libtomcrypt/src/ciphers/ |
| noekeon.c | 33 static const ulong32 RC[] = {
129 a ^= RC[i]; \
141 a ^= RC[16];
185 a ^= RC[i]; \
197 a ^= RC[0];
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| FastISel.cpp | 592 const TargetRegisterClass *RC = TLI.getRegClassFor(VT);
593 unsigned ResultReg = createResultReg(RC);
616 const TargetRegisterClass *RC = TLI.getRegClassFor(SrcVT);
617 unsigned ResultReg = createResultReg(RC);
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsISelLowering.cpp | 692 AddLiveIn(MachineFunction &MF, unsigned PReg, TargetRegisterClass *RC)
694 assert(RC->contains(PReg) && "Not the correct regclass!");
695 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC);
[all...] |
| /external/llvm/lib/Target/MBlaze/ |
| MBlazeInstrInfo.h | 218 const TargetRegisterClass *RC,
224 const TargetRegisterClass *RC,
|
| /external/llvm/utils/TableGen/ |
| FastISelEmitter.cpp | 36 const CodeGenRegisterClass *RC;
250 const CodeGenRegisterClass *RC = 0;
254 RC = &Target.getRegisterClass(OpLeafRec);
256 RC = Target.getRegBank().getRegClassForRegister(OpLeafRec);
261 if (!RC)
267 if (DstRC != RC && !DstRC->hasSubClass(RC))
270 DstRC = RC;
643 OS << InstNS << Memo.RC->getName() << "RegisterClass";
735 OS << InstNS << Memo.RC->getName() << "RegisterClass"
[all...] |
| /external/llvm/include/llvm/Target/ |
| TargetInstrInfo.h | 372 const TargetRegisterClass *RC,
384 const TargetRegisterClass *RC,
571 virtual bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
[all...] |
