| /external/llvm/lib/CodeGen/SelectionDAG/ |
| TargetLowering.cpp | [all...] |
| LegalizeVectorOps.cpp | 129 if (Op.getOpcode() == ISD::LOAD) {
138 } else if (Op.getOpcode() == ISD::STORE) {
165 switch (Op.getOpcode()) {
230 switch (TLI.getOperationAction(Node->getOpcode(), QueryType)) {
246 if (Node->getOpcode() == ISD::VSELECT)
248 else if (Node->getOpcode() == ISD::UINT_TO_FP)
250 else if (Node->getOpcode() == ISD::FNEG)
252 else if (Node->getOpcode() == ISD::SETCC)
278 EVT NVT = TLI.getTypeToPromoteTo(Op.getOpcode(), VT);
289 Op = DAG.getNode(Op.getOpcode(), dl, NVT, &Operands[0], Operands.size())
[all...] |
| /external/llvm/include/llvm/ |
| Instructions.h | 115 return (I->getOpcode() == Instruction::Alloca);
235 return I->getOpcode() == Instruction::Load;
357 return I->getOpcode() == Instruction::Store;
429 return I->getOpcode() == Instruction::Fence;
529 return I->getOpcode() == Instruction::AtomicCmpXchg;
673 return I->getOpcode() == Instruction::AtomicRMW;
833 return (I->getOpcode() == Instruction::GetElementPtr);
[all...] |
| /dalvik/dexgen/src/com/android/dexgen/dex/code/ |
| CstInsn.java | 88 new CstInsn(getOpcode(), getPosition(), registers, constant);
|
| Dop.java | 85 public int getOpcode() {
|
| OutputFinisher.java | 369 result[i] = insns.get(i).getOpcode().getFormat();
496 Dop dop = insn.getOpcode();
545 Dop dop = insn.getOpcode();
578 Dop dop = insn.getOpcode();
598 originalFormat = insn.getOpcode().getFormat();
672 Dop dop = insn.getOpcode();
|
| /dalvik/dexgen/src/com/android/dexgen/rop/code/ |
| DexTranslationAdvice.java | 70 switch (opcode.getOpcode()) {
|
| /dalvik/dx/src/com/android/dx/dex/code/ |
| CstInsn.java | 88 new CstInsn(getOpcode(), getPosition(), registers, constant);
|
| Dop.java | 96 public int getOpcode() {
|
| InsnFormat.java | 57 String op = insn.getOpcode().getName();
489 int opcode = insn.getOpcode().getOpcode();
508 int opcode = insn.getOpcode().getOpcode();
|
| /external/clang/lib/StaticAnalyzer/Checkers/ |
| DivZeroChecker.cpp | 34 BinaryOperator::Opcode Op = B->getOpcode();
|
| PointerSubChecker.cpp | 39 if (B->getOpcode() != BO_Sub)
|
| /external/llvm/lib/Target/MSP430/ |
| MSP430RegisterInfo.cpp | 122 if (Old->getOpcode() == TII.getCallFrameSetupOpcode()) {
127 assert(Old->getOpcode() == TII.getCallFrameDestroyOpcode());
145 } else if (I->getOpcode() == TII.getCallFrameDestroyOpcode()) {
195 if (MI.getOpcode() == MSP430::ADD16ri) {
|
| /external/llvm/lib/Target/PowerPC/MCTargetDesc/ |
| PPCMCCodeEmitter.cpp | 170 assert((MI.getOpcode() == PPC::MTCRF || MI.getOpcode() == PPC::MFOCRF) &&
182 assert((MI.getOpcode() != PPC::MTCRF && MI.getOpcode() != PPC::MFOCRF) ||
|
| /external/llvm/lib/Target/ARM/ |
| Thumb1FrameLowering.cpp | 118 if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tPUSH) {
208 if (MI->getOpcode() == ARM::tLDRspi &&
212 else if (MI->getOpcode() == ARM::tPOP) {
226 assert((MBBI->getOpcode() == ARM::tBX_RET ||
227 MBBI->getOpcode() == ARM::tPOP_RET) &&
278 if (MBBI->getOpcode() == ARM::tBX_RET &&
280 prior(MBBI)->getOpcode() == ARM::tPOP) {
|
| /external/llvm/lib/VMCore/ |
| Instruction.cpp | 185 if (getOpcode() != I->getOpcode() ||
240 if (getOpcode() != I->getOpcode() ||
316 switch (getOpcode()) {
336 switch (getOpcode()) {
400 switch (getOpcode()) {
|
| /external/webkit/Source/JavaScriptCore/bytecode/ |
| CodeBlock.cpp | 290 if (vPC[0].u.opcode == interpreter->getOpcode(op_get_by_id)) {
294 if (vPC[0].u.opcode == interpreter->getOpcode(op_get_by_id_self)) {
298 if (vPC[0].u.opcode == interpreter->getOpcode(op_get_by_id_proto)) {
302 if (vPC[0].u.opcode == interpreter->getOpcode(op_put_by_id_transition)) {
306 if (vPC[0].u.opcode == interpreter->getOpcode(op_get_by_id_chain)) {
310 if (vPC[0].u.opcode == interpreter->getOpcode(op_put_by_id)) {
314 if (vPC[0].u.opcode == interpreter->getOpcode(op_put_by_id_replace)) {
318 if (vPC[0].u.opcode == interpreter->getOpcode(op_resolve_global)) {
322 if (vPC[0].u.opcode == interpreter->getOpcode(op_resolve_global_dynamic)) {
328 ASSERT(vPC[0].u.opcode == interpreter->getOpcode(op_get_by_id_generic) || vPC[0].u.opcode == interpreter->getOpcode(op_put_by_id_generic) || vPC[0] (…)
[all...] |
| /external/llvm/lib/Transforms/InstCombine/ |
| InstructionCombining.cpp | 113 // The No Signed Wrap flag can be kept if the operation "B (I.getOpcode) C",
124 Instruction::BinaryOps Opcode = I.getOpcode();
172 Instruction::BinaryOps Opcode = I.getOpcode();
188 if (Op0 && Op0->getOpcode() == Opcode) {
217 if (Op1 && Op1->getOpcode() == Opcode) {
239 if (Op0 && Op0->getOpcode() == Opcode) {
259 if (Op1 && Op1->getOpcode() == Opcode) {
281 Op0->getOpcode() == Opcode && Op1->getOpcode() == Opcode &&
370 Instruction::BinaryOps TopLevelOpcode = I.getOpcode(); // o
[all...] |
| InstCombineMulDivRem.cpp | 57 if (I->getOpcode() == Instruction::LShr && !I->isExact()) {
62 if (I->getOpcode() == Instruction::Shl && !I->hasNoUnsignedWrap()) {
116 if (SI->getOpcode() == Instruction::Shl)
185 (BO->getOpcode() != Instruction::UDiv &&
186 BO->getOpcode() != Instruction::SDiv)) {
193 (BO->getOpcode() == Instruction::UDiv ||
194 BO->getOpcode() == Instruction::SDiv)) {
206 if (BO->getOpcode() == Instruction::UDiv)
387 if (Instruction::BinaryOps(LHS->getOpcode()) == I.getOpcode())
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86ISelDAGToDAG.cpp | 303 if (N.getOpcode() != ISD::LOAD)
308 switch (U->getOpcode()) {
347 if (Op1.getOpcode() == X86ISD::Wrapper) {
349 if (Val.getOpcode() == ISD::TargetGlobalTLSAddress)
368 assert(Chain.getOpcode() == ISD::TokenFactor &&
409 while (HasCallSeq && Chain.getOpcode() != ISD::CALLSEQ_START) {
419 if (Chain.getOperand(0).getOpcode() == ISD::TokenFactor &&
435 (N->getOpcode() == X86ISD::CALL ||
436 N->getOpcode() == X86ISD::TC_RETURN)) {
456 bool HasCallSeq = N->getOpcode() == X86ISD::CALL
[all...] |
| X86FloatingPoint.cpp | 837 int Opcode = Lookup(PopTable, array_lengthof(PopTable), I->getOpcode());
[all...] |
| /dalvik/dx/src/com/android/dx/ssa/ |
| SCCP.java | 242 Rop opcode = insn.getOpcode();
275 switch (opcode.getOpcode()) {
307 switch (opcode.getOpcode()) {
368 int opcode = insn.getOpcode().getOpcode();
472 if (ropInsn.getOpcode().getBranchingness() != Rop.BRANCH_NONE
473 || ropInsn.getOpcode().isCallLike()) {
477 int opcode = insn.getOpcode().getOpcode();
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelDAGToDAG.cpp | 260 if (N->getOpcode() != ISD::Constant)
278 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i32) {
288 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i64) {
306 return N->getOpcode() == Opc
341 unsigned Opcode = N->getOpcode();
388 unsigned Op0Opc = Op0.getOpcode();
389 unsigned Op1Opc = Op1.getOpcode();
397 if (Op0.getOperand(0).getOpcode() == ISD::SHL ||
398 Op0.getOperand(0).getOpcode() == ISD::SRL) {
399 if (Op1.getOperand(0).getOpcode() != ISD::SHL &
[all...] |
| /external/llvm/lib/Target/X86/MCTargetDesc/ |
| X86AsmBackend.cpp | 219 if (getRelaxedOpcodeBranch(Inst.getOpcode()) != Inst.getOpcode())
226 if (getRelaxedOpcodeArith(Inst.getOpcode()) == Inst.getOpcode())
251 unsigned RelaxedOp = getRelaxedOpcode(Inst.getOpcode());
253 if (RelaxedOp == Inst.getOpcode()) {
|
| /external/llvm/lib/Transforms/Utils/ |
| SimplifyIndVar.cpp | 97 switch (UseInst->getOpcode()) {
119 if (UseInst->getOpcode() == Instruction::LShr) {
253 bool IsSigned = Rem->getOpcode() == Instruction::SRem;
254 if (IsSigned || Rem->getOpcode() == Instruction::URem) {
422 bool IsSigned = Rem->getOpcode() == Instruction::SRem;
423 if (IsSigned || Rem->getOpcode() == Instruction::URem) {
|
