1 //===-- ARMAsmBackend.cpp - ARM Assembler Backend -------------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #include "MCTargetDesc/ARMMCTargetDesc.h" 11 #include "MCTargetDesc/ARMBaseInfo.h" 12 #include "MCTargetDesc/ARMFixupKinds.h" 13 #include "MCTargetDesc/ARMAddressingModes.h" 14 #include "llvm/ADT/Twine.h" 15 #include "llvm/MC/MCAssembler.h" 16 #include "llvm/MC/MCDirectives.h" 17 #include "llvm/MC/MCELFObjectWriter.h" 18 #include "llvm/MC/MCExpr.h" 19 #include "llvm/MC/MCMachObjectWriter.h" 20 #include "llvm/MC/MCObjectWriter.h" 21 #include "llvm/MC/MCSectionELF.h" 22 #include "llvm/MC/MCSectionMachO.h" 23 #include "llvm/MC/MCAsmBackend.h" 24 #include "llvm/MC/MCSubtargetInfo.h" 25 #include "llvm/Object/MachOFormat.h" 26 #include "llvm/Support/ELF.h" 27 #include "llvm/Support/ErrorHandling.h" 28 #include "llvm/Support/raw_ostream.h" 29 using namespace llvm; 30 31 namespace { 32 class ARMELFObjectWriter : public MCELFObjectTargetWriter { 33 public: 34 ARMELFObjectWriter(Triple::OSType OSType) 35 : MCELFObjectTargetWriter(/*Is64Bit*/ false, OSType, ELF::EM_ARM, 36 /*HasRelocationAddend*/ false) {} 37 }; 38 39 class ARMAsmBackend : public MCAsmBackend { 40 const MCSubtargetInfo* STI; 41 bool isThumbMode; // Currently emitting Thumb code. 42 public: 43 ARMAsmBackend(const Target &T, const StringRef TT) 44 : MCAsmBackend(), STI(ARM_MC::createARMMCSubtargetInfo(TT, "", "")), 45 isThumbMode(TT.startswith("thumb")) {} 46 47 ~ARMAsmBackend() { 48 delete STI; 49 } 50 51 unsigned getNumFixupKinds() const { return ARM::NumTargetFixupKinds; } 52 53 bool hasNOP() const { 54 return (STI->getFeatureBits() & ARM::HasV6T2Ops) != 0; 55 } 56 57 const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const { 58 const static MCFixupKindInfo Infos[ARM::NumTargetFixupKinds] = { 59 // This table *must* be in the order that the fixup_* kinds are defined in 60 // ARMFixupKinds.h. 61 // 62 // Name Offset (bits) Size (bits) Flags 63 { "fixup_arm_ldst_pcrel_12", 1, 24, MCFixupKindInfo::FKF_IsPCRel }, 64 { "fixup_t2_ldst_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel | 65 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, 66 { "fixup_arm_pcrel_10", 1, 24, MCFixupKindInfo::FKF_IsPCRel }, 67 { "fixup_t2_pcrel_10", 0, 32, MCFixupKindInfo::FKF_IsPCRel | 68 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, 69 { "fixup_thumb_adr_pcrel_10",0, 8, MCFixupKindInfo::FKF_IsPCRel | 70 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, 71 { "fixup_arm_adr_pcrel_12", 1, 24, MCFixupKindInfo::FKF_IsPCRel }, 72 { "fixup_t2_adr_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel | 73 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, 74 { "fixup_arm_condbranch", 0, 24, MCFixupKindInfo::FKF_IsPCRel }, 75 { "fixup_arm_uncondbranch", 0, 24, MCFixupKindInfo::FKF_IsPCRel }, 76 { "fixup_t2_condbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, 77 { "fixup_t2_uncondbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, 78 { "fixup_arm_thumb_br", 0, 16, MCFixupKindInfo::FKF_IsPCRel }, 79 { "fixup_arm_thumb_bl", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, 80 { "fixup_arm_thumb_blx", 0, 32, MCFixupKindInfo::FKF_IsPCRel }, 81 { "fixup_arm_thumb_cb", 0, 16, MCFixupKindInfo::FKF_IsPCRel }, 82 { "fixup_arm_thumb_cp", 0, 8, MCFixupKindInfo::FKF_IsPCRel }, 83 { "fixup_arm_thumb_bcc", 0, 8, MCFixupKindInfo::FKF_IsPCRel }, 84 // movw / movt: 16-bits immediate but scattered into two chunks 0 - 12, 16 - 19. 85 { "fixup_arm_movt_hi16", 0, 20, 0 }, 86 { "fixup_arm_movw_lo16", 0, 20, 0 }, 87 { "fixup_t2_movt_hi16", 0, 20, 0 }, 88 { "fixup_t2_movw_lo16", 0, 20, 0 }, 89 { "fixup_arm_movt_hi16_pcrel", 0, 20, MCFixupKindInfo::FKF_IsPCRel }, 90 { "fixup_arm_movw_lo16_pcrel", 0, 20, MCFixupKindInfo::FKF_IsPCRel }, 91 { "fixup_t2_movt_hi16_pcrel", 0, 20, MCFixupKindInfo::FKF_IsPCRel }, 92 { "fixup_t2_movw_lo16_pcrel", 0, 20, MCFixupKindInfo::FKF_IsPCRel }, 93 }; 94 95 if (Kind < FirstTargetFixupKind) 96 return MCAsmBackend::getFixupKindInfo(Kind); 97 98 assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() && 99 "Invalid kind!"); 100 return Infos[Kind - FirstTargetFixupKind]; 101 } 102 103 bool MayNeedRelaxation(const MCInst &Inst) const; 104 105 void RelaxInstruction(const MCInst &Inst, MCInst &Res) const; 106 107 bool WriteNopData(uint64_t Count, MCObjectWriter *OW) const; 108 109 void HandleAssemblerFlag(MCAssemblerFlag Flag) { 110 switch (Flag) { 111 default: break; 112 case MCAF_Code16: 113 setIsThumb(true); 114 break; 115 case MCAF_Code32: 116 setIsThumb(false); 117 break; 118 } 119 } 120 121 unsigned getPointerSize() const { return 4; } 122 bool isThumb() const { return isThumbMode; } 123 void setIsThumb(bool it) { isThumbMode = it; } 124 }; 125 } // end anonymous namespace 126 127 bool ARMAsmBackend::MayNeedRelaxation(const MCInst &Inst) const { 128 // FIXME: Thumb targets, different move constant targets.. 129 return false; 130 } 131 132 void ARMAsmBackend::RelaxInstruction(const MCInst &Inst, MCInst &Res) const { 133 assert(0 && "ARMAsmBackend::RelaxInstruction() unimplemented"); 134 return; 135 } 136 137 bool ARMAsmBackend::WriteNopData(uint64_t Count, MCObjectWriter *OW) const { 138 const uint16_t Thumb1_16bitNopEncoding = 0x46c0; // using MOV r8,r8 139 const uint16_t Thumb2_16bitNopEncoding = 0xbf00; // NOP 140 const uint32_t ARMv4_NopEncoding = 0xe1a0000; // using MOV r0,r0 141 const uint32_t ARMv6T2_NopEncoding = 0xe3207800; // NOP 142 if (isThumb()) { 143 const uint16_t nopEncoding = hasNOP() ? Thumb2_16bitNopEncoding 144 : Thumb1_16bitNopEncoding; 145 uint64_t NumNops = Count / 2; 146 for (uint64_t i = 0; i != NumNops; ++i) 147 OW->Write16(nopEncoding); 148 if (Count & 1) 149 OW->Write8(0); 150 return true; 151 } 152 // ARM mode 153 const uint32_t nopEncoding = hasNOP() ? ARMv6T2_NopEncoding 154 : ARMv4_NopEncoding; 155 uint64_t NumNops = Count / 4; 156 for (uint64_t i = 0; i != NumNops; ++i) 157 OW->Write32(nopEncoding); 158 // FIXME: should this function return false when unable to write exactly 159 // 'Count' bytes with NOP encodings? 160 switch (Count % 4) { 161 default: break; // No leftover bytes to write 162 case 1: OW->Write8(0); break; 163 case 2: OW->Write16(0); break; 164 case 3: OW->Write16(0); OW->Write8(0xa0); break; 165 } 166 167 return true; 168 } 169 170 static unsigned adjustFixupValue(unsigned Kind, uint64_t Value) { 171 switch (Kind) { 172 default: 173 llvm_unreachable("Unknown fixup kind!"); 174 case FK_Data_1: 175 case FK_Data_2: 176 case FK_Data_4: 177 return Value; 178 case ARM::fixup_arm_movt_hi16: 179 Value >>= 16; 180 // Fallthrough 181 case ARM::fixup_arm_movw_lo16: 182 case ARM::fixup_arm_movt_hi16_pcrel: 183 case ARM::fixup_arm_movw_lo16_pcrel: { 184 unsigned Hi4 = (Value & 0xF000) >> 12; 185 unsigned Lo12 = Value & 0x0FFF; 186 // inst{19-16} = Hi4; 187 // inst{11-0} = Lo12; 188 Value = (Hi4 << 16) | (Lo12); 189 return Value; 190 } 191 case ARM::fixup_t2_movt_hi16: 192 Value >>= 16; 193 // Fallthrough 194 case ARM::fixup_t2_movw_lo16: 195 case ARM::fixup_t2_movt_hi16_pcrel: //FIXME: Shouldn't this be shifted like 196 // the other hi16 fixup? 197 case ARM::fixup_t2_movw_lo16_pcrel: { 198 unsigned Hi4 = (Value & 0xF000) >> 12; 199 unsigned i = (Value & 0x800) >> 11; 200 unsigned Mid3 = (Value & 0x700) >> 8; 201 unsigned Lo8 = Value & 0x0FF; 202 // inst{19-16} = Hi4; 203 // inst{26} = i; 204 // inst{14-12} = Mid3; 205 // inst{7-0} = Lo8; 206 Value = (Hi4 << 16) | (i << 26) | (Mid3 << 12) | (Lo8); 207 uint64_t swapped = (Value & 0xFFFF0000) >> 16; 208 swapped |= (Value & 0x0000FFFF) << 16; 209 return swapped; 210 } 211 case ARM::fixup_arm_ldst_pcrel_12: 212 // ARM PC-relative values are offset by 8. 213 Value -= 4; 214 // FALLTHROUGH 215 case ARM::fixup_t2_ldst_pcrel_12: { 216 // Offset by 4, adjusted by two due to the half-word ordering of thumb. 217 Value -= 4; 218 bool isAdd = true; 219 if ((int64_t)Value < 0) { 220 Value = -Value; 221 isAdd = false; 222 } 223 assert ((Value < 4096) && "Out of range pc-relative fixup value!"); 224 Value |= isAdd << 23; 225 226 // Same addressing mode as fixup_arm_pcrel_10, 227 // but with 16-bit halfwords swapped. 228 if (Kind == ARM::fixup_t2_ldst_pcrel_12) { 229 uint64_t swapped = (Value & 0xFFFF0000) >> 16; 230 swapped |= (Value & 0x0000FFFF) << 16; 231 return swapped; 232 } 233 234 return Value; 235 } 236 case ARM::fixup_thumb_adr_pcrel_10: 237 return ((Value - 4) >> 2) & 0xff; 238 case ARM::fixup_arm_adr_pcrel_12: { 239 // ARM PC-relative values are offset by 8. 240 Value -= 8; 241 unsigned opc = 4; // bits {24-21}. Default to add: 0b0100 242 if ((int64_t)Value < 0) { 243 Value = -Value; 244 opc = 2; // 0b0010 245 } 246 assert(ARM_AM::getSOImmVal(Value) != -1 && 247 "Out of range pc-relative fixup value!"); 248 // Encode the immediate and shift the opcode into place. 249 return ARM_AM::getSOImmVal(Value) | (opc << 21); 250 } 251 252 case ARM::fixup_t2_adr_pcrel_12: { 253 Value -= 4; 254 unsigned opc = 0; 255 if ((int64_t)Value < 0) { 256 Value = -Value; 257 opc = 5; 258 } 259 260 uint32_t out = (opc << 21); 261 out |= (Value & 0x800) << 15; 262 out |= (Value & 0x700) << 4; 263 out |= (Value & 0x0FF); 264 265 uint64_t swapped = (out & 0xFFFF0000) >> 16; 266 swapped |= (out & 0x0000FFFF) << 16; 267 return swapped; 268 } 269 270 case ARM::fixup_arm_condbranch: 271 case ARM::fixup_arm_uncondbranch: 272 // These values don't encode the low two bits since they're always zero. 273 // Offset by 8 just as above. 274 return 0xffffff & ((Value - 8) >> 2); 275 case ARM::fixup_t2_uncondbranch: { 276 Value = Value - 4; 277 Value >>= 1; // Low bit is not encoded. 278 279 uint32_t out = 0; 280 bool I = Value & 0x800000; 281 bool J1 = Value & 0x400000; 282 bool J2 = Value & 0x200000; 283 J1 ^= I; 284 J2 ^= I; 285 286 out |= I << 26; // S bit 287 out |= !J1 << 13; // J1 bit 288 out |= !J2 << 11; // J2 bit 289 out |= (Value & 0x1FF800) << 5; // imm6 field 290 out |= (Value & 0x0007FF); // imm11 field 291 292 uint64_t swapped = (out & 0xFFFF0000) >> 16; 293 swapped |= (out & 0x0000FFFF) << 16; 294 return swapped; 295 } 296 case ARM::fixup_t2_condbranch: { 297 Value = Value - 4; 298 Value >>= 1; // Low bit is not encoded. 299 300 uint64_t out = 0; 301 out |= (Value & 0x80000) << 7; // S bit 302 out |= (Value & 0x40000) >> 7; // J2 bit 303 out |= (Value & 0x20000) >> 4; // J1 bit 304 out |= (Value & 0x1F800) << 5; // imm6 field 305 out |= (Value & 0x007FF); // imm11 field 306 307 uint32_t swapped = (out & 0xFFFF0000) >> 16; 308 swapped |= (out & 0x0000FFFF) << 16; 309 return swapped; 310 } 311 case ARM::fixup_arm_thumb_bl: { 312 // The value doesn't encode the low bit (always zero) and is offset by 313 // four. The value is encoded into disjoint bit positions in the destination 314 // opcode. x = unchanged, I = immediate value bit, S = sign extension bit 315 // 316 // BL: xxxxxSIIIIIIIIII xxxxxIIIIIIIIIII 317 // 318 // Note that the halfwords are stored high first, low second; so we need 319 // to transpose the fixup value here to map properly. 320 unsigned isNeg = (int64_t(Value - 4) < 0) ? 1 : 0; 321 uint32_t Binary = 0; 322 Value = 0x3fffff & ((Value - 4) >> 1); 323 Binary = (Value & 0x7ff) << 16; // Low imm11 value. 324 Binary |= (Value & 0x1ffc00) >> 11; // High imm10 value. 325 Binary |= isNeg << 10; // Sign bit. 326 return Binary; 327 } 328 case ARM::fixup_arm_thumb_blx: { 329 // The value doesn't encode the low two bits (always zero) and is offset by 330 // four (see fixup_arm_thumb_cp). The value is encoded into disjoint bit 331 // positions in the destination opcode. x = unchanged, I = immediate value 332 // bit, S = sign extension bit, 0 = zero. 333 // 334 // BLX: xxxxxSIIIIIIIIII xxxxxIIIIIIIIII0 335 // 336 // Note that the halfwords are stored high first, low second; so we need 337 // to transpose the fixup value here to map properly. 338 unsigned isNeg = (int64_t(Value-4) < 0) ? 1 : 0; 339 uint32_t Binary = 0; 340 Value = 0xfffff & ((Value - 2) >> 2); 341 Binary = (Value & 0x3ff) << 17; // Low imm10L value. 342 Binary |= (Value & 0xffc00) >> 10; // High imm10H value. 343 Binary |= isNeg << 10; // Sign bit. 344 return Binary; 345 } 346 case ARM::fixup_arm_thumb_cp: 347 // Offset by 4, and don't encode the low two bits. Two bytes of that 348 // 'off by 4' is implicitly handled by the half-word ordering of the 349 // Thumb encoding, so we only need to adjust by 2 here. 350 return ((Value - 2) >> 2) & 0xff; 351 case ARM::fixup_arm_thumb_cb: { 352 // Offset by 4 and don't encode the lower bit, which is always 0. 353 uint32_t Binary = (Value - 4) >> 1; 354 return ((Binary & 0x20) << 4) | ((Binary & 0x1f) << 3); 355 } 356 case ARM::fixup_arm_thumb_br: 357 // Offset by 4 and don't encode the lower bit, which is always 0. 358 return ((Value - 4) >> 1) & 0x7ff; 359 case ARM::fixup_arm_thumb_bcc: 360 // Offset by 4 and don't encode the lower bit, which is always 0. 361 return ((Value - 4) >> 1) & 0xff; 362 case ARM::fixup_arm_pcrel_10: 363 Value = Value - 4; // ARM fixups offset by an additional word and don't 364 // need to adjust for the half-word ordering. 365 // Fall through. 366 case ARM::fixup_t2_pcrel_10: { 367 // Offset by 4, adjusted by two due to the half-word ordering of thumb. 368 Value = Value - 4; 369 bool isAdd = true; 370 if ((int64_t)Value < 0) { 371 Value = -Value; 372 isAdd = false; 373 } 374 // These values don't encode the low two bits since they're always zero. 375 Value >>= 2; 376 assert ((Value < 256) && "Out of range pc-relative fixup value!"); 377 Value |= isAdd << 23; 378 379 // Same addressing mode as fixup_arm_pcrel_10, 380 // but with 16-bit halfwords swapped. 381 if (Kind == ARM::fixup_t2_pcrel_10) { 382 uint32_t swapped = (Value & 0xFFFF0000) >> 16; 383 swapped |= (Value & 0x0000FFFF) << 16; 384 return swapped; 385 } 386 387 return Value; 388 } 389 } 390 } 391 392 namespace { 393 394 // FIXME: This should be in a separate file. 395 // ELF is an ELF of course... 396 class ELFARMAsmBackend : public ARMAsmBackend { 397 public: 398 Triple::OSType OSType; 399 ELFARMAsmBackend(const Target &T, const StringRef TT, 400 Triple::OSType _OSType) 401 : ARMAsmBackend(T, TT), OSType(_OSType) { } 402 403 void ApplyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize, 404 uint64_t Value) const; 405 406 MCObjectWriter *createObjectWriter(raw_ostream &OS) const { 407 return createELFObjectWriter(new ARMELFObjectWriter(OSType), OS, 408 /*IsLittleEndian*/ true); 409 } 410 }; 411 412 // FIXME: Raise this to share code between Darwin and ELF. 413 void ELFARMAsmBackend::ApplyFixup(const MCFixup &Fixup, char *Data, 414 unsigned DataSize, uint64_t Value) const { 415 unsigned NumBytes = 4; // FIXME: 2 for Thumb 416 Value = adjustFixupValue(Fixup.getKind(), Value); 417 if (!Value) return; // Doesn't change encoding. 418 419 unsigned Offset = Fixup.getOffset(); 420 421 // For each byte of the fragment that the fixup touches, mask in the bits from 422 // the fixup value. The Value has been "split up" into the appropriate 423 // bitfields above. 424 for (unsigned i = 0; i != NumBytes; ++i) 425 Data[Offset + i] |= uint8_t((Value >> (i * 8)) & 0xff); 426 } 427 428 // FIXME: This should be in a separate file. 429 class DarwinARMAsmBackend : public ARMAsmBackend { 430 public: 431 const object::mach::CPUSubtypeARM Subtype; 432 DarwinARMAsmBackend(const Target &T, const StringRef TT, 433 object::mach::CPUSubtypeARM st) 434 : ARMAsmBackend(T, TT), Subtype(st) { } 435 436 MCObjectWriter *createObjectWriter(raw_ostream &OS) const { 437 return createARMMachObjectWriter(OS, /*Is64Bit=*/false, 438 object::mach::CTM_ARM, 439 Subtype); 440 } 441 442 void ApplyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize, 443 uint64_t Value) const; 444 445 virtual bool doesSectionRequireSymbols(const MCSection &Section) const { 446 return false; 447 } 448 }; 449 450 /// getFixupKindNumBytes - The number of bytes the fixup may change. 451 static unsigned getFixupKindNumBytes(unsigned Kind) { 452 switch (Kind) { 453 default: 454 llvm_unreachable("Unknown fixup kind!"); 455 456 case FK_Data_1: 457 case ARM::fixup_arm_thumb_bcc: 458 case ARM::fixup_arm_thumb_cp: 459 case ARM::fixup_thumb_adr_pcrel_10: 460 return 1; 461 462 case FK_Data_2: 463 case ARM::fixup_arm_thumb_br: 464 case ARM::fixup_arm_thumb_cb: 465 return 2; 466 467 case ARM::fixup_arm_ldst_pcrel_12: 468 case ARM::fixup_arm_pcrel_10: 469 case ARM::fixup_arm_adr_pcrel_12: 470 case ARM::fixup_arm_condbranch: 471 case ARM::fixup_arm_uncondbranch: 472 return 3; 473 474 case FK_Data_4: 475 case ARM::fixup_t2_ldst_pcrel_12: 476 case ARM::fixup_t2_condbranch: 477 case ARM::fixup_t2_uncondbranch: 478 case ARM::fixup_t2_pcrel_10: 479 case ARM::fixup_t2_adr_pcrel_12: 480 case ARM::fixup_arm_thumb_bl: 481 case ARM::fixup_arm_thumb_blx: 482 case ARM::fixup_arm_movt_hi16: 483 case ARM::fixup_arm_movw_lo16: 484 case ARM::fixup_arm_movt_hi16_pcrel: 485 case ARM::fixup_arm_movw_lo16_pcrel: 486 case ARM::fixup_t2_movt_hi16: 487 case ARM::fixup_t2_movw_lo16: 488 case ARM::fixup_t2_movt_hi16_pcrel: 489 case ARM::fixup_t2_movw_lo16_pcrel: 490 return 4; 491 } 492 } 493 494 void DarwinARMAsmBackend::ApplyFixup(const MCFixup &Fixup, char *Data, 495 unsigned DataSize, uint64_t Value) const { 496 unsigned NumBytes = getFixupKindNumBytes(Fixup.getKind()); 497 Value = adjustFixupValue(Fixup.getKind(), Value); 498 if (!Value) return; // Doesn't change encoding. 499 500 unsigned Offset = Fixup.getOffset(); 501 assert(Offset + NumBytes <= DataSize && "Invalid fixup offset!"); 502 503 // For each byte of the fragment that the fixup touches, mask in the 504 // bits from the fixup value. 505 for (unsigned i = 0; i != NumBytes; ++i) 506 Data[Offset + i] |= uint8_t((Value >> (i * 8)) & 0xff); 507 } 508 509 } // end anonymous namespace 510 511 MCAsmBackend *llvm::createARMAsmBackend(const Target &T, StringRef TT) { 512 Triple TheTriple(TT); 513 514 if (TheTriple.isOSDarwin()) { 515 if (TheTriple.getArchName() == "armv4t" || 516 TheTriple.getArchName() == "thumbv4t") 517 return new DarwinARMAsmBackend(T, TT, object::mach::CSARM_V4T); 518 else if (TheTriple.getArchName() == "armv5e" || 519 TheTriple.getArchName() == "thumbv5e") 520 return new DarwinARMAsmBackend(T, TT, object::mach::CSARM_V5TEJ); 521 else if (TheTriple.getArchName() == "armv6" || 522 TheTriple.getArchName() == "thumbv6") 523 return new DarwinARMAsmBackend(T, TT, object::mach::CSARM_V6); 524 return new DarwinARMAsmBackend(T, TT, object::mach::CSARM_V7); 525 } 526 527 if (TheTriple.isOSWindows()) 528 assert(0 && "Windows not supported on ARM"); 529 530 return new ELFARMAsmBackend(T, TT, Triple(TT).getOS()); 531 } 532
