1 ; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mcpu=cortex-a9 | FileCheck %s 2 ; Avoid some 's' 16-bit instruction which partially update CPSR (and add false 3 ; dependency) when it isn't dependent on last CPSR defining instruction. 4 ; rdar://8928208 5 6 define i32 @t(i32 %a, i32 %b, i32 %c, i32 %d) nounwind readnone { 7 entry: 8 ; CHECK: t: 9 ; CHECK: muls [[REG:(r[0-9]+)]], r2, r3 10 ; CHECK-NEXT: mul [[REG2:(r[0-9]+)]], r0, r1 11 ; CHECK-NEXT: muls r0, [[REG2]], [[REG]] 12 %0 = mul nsw i32 %a, %b 13 %1 = mul nsw i32 %c, %d 14 %2 = mul nsw i32 %0, %1 15 ret i32 %2 16 } 17
