1 ; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s 2 3 define i32 @f1(float %a) { 4 ;CHECK: f1: 5 ;CHECK: vcmpe.f32 6 ;CHECK: movmi 7 entry: 8 %tmp = fcmp olt float %a, 1.000000e+00 ; <i1> [#uses=1] 9 %tmp1 = zext i1 %tmp to i32 ; <i32> [#uses=1] 10 ret i32 %tmp1 11 } 12 13 define i32 @f2(float %a) { 14 ;CHECK: f2: 15 ;CHECK: vcmpe.f32 16 ;CHECK: moveq 17 entry: 18 %tmp = fcmp oeq float %a, 1.000000e+00 ; <i1> [#uses=1] 19 %tmp2 = zext i1 %tmp to i32 ; <i32> [#uses=1] 20 ret i32 %tmp2 21 } 22 23 define i32 @f3(float %a) { 24 ;CHECK: f3: 25 ;CHECK: vcmpe.f32 26 ;CHECK: movgt 27 entry: 28 %tmp = fcmp ogt float %a, 1.000000e+00 ; <i1> [#uses=1] 29 %tmp3 = zext i1 %tmp to i32 ; <i32> [#uses=1] 30 ret i32 %tmp3 31 } 32 33 define i32 @f4(float %a) { 34 ;CHECK: f4: 35 ;CHECK: vcmpe.f32 36 ;CHECK: movge 37 entry: 38 %tmp = fcmp oge float %a, 1.000000e+00 ; <i1> [#uses=1] 39 %tmp4 = zext i1 %tmp to i32 ; <i32> [#uses=1] 40 ret i32 %tmp4 41 } 42 43 define i32 @f5(float %a) { 44 ;CHECK: f5: 45 ;CHECK: vcmpe.f32 46 ;CHECK: movls 47 entry: 48 %tmp = fcmp ole float %a, 1.000000e+00 ; <i1> [#uses=1] 49 %tmp5 = zext i1 %tmp to i32 ; <i32> [#uses=1] 50 ret i32 %tmp5 51 } 52 53 define i32 @f6(float %a) { 54 ;CHECK: f6: 55 ;CHECK: vcmpe.f32 56 ;CHECK: movne 57 entry: 58 %tmp = fcmp une float %a, 1.000000e+00 ; <i1> [#uses=1] 59 %tmp6 = zext i1 %tmp to i32 ; <i32> [#uses=1] 60 ret i32 %tmp6 61 } 62 63 define i32 @g1(double %a) { 64 ;CHECK: g1: 65 ;CHECK: vcmpe.f64 66 ;CHECK: movmi 67 entry: 68 %tmp = fcmp olt double %a, 1.000000e+00 ; <i1> [#uses=1] 69 %tmp7 = zext i1 %tmp to i32 ; <i32> [#uses=1] 70 ret i32 %tmp7 71 } 72
