__gmon_start__ libc.so.6 strcpy getgid stdout ungetc strerror fdopen memmove ftello64 getenv __rawmemchr __strtol_internal qsort fgets memcpy perror getuid malloc optarg vsnprintf _obstack_newchunk __strtoul_internal fflush strncasecmp abort chmod __lxstat strrchr _obstack_begin calloc strcat dcgettext fseek optind stdin fnmatch umask ferror strstr strncmp strncpy unlink getrusage strcasecmp realloc __strdup _IO_getc fread sbrk memset ftell time getopt_long_only strcmp getcwd fgetc asprintf fclose setlocale stderr obstack_free fputc fwrite __xstat __errno_location __fxstat bindtextdomain fopen _IO_putc fileno _IO_stdin_used _exit __libc_start_main strchr fputs fcntl fseeko64 vfprintf fopen64 __environ GLIBC_2.2.3 GLIBC_2.1 GLIBC_2.0
.symver $._ABCDEFGHIJKLMNOPQRSTUVWXYZabcdefghijklmnopqrstuvwxyz0123456789 app_pop C W W W W Z V r 6 6 M r o o : : : : : ../../../toolchain/android-toolchain/binutils-2.17/gas/app.c end of file in string; '%c' inserted end of file not at end of a line; newline inserted Case value %ld unexpected at line %d of file "%s" end of file in multiline comment end of file after a one-character quote; \0 inserted end of file in escape character end of file in comment; newline inserted end of file in comment .appfile .appline GNU assembler version %s (%s) using BFD version %s %s: total time in assembly: %ld.%06ld Usage: %s [option...] [asmfile...] Options: -a[sub-option...] turn on listings Sub-options [default hls]: c omit false conditionals d omit debugging directives h include high-level source l include assembly m include macro expansions n omit forms processing s include symbols =FILE list to FILE (must be last sub-option) --alternate initially turn on alternate macro syntax -D produce assembler debugging messages --defsym SYM=VAL define symbol SYM to given value --execstack require executable stack for this object --noexecstack don't require executable stack for this object -f skip whitespace and comment preprocessing -g --gen-debug generate debugging information --gstabs generate STABS debugging information --gstabs+ generate STABS debug info with GNU extensions --gdwarf-2 generate DWARF2 debugging information --hash-size= set the hash table size close to --help show this message and exit --target-help show target specific options -I DIR add DIR to search list for .include directives -J don't warn about signed overflow -K warn when differences altered for long displacements -L,--keep-locals keep local symbols (e.g. starting with `L') -M,--mri assemble in MRI compatibility mode --MD FILE write dependency information in FILE (default none) -nocpp ignored -o OBJFILE name the object-file output OBJFILE (default a.out) -R fold data section into text section --reduce-memory-overheads prefer smaller memory use at the cost of longer assembly times --statistics print various measured statistics from execution --strip-local-absolute strip local absolute symbols --traditional-format Use same format as native assembler when possible --version print assembler version number and exit -W --no-warn suppress warnings --warn don't suppress warnings --fatal-warnings treat warnings as errors --itbl INSTTBL extend instruction set to include instructions matching the specifications defined in file INSTTBL -w ignored -X ignored -Z generate object file even after errors --listing-lhs-width set the width in words of the output data column of the listing --listing-lhs-width2 set the width in words of the continuation lines of the output data column; ignored if smaller than the width of the first line --listing-rhs-width set the max width in characters of the lines from the source file --listing-cont-lines set the maximum number of continuation lines used for the output data column of the listing @FILE read options from FILE expected address expression .fill size clamped to %d size negative; .fill ignored repeat < 0; .fill ignored missing string .error .warning %s argument must be a string %s/%s file not found: %s unknown pseudo-op: `%s' label "%d$" redefined #NO_APP missing .func pseudo-op table this_GCC_requires_the_GNU_assembler this_gcc_requires_the_gnu_assembler bad or irreducible absolute expression error constructing %s pseudo-op table: %s .abort detected. Abandoning ship. ignoring fill value in absolute section junk at end of line, first unrecognized character is `%c' junk at end of line, first unrecognized character valued 0x%x alignment too large: %u assumed ../../../toolchain/android-toolchain/binutils-2.17/gas/read.c size (%ld) out of range, ignored symbol `%s' is already defined size of "%s" is already %ld; not changing to %ld line numbers must be positive; line number %d rejected unrecognized .linkonce type `%s' .linkonce is not supported for this object file format attempt to redefine pseudo-op `%s' ignored only constant offsets supported in absolute section MRI mode not supported for this target .end%c encountered without preceeding %s unknown floating type type '%c' floating point constant too large %s: would close weakref loop: %s attempt to set value of section symbol `%s' can't be equated to common symbol '%s' attempt to store value in absolute section zero assumed for missing expression register value used as expression value 0x%lx truncated to 0x%lx unsupported variable size or fill value .space repeat count is zero, ignored .space repeat count is negative, ignored space allocation too complex in absolute section space allocation too complex in common section unterminated string; newline inserted strings must be placed into a section symbol "%s" undefined; zero assumed some symbol undefined; zero assumed this string may not contain '\0' .error directive invoked in source file .warning directive invoked in source file .incbin count zero, ignoring `%s' seek to end of .incbin file failed `%s' skip (%ld) or count (%ld) invalid for file size (%ld) could not skip to %ld in file `%s' truncated file `%s', %ld of %ld bytes read .endfunc missing for previous .func ,: > ; ; 2: F 8: F >: E: M: } ; U: k !s ^: c: h: d m: r: f w: |: x # : : d : : f : : x : : : : : : : w ; w ; ; o j_ b ,p ; p ; > ; ; ; ' ; ; ' ; ,p ; 7q ; y f * ; ; ; ; o ; p ; ; p < < ; | < | < < Fq f ` < %< f ,< 2< 7< ?< ' C< d 1 n s W? F I< y ? ' ? ' S2 Fq < Fq P< X< ]< b< ' R s 9? g< -; s_align s_linkonce 6 6 6 6 s_weakref 3 o B L V e o emit_leb128_expr sb_build ../../../toolchain/android-toolchain/binutils-2.17/gas/sb.c get_stab_string_offset s_stab_generic .stab%c: missing comma .stabstr .stab comma missing in .xstabs %sF%d ",%d,0,0,%s %sL%d %d,0,%d,%s-%s %d,0,%d,%s "void:t1=1",128,0,0,0 "%s:F1",%d,0,%d,%s %sendfunc%d "",%d,0,0,%s-%s .stab%c: description field '%x' too big, try a different debug format subseg_set_rest section_symbol ../../../toolchain/android-toolchain/binutils-2.17/gas/subsegs.c can't allocate ELF private section data: %s frag chains: %p %-10s %10d frags symbol_append symbol_clear_list_pointers S_IS_EXTERNAL local_symbol_convert S_SET_SEGMENT symbol_new symbol_remove symbol_insert symbol_next verify_symbol_chain resolve_symbol_value 6 i6 k6 6 6 6 6 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 6 9 9 9 9 9 9 9 9 9 : : : .: g: y: @: O: : S_IS_LOCAL symbol_previous O O P 9P O P P P Q O /Q BQ UQ hQ {Q Q O Q Q Q /R VR iR |R R R R R R ../../../toolchain/android-toolchain/binutils-2.17/gas/symbols.c inserting "%s" into symbol table failed: %s undefined symbol `%s' in operation invalid sections for operation on `%s' and `%s' invalid section for operation on `%s' undefined symbol `%s' in operation setting `%s' invalid sections for operation on `%s' and `%s' setting `%s' invalid section for operation on `%s' setting `%s' "%d" (instance number %d of a %s label) symbol definition loop encountered at `%s' division by zero when setting `%s' can't resolve value for symbol `%s' attempt to get value of unresolved symbol `%s' symbol `%s' is already defined as "%s"/%s%ld section symbols are already global Accessing function `%s' as thread-local object Accessing `%s' as thread-local object %lu mini local symbols created, %lu converted bfd_make_empty_symbol dollar %s %*s< > %*s< expr %lx illegal absent constant %lx symbol %*s< %*s%lx register #%d uminus -< bit_not multiply divide modulus lshift rshift bit_ior bit_xor bit_and logical_and logical_or add %*s< subtract %*s< {unknown opcode %d} (unnamed) sym %lx %s frag %lx resolved local written resolving used-in-reloc used extern weak debug weakrefr weakrefd mini local symbol table fix_new_internal t[ [ b\ \\ K\ [ t[ ?\ t[ t[ t[ t[ t[ t[ t[ t[ t[ t[ t[ \ [ chain_frchains_together_1 cvt_frag_to_fill size_seg ^ _ _ _ _ _ ^ _ _ (` s` ` adjust_reloc_syms write_contents set_symtab q jr r r r q q q q r r xr 6s ns s s s Dt 6s qt t s s s number_to_chars_bigendian number_to_chars_littleendian field fx_size too small to hold %d ../../../toolchain/android-toolchain/binutils-2.17/gas/write.c attempt to .org/.space backwards? (%ld) %s:%u: bad return from bfd_install_relocation: %x %d error%s, %d warning%s, generating bad object file %d error%s, %d warning%s, no object file generated %s: global symbols not supported in common sections local label `%s' is not defined Local symbol `%s' can't be equated to common symbol `%s' alignment padding (%lu bytes) not a multiple of %ld attempt to move .org backwards .space specifies non-absolute value .space or .fill with negative value, ignored Infinite loop encountered whilst attempting to compute the addresses of symbols in section %s can't resolve `%s' {%s section} - `%s' {%s section} value of %s too large for field of %d bytes at %s size=%d frag=%lx where=%ld offset=%lx addnumber=%lx .gnu.linkonce relocation out of range FATAL: Can't write %s cannot write to output file fixups: %d fix %lx %s:%d pcrel pcrel_adjust=%d im_disp tcbit done %s (%d) +< -< mcpu= march= mfpu= mfloat-abi= meabi= marm1 use -mcpu=arm1 marm2 use -mcpu=arm2 marm250 use -mcpu=arm250 marm3 use -mcpu=arm3 marm6 use -mcpu=arm6 marm600 use -mcpu=arm600 marm610 use -mcpu=arm610 marm620 use -mcpu=arm620 marm7 use -mcpu=arm7 marm70 use -mcpu=arm70 marm700 use -mcpu=arm700 marm700i use -mcpu=arm700i marm710 use -mcpu=arm710 marm710c use -mcpu=arm710c marm720 use -mcpu=arm720 marm7d use -mcpu=arm7d marm7di use -mcpu=arm7di marm7m use -mcpu=arm7m marm7dm use -mcpu=arm7dm marm7dmi use -mcpu=arm7dmi marm7100 use -mcpu=arm7100 marm7500 use -mcpu=arm7500 marm7500fe use -mcpu=arm7500fe marm7t use -mcpu=arm7tdmi marm7tdmi marm710t use -mcpu=arm710t marm720t use -mcpu=arm720t marm740t use -mcpu=arm740t marm8 use -mcpu=arm8 marm810 use -mcpu=arm810 marm9 use -mcpu=arm9 marm9tdmi use -mcpu=arm9tdmi marm920 use -mcpu=arm920 marm940 use -mcpu=arm940 mstrongarm use -mcpu=strongarm mstrongarm110 use -mcpu=strongarm110 mstrongarm1100 use -mcpu=strongarm1100 mstrongarm1110 use -mcpu=strongarm1110 mxscale use -mcpu=xscale miwmmxt use -mcpu=iwmmxt mall use -mcpu=all use -march=armv2 marmv2 use -march=armv2a marmv2a use -march=armv3 marmv3 use -march=armv3m marmv3m use -march=armv4 marmv4 use -march=armv4t marmv4t use -march=armv5 marmv5 use -march=armv5t marmv5t use -march=armv5te marmv5e mfpe-old use -mfpu=fpe mfpa10 use -mfpu=fpa10 mfpa11 use -mfpu=fpa11 mno-fpu generate PIC code mthumb assemble Thumb code mthumb-interwork mapcs-32 mapcs-26 mapcs-float mapcs-reentrant re-entrant code matpcs code is ATPCS conformant mbig-endian assemble for big-endian mlittle-endian assemble for little-endian mapcs-frame use frame pointer mapcs-stack-check use stack size checking EB m:k unreq force_thumb thumb_func thumb_set even ltorg pool syntax rel31 fnstart fnend cantunwind personality personalityindex handlerdata movsp pad setfp unwind_raw cpu arch eabi_attribute extend ldouble packed ARM register expected FPA register expected VFP system register expected iWMMXt data register expected 1.0 2.0 3.0 4.0 5.0 0.5 10.0 softfpa fpe2 fpe3 softvfp softvfp+vfp vfp9 vfp10 vfp10-r0 vfpxd arm1020t arm1020e arm1136jfs arm1136jf-s maverick armv1 armv2s armv4xm armv4txm armv5txm armv5texp armv5tej armv6 armv6j armv6k armv6z armv6zk armv6t2 armv6kt2 armv6zt2 armv6zkt2 armv7 armv7a armv7r armv7m arm60 arm7tdmi-s strongarm1 ARM920T arm920t arm922t arm940t arm9e-r0 arm9e arm926ej ARM926EJ-S arm926ejs arm926ej-s arm946e-r0 arm946e ARM946E-S arm946e-s arm966e-r0 arm966e ARM966E-S arm966e-s arm968e-s arm10t arm10tdmi arm10e arm1020 ARM1020E arm1022e arm1026ejs ARM1026EJ-S arm1026ej-s arm1136js ARM1136J-S arm1136j-s ARM1136JF-S mpcore mpcorenovfp arm1156t2-s arm1156t2f-s arm1176jz-s arm1176jzf-s cortex-a8 cortex-r4 cortex-m3 i80200 ep9312 hard softfp soft gotoff target1 target2 sbrel SBREL tlsgd tlsldm tlsldo TLSLDO gottpoff sy un unst a2 a3 a4 v8 A1 A2 A3 A4 V1 V2 V3 V4 V5 V6 V7 V8 wr WR FP p0 p1 p3 p4 p5 p6 p7 p8 p11 p12 p13 p14 p15 P3 P4 P5 P9 P10 P13 P14 P15 c1 c3 c4 c5 c6 c7 c8 c9 c10 c11 c12 c13 c14 c15 C1 C2 C3 C4 C5 C6 C7 C9 C11 C14 C15 cr0 cr1 cr3 cr4 cr5 cr6 cr7 cr8 cr9 cr10 cr11 cr12 cr13 cr14 cr15 CR0 CR1 CR2 CR3 CR4 CR5 CR6 CR7 CR8 CR9 CR10 CR11 CR12 CR13 CR14 CR15 s0 s1 s2 s3 s4 s5 s6 s7 s8 s9 s10 s11 s12 s13 s14 s15 s16 s17 s18 s19 s20 s21 s22 s23 s24 s25 s26 s27 s28 s29 s30 s31 S0 S1 S3 S4 S11 S13 S14 S15 S17 S18 S19 S21 S22 S23 S25 S26 S27 S28 S29 S30 S31 fpsid fpscr fpexc FPSID FPSCR FPEXC mvf0 mvf1 mvf2 mvf3 mvf4 mvf5 mvf6 mvf7 mvf8 mvf9 mvf10 mvf11 mvf12 mvf13 mvf14 mvf15 mvd0 mvd1 mvd2 mvd3 mvd4 mvd5 mvd6 mvd7 mvd8 mvd9 mvd10 mvd11 mvd12 mvd13 mvd14 mvd15 mvfx0 mvfx1 mvfx2 mvfx3 mvfx4 mvfx5 mvfx6 mvfx7 mvfx8 mvfx9 mvfx10 mvfx11 mvfx12 mvfx13 mvfx14 mvfx15 mvdx0 mvdx1 mvdx2 mvdx3 mvdx4 mvdx5 mvdx6 mvdx7 mvdx8 mvdx9 mvdx10 mvdx11 mvdx12 mvdx13 mvdx14 mvdx15 MVF0 MVF1 MVF2 MVF3 MVF4 MVF5 MVF6 MVF7 MVF8 MVF9 MVF10 MVF11 MVF12 MVF13 MVF14 MVF15 MVD0 MVD1 MVD2 MVD3 MVD4 MVD5 MVD6 MVD7 MVD8 MVD9 MVD10 MVD11 MVD12 MVD13 MVD14 MVD15 MVFX0 MVFX1 MVFX2 MVFX3 MVFX4 MVFX5 MVFX6 MVFX7 MVFX8 MVFX9 MVFX10 MVFX11 MVFX12 MVFX13 MVFX14 MVFX15 MVDX0 MVDX1 MVDX2 MVDX3 MVDX4 MVDX5 MVDX6 MVDX7 MVDX8 MVDX9 MVDX10 MVDX11 MVDX12 MVDX13 MVDX14 MVDX15 mvax0 mvax1 mvax2 mvax3 dspsc MVAX0 MVAX1 MVAX2 MVAX3 DSPSC wr0 wr1 wr2 wr3 wr4 wr5 wr6 wr7 wr8 wr9 wr10 wr11 wr12 wr13 wr14 wr15 wR0 wR1 wR2 wR3 wR4 wR5 wR6 wR7 wR8 wR9 wR10 wR11 wR12 wR13 wR14 wR15 WR0 WR1 WR2 WR3 WR4 WR5 WR6 WR7 WR8 WR9 WR10 WR11 WR12 WR13 WR14 WR15 wcid wCID WCID wcon wCon WCON wcssf wCSSF WCSSF wcasf wCASF WCASF wcgr0 wCGR0 WCGR0 wcgr1 wCGR1 WCGR1 wcgr2 wCGR2 WCGR2 wcgr3 wCGR3 WCGR3 acc0 ACC0 iapsr eapsr ipsr iepsr primask basepri basepri_max faultmask control flg ctl fsxc fscx fxsc fxcs fcsx fcxs sfxc sfcx sxfc sxcf scfx scxf xfsc xfcs xsfc xscf xcfs xcsf cfsx cfxs csfx csxf cxfs cxsf asl ASL LSL LSR asr ASR ROR rrx RRX hs cc pl hi ands eor eors adc adcs sbc sbcs orr orrs bic bics tst tsts tstp cmp cmpp cmn cmns cmnp movs mvn mvns ldr stm stmia stmea ldmia ldmfd swi svc adr adrl nop lsls lsrs asrs rors neg push pop cpy rsbs teq teqs teqp ldrt ldrbt strt strbt stmdb stmfd ldmdb ldmea rsc rscs stmib stmfa stmda stmed ldmib ldmed ldmda ldmfa mlas cdp ldc ldcl stc stcl swp swpb smull smulls smulleqs smullnes smullcss smullhss smullccs smulluls smulllos smullmis smullpls smullvss smullvcs smullhis smulllss smullges smulllts smullgts smullles smullals umull umulls umulleqs umullnes umullcss umullhss umullccs umulluls umulllos umullmis umullpls umullvss umullvcs umullhis umulllss umullges umulllts umullgts umullles umullals smlal smlals smlaleqs smlalnes smlalcss smlalhss smlalccs smlaluls smlallos smlalmis smlalpls smlalvss smlalvcs smlalhis smlallss smlalges smlallts smlalgts smlalles smlalals umlal umlals umlaleqs umlalnes umlalcss umlalhss umlalccs umlaluls umlallos umlalmis umlalpls umlalvss umlalvcs umlalhis umlallss umlalges umlallts umlalgts umlalles umlalals ldrsh ldrsb ldsh ldeqsh ldnesh ldcssh ldhssh ldccsh ldulsh ldlosh ldmish ldplsh ldvssh ldvcsh ldhish ldlssh ldgesh ldltsh ldgtsh ldlesh ldalsh ldsb ldeqsb ldnesb ldcssb ldhssb ldccsb ldulsb ldlosb ldmisb ldplsb ldvssb ldvcsb ldhisb ldlssb ldgesb ldltsb ldgtsb ldlesb ldalsb blx bkpt clz ldc2 ldc2l stc2 stc2l cdp2 mcr2 mrc2 smlabb smlatb smlabt smlatt smlawb smlawt smlalbb smlaltb smlalbt smlaltt smulbb smultb smulbt smultt smulwb smulwt qadd qdadd qsub qdsub pld bxj cpsie cpsid rev16 revsh sxth uxth sxtb uxtb setend ldrex mcrr2 mrrc2 ssat usat cps pkhbt pkhtb sadd16 sadd8 saddsubx shadd16 shadd8 shaddsubx shsub16 shsub8 shsubaddx ssub16 ssub8 ssubaddx uadd16 uadd8 uaddsubx uhadd16 uhadd8 uhaddsubx uhsub16 uhsub8 uhsubaddx uqadd16 uqadd8 uqaddsubx uqsub16 uqsub8 uqsubaddx usub16 usub8 usubaddx rfeia rfeib rfeda rfedb rfefd rfefa rfeea rfeed sxtah sxtab16 sxtab sxtb16 uxtah uxtab16 uxtab uxtb16 sel smlad smladx smlald smlaldx smlsd smlsdx smlsld smlsldx smmla smmlar smmls smmlsr smmul smmulr smuad smuadx smusd smusdx srsia srsib srsda srsdb ssat16 strex umaal usad8 usada8 usat16 yield wfe wfi sev ldrexd strexd ldrexb ldrexh strexb strexh clrex smc bfc bfi sbfx ubfx movw movt rbit ldrht ldrsht ldrsbt strht cbnz cbz itt ittt itet itte itee itttt itett ittet iteet ittte itete ittee iteee tbb tbh sdiv udiv pli dbg dmb wfs rfs wfc rfc ldfs ldfd ldfe ldfp stfs stfd stfe stfp mvfs mvfsp mvfsm mvfsz mvfd mvfdp mvfdm mvfdz mvfe mvfep mvfem mvfez mnfs mnfsp mnfsm mnfsz mnfd mnfdp mnfdm mnfdz mnfe mnfep mnfem mnfez abssp abssm abssz absdp absdm absdz abse absep absem absez rnds rndsp rndsm rndsz rndd rnddp rnddm rnddz rnde rndep rndem rndez sqts sqtsp sqtsm sqtsz sqtd sqtdp sqtdm sqtdz sqte sqtep sqtem sqtez logs logsp logsm logsz logd logdp logdm logdz loge logep logem logez lgns lgnsp lgnsm lgnsz lgnd lgndp lgndm lgndz lgne lgnep lgnem lgnez exps expsp expsm expsz expd expdp expdm expdz expe expep expem sins sinsp sinsm sinsz sind sindp sindm sindz sine sinep sinem sinez coss cossp cossm cossz cosd cosdp cosdm cosdz cose cosep cosem cosez tans tansp tansm tansz tand tandp tandm tandz tane tanep tanem tanez asns asnsp asnsm asnsz asnd asndp asndm asndz asne asnep asnem asnez acss acssp acssm acssz acsd acsdp acsdm acsdz acse acsep acsem acsez atns atnsp atnsm atnsz atnd atndp atndm atndz atne atnep atnem atnez urds urdsp urdsm urdsz urdd urddp urddm urddz urde urdep urdem urdez nrms nrmsp nrmsm nrmsz nrmd nrmdp nrmdm nrmdz nrme nrmep nrmem nrmez adfs adfsp adfsm adfsz adfd adfdp adfdm adfdz adfe adfep adfem adfez sufs sufsp sufsm sufsz sufd sufdp sufdm sufdz sufe sufep sufem sufez rsfs rsfsp rsfsm rsfsz rsfd rsfdp rsfdm rsfdz rsfe rsfep rsfem rsfez mufs mufsp mufsm mufsz mufd mufdp mufdm mufdz mufe mufep mufem mufez dvfs dvfsp dvfsm dvfsz dvfd dvfdp dvfdm dvfdz dvfe dvfep dvfem dvfez rdfs rdfsp rdfsm rdfsz rdfd rdfdp rdfdm rdfdz rdfe rdfep rdfem rdfez pows powsp powsm powsz powd powdp powdm powdz powe powep powem powez rpws rpwsp rpwsm rpwsz rpwd rpwdp rpwdm rpwdz rpwe rpwep rpwem rpwez rmfs rmfsp rmfsm rmfsz rmfd rmfdp rmfdm rmfdz rmfe rmfep rmfem rmfez fmls fmlsp fmlsm fmlsz fmld fmldp fmldm fmldz fmle fmlep fmlem fmlez fdvs fdvsp fdvsm fdvsz fdvd fdvdp fdvdm fdvdz fdve fdvep fdvem fdvez frds frdsp frdsm frdsz frdd frddp frddm frddz frde frdep frdem frdez pols polsp polsm polsz pold poldp poldm poldz pole polep polem polez cmf cmfe cnf cnfe flts fltsp fltsm fltsz fltd fltdp fltdm fltdz flte fltep fltem fltez fix fixp fixm fixz fixsp fixsm fixsz fixdp fixdm fixdz fixep fixem fixez lfm lfmfd lfmea sfm sfmfd sfmea fmrs fmsr fmstat fsitos fuitos ftosis ftosizs ftouis ftouizs fmrx fmxr flds fsts fldmias fldmfds fldmdbs fldmeas fldmiax fldmfdx fldmdbx fldmeax fstmias fstmeas fstmdbs fstmfds fstmiax fstmeax fstmdbx fstmfdx fsqrts fdivs fmacs fmscs fnmuls fnmacs fnmscs fcmpzs fcmpes fcmpezs fmdhr fmdlr fmrdh fmrdl fsitod fuitod ftosid ftosizd ftouid ftouizd fldd fstd fldmiad fldmfdd fldmdbd fldmead fstmiad fstmead fstmdbd fstmfdd fsqrtd fdivd fmacd fmscd fnmuld fnmacd fnmscd fcmpzd fcmped fcmpezd fmsrr fmrrs fmdrr fmrrd mar mra tandcb tandch tandcw tbcstb tbcsth tbcstw textrcb textrch textrcw textrmub textrmuh textrmuw textrmsb textrmsh textrmsw tinsrb tinsrh tinsrw tmcr tmcrr tmiaph tmiabb tmiabt tmiatb tmiatt tmovmskb tmovmskh tmovmskw tmrc tmrrc torcb torch torcw waccb wacch waccw waddbss waddb waddbus waddhss waddh waddhus waddwss waddw waddwus waligni walignr0 walignr1 walignr2 walignr3 wand wandn wavg2b wavg2br wavg2h wavg2hr wcmpeqb wcmpeqh wcmpeqw wcmpgtub wcmpgtuh wcmpgtuw wcmpgtsb wcmpgtsh wcmpgtsw wldrb wldrh wldrw wldrd wmacs wmacsz wmacu wmacuz wmadds wmaddu wmaxsb wmaxsh wmaxsw wmaxub wmaxuh wmaxuw wminsb wminsh wminsw wminub wminuh wminuw wmov wmulsm wmulsl wmulum wmulul wor wpackhss wpackhus wpackwss wpackwus wpackdss wpackdus wrorh wrorhg wrorw wrorwg wrord wrordg wsadb wsadbz wsadh wsadhz wshufh wsllh wsllhg wsllw wsllwg wslld wslldg wsrah wsrahg wsraw wsrawg wsrad wsradg wsrlh wsrlhg wsrlw wsrlwg wsrld wsrldg wstrb wstrh wstrw wstrd wsubbss wsubb wsubbus wsubhss wsubh wsubhus wsubwss wsubw wsubwus wunpckehub wunpckehuh wunpckehuw wunpckehsb wunpckehsh wunpckehsw wunpckihb wunpckihh wunpckihw wunpckelub wunpckeluh wunpckeluw wunpckelsb wunpckelsh wunpckelsw wunpckilb wunpckilh wunpckilw wxor wzero cfldrs cfldrd cfldr32 cfldr64 cfstrs cfstrd cfstr32 cfstr64 cfmvsr cfmvrs cfmvdlr cfmvrdl cfmvdhr cfmvrdh cfmv64lr cfmvr64l cfmv64hr cfmvr64h cfmval32 cfmv32al cfmvam32 cfmv32am cfmvah32 cfmv32ah cfmva32 cfmv32a cfmva64 cfmv64a cfmvsc32 cfmv32sc cfcpys cfcpyd cfcvtsd cfcvtds cfcvt32s cfcvt32d cfcvt64s cfcvt64d cfcvts32 cfcvtd32 cftruncs32 cftruncd32 cfrshl32 cfrshl64 cfsh32 cfsh64 cfcmps cfcmpd cfcmp32 cfcmp64 cfabss cfabsd cfnegs cfnegd cfadds cfaddd cfsubs cfsubd cfmuls cfmuld cfabs32 cfabs64 cfneg32 cfneg64 cfadd32 cfadd64 cfsub32 cfsub64 cfmul32 cfmul64 cfmac32 cfmsc32 cfmadd32 cfmsub32 cfmadda32 cfmsuba32 invalid constant expected #constant .req unknown register alias '%s' $d $a $t .real_start_of _GLOBAL_OFFSET_TABLE_ symbol `%s' already defined unified divided unrecognized syntax mode "%s" /data $$lit_ %x constant expression required immediate value out of range shift expression expected 'LSL' or 'ASR' required 'LSL' required invalid pseudo operation constant expression expected literal pool overflow literal pool insertion failed bad barrier type r14 not allowed here '[' expected even register required 'CPSR' or 'SPSR' expected registers may not be the same only r15 allowed here expression too complex shift expression is too large shift out of range PC not allowed as destination lo register required shift must be constant unshifted register required r15 based store not allowed ror #imm not supported data: bad call to MD_ATOF() .ARM.exidx .gnu.linkonce.armexidx. .ARM.extab .gnu.linkonce.armextab. .gnu.linkonce.t. too many unwind opcodes __aeabi_unwind_cpp_pr0 __aeabi_unwind_cpp_pr1 __aeabi_unwind_cpp_pr2 offset not a multiple of 4 offset out of range invalid smc expression invalid swi expression misaligned branch destination branch out of range rel31 relocation overflow invalid shift value: %ld undefined local label `%s' elf32-bigarm elf32-littlearm virtual memory exhausted .arm.atpcs missing cpu name `%s' unknown cpu `%s' unknown architecture `%s' unknown EABI `%s' -%-23s%s -%s%s armv .ARM.attributes invalid register list non-contiguous register range bad range in register list missing `}' invalid register mask unrecognized CPS flag missing CPS flags BE SPSR CPSR condition required invalid shift invalid rotation unhandled operand code %d r15 not allowed here bad arguments to instruction garbage following instruction ',' expected ']' expected bad instruction `%s' %s -- `%s' expected , expected register list bad register range expected , expected , unwind opcode too long invalid unwind opcode expected numeric constant bad string constant expected , expected comma assemble for CPU assemble for architecture assemble for FPU architecture assemble for floating point ABI assemble for eabi version use either -mfpu=softfpa or -mfpu=softvfp support ARM/Thumb interworking code uses 32-bit program counter code uses 26-bit program counter floating point args are in fp regs bad or missing co-processor number co-processor register expected VFP single precision register expected VFP double precision register expected Maverick MVF register expected Maverick MVD register expected Maverick MVFX register expected Maverick MVDX register expected Maverick MVAX register expected Maverick DSPSC register expected iWMMXt control register expected iWMMXt scalar register expected XScale accumulator register expected immediate expression requires a # prefix ../../../toolchain/android-toolchain/binutils-2.17/gas/config/tc-arm.c ignoring attempt to redefine built-in register '%s' ignoring redefinition of register alias '%s' unknown register '%s' -- .req ignored invalid syntax for .req directive invalid syntax for .unreq directive ignoring attempt to undefine built-in register '%s' Failed to find real start of function: %s selected processor does not support THUMB opcodes selected processor does not support ARM opcodes invalid instruction size selected (%d) invalid operand to .code directive (%d) (expecting 16 or 32) GOT already in the symbol table expected comma after name "%s" alignment too large: %d assumed alignment negative. 0 assumed. unrecognized relocation suffix (plt) is only valid on branch targets %s relocations do not fit in %d bytes personality routine specified for cantunwind frame duplicate .personalityindex directive bad personality routine number duplicate .personality directive stack increment must be multiple of 4 instruction does not accept preindexed addressing instruction does not accept unindexed addressing destination register same as write-back base source register same as write-back base instruction does not accept scaled register index instruction does not support unindexed addressing pc may not be used with write-back instruction does not support writeback Rn must not overlap other operands bit-field extends past end of register the only suffix valid here is '(plt)' use of r15 in blx in ARM mode is not really useful instruction cannot be conditional use of r15 in bx in ARM mode is not really useful use of r15 in bxj is not really useful writeback of base register is UNPREDICTABLE writeback of base register when in register list is UNPREDICTABLE if writeback register is in list, it must be the lowest reg in the list first destination register must be even can only load two consecutive registers base register written back, and overlaps second destination register index register overlaps destination register instruction does not accept this addressing mode offset must be zero in ARM encoding this instruction requires a post-indexed address rd and rm should be different in mla rd and rm should be different in mul rdhi, rdlo and rm must all be different '[' expected after PLD mnemonic post-indexed expression used in preload instruction writeback used in preload instruction unindexed addressing used in preload instruction '[' expected after PLI mnemonic rdhi and rdlo must be different can only store two consecutive registers only two consecutive VFP SP registers allowed here this addressing mode requires base-register writeback this instruction does not support indexing shift by register not allowed in thumb mode Instruction does not support =N addresses cannot use register index with PC-relative addressing cannot use register index with this instruction Thumb does not support negative register indexing Thumb does not support register post-indexing Thumb does not support register indexing with writeback Thumb supports only LSL in shifted register indexing cannot use writeback with PC-relative addressing cannot use writeback with this instruction cannot use post-indexing with PC-relative addressing cannot use post-indexing with this instruction instruction not supported in Thumb16 mode dest must overlap one source register dest and source1 must be the same register branch must be last instruction in IT block instruction is always unconditional instruction not allowed in IT block selected processor does not support 'A' form of this instruction Thumb does not support the 2-argument form of this instruction Thumb load/store multiple does not support {reglist}^ value stored for r%d is UNPREDICTABLE SP should not be in register list PC should not be in register list LR and PC should not both be in register list base register should not be in register list when written back this instruction will write back the base register this instruction will not write back the base register r14 not allowed as first register when second register is omitted Thumb does not support this addressing mode byte or halfword not valid for base register invalid base register for register offset only lo regs allowed with immediate selected processor does not support requested special purpose register selected processor does not support requested special purpose register %x Thumb encoding does not support an immediate here Thumb does not support NOP with hints push/pop do not support {reglist}^ SP not allowed in register list PC not allowed in register list invalid register list to push/pop instruction source1 and dest must be same register Thumb encoding does not support rotation instruction requires register index PC is not a valid index register instruction does not allow shifted index alignments greater than 32 bytes not supported in .text sections. SP and PC not permitted in .unwind_movsp directive unexpected .unwind_movsp directive Group section `%s' has no group signature handerdata in cantunwind frame too many unwind opcodes for personality routine 0 dupicate .handlerdata directive undefined symbol %s used as an immediate value invalid constant (%lx) after fixup unable to compute ADRL instructions for PC offset of 0x%lx invalid literal constant: pool needs to be closer bad immediate value for offset (%ld) bad immediate value for half-word offset (%ld) invalid expression in load/store multiple conditional branch out of range co-processor offset out of range invalid offset, target not word aligned (0x%08lX) invalid offset, value too big (0x%08lX) Unable to process relocation for thumb opcode: %lx invalid Hi register with immediate invalid immediate for stack address calculation invalid immediate for address calculation (value = 0x%08lX) invalid immediate: %ld is too large bad relocation fixup type (%d) literal referenced across section boundary internal relocation (type: IMMEDIATE) not fixed up ADRL used for a symbol not defined in the same file internal_relocation (type: OFFSET_IMM) not fixed up cannot represent %s relocation in this object file format use of old and new-style options to set CPU type use of old and new-style options to set FPU type hard-float conflicts with specified fpu invalid architectural extension missing architectural extension unknown architectural extnsion `%s' missing architecture name `%s' unknown floating point format `%s' unknown floating point abi `%s' ARM-specific assembler options: -EB assemble code for a big-endian cpu -EL assemble code for a little-endian cpu register list not in ascending order register range not in ascending order Warning: duplicated register (r%d) in register list Warning: register range not in ascending order invalid FPA immediate expression iWMMXt data or control register expected valid endian specifiers are be or le missing rotation field after comma rotation can only be 0, 8, 16, or 24 flag for {c}psr instruction expected cannot combine index with option cannot combine pre- and post-indexing '}' expected at end of 'option' field conditional infixes are deprecated in unified syntax selected processor does not support `%s' Thumb does not support conditional execution incorrect condition in IT block thumb conditional instrunction not in IT block cannot honor width suffix -- `%s' width suffixes are invalid in ARM mode -- `%s' FPA .unwind_save does not take a register list number of registers must be in the range [1:4] .unwind_save does not support this kind of register register must be either sp or set by a previousunwind_movsp directive F` C L` X` C L` [` C a` m` C a` p` C x` ` C x` ` C ` j C ` ` C ` ` C ` ` C ` ` C ` ` C ` ` C ` ` C ` ` C ` ` C a a C a a C a &a C a *a C 2a >a C 2a Ca C La Xa C La ^a C fa ra C fa wa C a a C a a C a a C a a C a a C a a C a a C a a C a a C a a C a b C a b C b b C b &b C /b ;b C /b Ab C Jb Vb C Jb \b C gb sb C gb {b C b ~b C b b C b b C b b C b b C b b C b b C b b C b b C b b C ? b c C ? b c C ? c c C ? c c C $c 0c C $c 3c C =c Ic C =c Pc C Xc dc C Xc ic C qc }c C qc c C ? c c C ? c c C ? c c C ? c d C d -d C 5d Fd C Kd fd C Yd jd C Yd ~d C qd d C qd d C d d C d d C d d C d d C ? d d C ? d d C d d C d d C d e C d e C e e C e 7e C !e 4e C !e l Cl Hl Ml Rl Wl \l `l dl hl ll pl tl xl l l l l l l l Dk Gk Jk h gd d d d h i Mk Pk Sk Vk Yk \k _k bk ek hk kk nk qk tk w r | 4< e} K ; wk r zk }k k bx k k k k k k =h Bh k k k k k C X m k k k ; b7 k k Q7 k k k r k Lx k k k k k k k k k k k k k r k k k k l l l u8 l l g 8 l l l l fx !l %l )l -l 1l 5l 9l =l Bl Gl Ll Ql Vl [l _l cl gl kl ol sl wl {l l l l l l l l m m m m m m m 4 d o o #o (o l l l l l l l l l l l l l l l l l l l l l l l l l l l m m m m m m m m m ?8 S J8 l #m /8 'm +m /m #8 3m 7m ;m ?m Cm Gm Km Om Sm Wm [m _m cm m m m m m m n n _{ n n n !n 'n -n 3n [o `o eo jo oo to yo ~o o o o o o o o o gm mm sm ym m m m m m m m m m m m m m m m m m m m m m m m m m n n n n n n %n +n 1n 7n =n Cn In On Un [n an gn mn sn zn n n n n n n n n n n n n n n n n n n n n o o o o o o !o &o +o 0o 5o ;o Ao Go Mo So Yo ^o co ho mo ro wo |o o o o o o o o o o o o o o o o o o o o o o p p p p p !p 'p -p 3p 9p ?p Ep Kp Qp Xp _p fp mp tp {p p p p p p p p p p p p p p p p p p p p p p p p p p p q q q q q q q q !q %q *q /q 4q 9q >q Cq Gq Kq Oq Sq Wq [q _q cq gq kq pq uq zq q q q q q q q q q q q q q q q q q q q q q q q r r r r r $r r #r %r )r /r .r x~ 4r ; V; L; + x Y 8% ( 0 v - s 8% ( 0 v - s 8% ( 0 v - s 8% ( 0 v - x 8% ? ( 0 v 8% @ ( 0 v x 8% ( 0 v 8% ( 0 v s 8% ( 0 v - $s 8% ( 0 v - )s 8% 8 ( 0 v -s 8% 9 ( 0 v 2s 8% / ( 0 v - 6s 8% 0 ( 0 v - ;s 8% ( 0 v ?s 8% ( 0 v Ds % E ( 0 Hs % E ( 0 Ms % ( Rs % ( 0 # ] % ( 0 # Vs % ( [s % ( 0 _s % ( 0 ds % ( % ' ( 0 # is % ( ( 0 # ns % + ( 0 rs % , ( 0 ws & A ( 0 e & E ( 0 e i5 & @; ( 0 e & D< ( 0 e {s : ( 0 s : ( 0 s : ( 0 i ( 0 s ( 0 s ( 0 s ( ( 0 s ( ( 0 : ) ( 0 C ); ) ( 0 s ' ( ( 0 s ' ( ( > s 7 H ( 0 W 8% # ( 0 d y s 8% $ ( 0 d y { 8% % ( 0 d y s 8% & ( 0 d y r 8% ( 0 d y s 8% ( 0 d y / 8% 6 ( 0 d y s 8% 7 ( 0 d y s &- ( 0 '. ( 0 s 2 ( 0 s 1 ( 0 s F ( 3w 8% ( v s 8% ( v s % ( s % ( s % ( s & C P ( s & G ( s & B @ ( s & F ( s ( t ( t ( t ( t 8% ( v t 8% ( v t ( !t ( 't ( -t ( 3t ( 9t ( ?t ( Et ( { 8 ) 0 8 * 0 z 0 Kt 0 Pt # 4 Tt & Xt & P ]t & at & @ " 4 " 4 ft jt , # ,1 } ot A ut A |t A t A t A t A t A t A t A t A t A t A t A t A t A t A t A u A u A u A u A $u A +u A 4u A =u A Fu A Ou A Xu A au A ju A su A |u A u A u A u A u A u A u A u A u A u A u A u A u A u A u A u A v A v A v A "v A +v A 4v A =v A Fv A Ov A Xv A av A jv A sv A |v A v A v A v A v A v A v A v A v A v A v A v A v A v A v A v A w A w A w A "w A & 0 C e & = 0 C e +w & 0 C e 1w & 0 C e 7w & 0 C e WP l l w > W@ l l x > W` l l `| d d d| 0 d d h| @ d d l| P d d p| & d d u| & d d z| & P d d | & P d d | & d d | & d d | & @ d d | & @ d d | 2 d d | 2 d d | 2 @ d d | 2 ` d d | 2 d d | 2 d d | 2 d d | 2 d d | 2 d d | 2 d d | 2 @ d d | 2 ` d d | 2 d d | 2 d d | 2 @ d d | 2 ` d d | 2 d d | 2 d d | 2 d d } 2 d d } 2 d d } 2 d d } 2 @ d d } 2 ` d d { 2 d d "} 2 d d (} 2 @ d d .} 2 ` d d 2 d d 4} 2 d d :} 2 d d @} 2 d d F} 2 ( d d K} 2 ( d d Q} 2 @ ( d d W} 2 ` ( d d ]} 2 0 d d b} 2 0 d d h} 2 @ 0 d d n} 2 ` 0 d d t} 2 0 d d y} 2 0 d d } 2 0 d d } 2 0 d d } 2 8 d d } 2 8 d d } 2 @ 8 d d } 2 ` 8 d d } 2 @ d d } 2 @ d d } 2 @ @ d d } 2 ` @ d d } 2 @ d d } 2 @ d d } 2 @ d d } 2 @ d d } 2 H d d } 2 H d d } 2 @ H d d } 2 ` H d d } 2 P d d } 2 P d d } 2 @ P d d } 2 ` P d d } 2 P d d ~ 2 P d d ~ 2 P d d ~ 2 P d d ~ 2 X d d ~ 2 X d d ~ 2 @ X d d &~ 2 ` X d d ,~ 2 ` d d 1~ 2 ` d d 7~ 2 @ ` d d =~ 2 ` ` d d C~ 2 ` d d H~ 2 ` d d N~ 2 ` d d T~ 2 ` d d Z~ 2 h d d _~ 2 h d d e~ 2 @ h d d k~ 2 ` h d d q~ 2 p d d v~ 2 p d d |~ 2 @ p d d ~ 2 ` p d d ~ 2 p d d ~ 2 p d d ~ 2 p d d ~ 2 p d d ~ 2 x d d ~ 2 x d d ~ 2 @ x d d ~ 2 ` x d d ~ 2 d d ~ 2 d d ~ 2 @ d d ~ 2 ` d d ~ 2 d d ~ 2 d d ~ 2 d d ~ 2 d d ~ 2 d d ~ 2 d d ~ 2 @ d d ~ 2 ` d d ~ 2 d d ~ 2 d d 2 @ d d 2 ` d d 2 d d 2 d d 2 d d 2 d d # 2 d d ( 2 d d . 2 @ d d 4 2 ` d d : 2 d d ? 2 d d E 2 @ d d K 2 ` d d Q 2 d d V 2 d d \ 2 d d b 2 d d h 2 d d m 2 d d s 2 @ d d y 2 ` d d 2 d d 2 d d 2 @ d d 2 ` d d 2 d d 2 d d 2 d d 2 d d 2 d d 2 d d 2 @ d d 2 ` d d 2 d d 2 d d 2 @ d d 2 ` d d 2 d d 2 d d 2 d d 2 d d 2 d d 2 d d 2 @ d d 2 ` d d 2 d d 2 d d 2 @ d d 2 ` d d 2 d d % 2 d d + 2 d d 1 2 d d 7 2 d d < 2 d d B 2 @ d d H 2 ` d d N 2 d d S 2 d d Y 2 @ d d _ 2 ` d d e 2 d d j 2 d d p 2 d d v 2 d d | 2 d d 2 d d 2 @ d d 2 ` d d 2 d d 2 d d 2 @ d d 2 ` d d 2 d d 2 d d 2 d d 2 d d 2 d d 2 d d 2 @ d d 2 ` d d 2 d d { { 2 d d { { 2 @ d d { { 2 ` d d { { 2 d d { { 2 d d { { 2 d d { { 2 d d { { 2 d d { { 2 d d { { 2 @ d d { { 2 ` d d { { 2 d d { { " 2 d d { { ( 2 @ d d { { . 2 ` d d { { 4 2 d d { { 9 2 d d { { ? 2 d d { { E 2 d d { { K 2 ( d d { { P 2 ( d d { { V 2 @ ( d d { { \ 2 ` ( d d { { b 2 0 d d { { g 2 0 d d { { m 2 @ 0 d d { { s 2 ` 0 d d { { y 2 0 d d { { ~ 2 0 d d { { 2 0 d d { { 2 0 d d { { 2 8 d d { { 2 8 d d { { 2 @ 8 d d { { 2 ` 8 d d { { 2 d d { { 2 d d { { 2 @ d d { { 2 ` d d { { 2 d d { { 2 d d { { 2 d d { { 2 d d { { 2 d d { { 2 d d { { 2 @ d d { { 2 ` d d { { 2 @ d d { { 2 @ d d { { 2 @ @ d d { { 2 ` @ d d { { 2 @ d d { { 2 @ d d { { 2 @ d d { { 2 @ d d { { 2 H d d { { 2 H d d { { % 2 @ H d d { { + 2 ` H d d { { 1 2 P d d { { 6 2 P d d { { < 2 @ P d d { { B 2 ` P d d { { H 2 P d d { { M 2 P d d { { S 2 P d d { { Y 2 P d d { { _ 2 X d d { { d 2 X d d { { j 2 @ X d d { { p 2 ` X d d { { v 2 ` d d { { { 2 ` d d { { 2 @ ` d d { { 2 ` ` d d { { 2 ` d d { { 2 ` d d { { 2 ` d d { { 2 ` d d { { 2 h d d { { 2 h d d { { 2 @ h d d { { 2 ` h d d { { 2 p d d { { 2 p d d { { 2 @ p d d { { 2 ` p d d { { 2 p d d { { 2 p d d { { 2 p d d { { 2 p d d { { 2 x d d { { 2 x d d { { 2 @ x d d { { 2 ` x d d { { 2 d d { { 2 d d { { 2 @ d d { { 2 ` d d { { 2 d d { { 2 d d { { " 2 d d { { ( 2 d d { { . 2 d d { { 3 2 d d { { 9 2 @ d d { { ? 2 ` d d { { E 2 d d { { J 2 d d { { P 2 @ d d { { V 2 ` d d { { \ 2 d d { { a 2 d d { { g 2 d d { { m 2 d d { { s 2 d d { { x 2 d d { { ~ 2 @ d d { { 2 ` d d { { 2 d d { { 2 d d { { 2 @ d d { { 2 ` d d { { 2 d d { { 2 d d { { 2 d d { { 2 d d { { 2 d d { { 2 d d { { 2 @ d d { { 2 ` d d { { 2 d d { { 2 d d { { 2 @ d d { { 2 ` d d { { 2 d d { { 2 d d { { 2 d d { { 2 d d { { 2 d d { { 2 d d { { 2 @ d d { { 2 ` d d { { 2 d d { { 2 d d { { 2 @ d d { { % 2 ` d d { { + 2 d d { { 0 2 d d { { 6 2 d d { { < 2 d d { { B 2 d d { { G 2 d d { { M 2 @ d d { { S 2 ` d d { { Y 2 d d S S ] 2 d d S S b 2 d d S S f 2 d d S S k d d p 0 d d v P d d | p d d d d d d d d d d d d 0 d d P d d p d d d d 0 d d P d d p d d 0 d d P d d p d d 0 d d P d d p d d 0 d d P d d p d d !& \ \ q q !& \ \ q q !& \ \ q q !& \ \ q q !& \ \ q q !& \ \ q q @ T T T T T T % % # T T * T T 1 @ T T 8 @ T T ? T T G @ T T N T T V T T [ T T ` & T T e & T T j T T r T T z 0 T T 0 T T T T 7 7 T T 7 7 0 T T E E 0 T T E E T T T T T T T T T T 7 7 T T 7 7 T T E E T T E E z T T @ T T T T 0 T T # # @ 0 T T # # T T # # T T # # T T # # T T # # @ T T # # @ T T # # @ T T # # \ @ @ T T P @ T T T T @ T T & P T T T T @ L L p L L d d p L L . L L 4 L L : 0 L L @ L L F L L d d M @ L L d d T @ L L [ L L c @ L L j L L r & L L w & L L | L L L L 0 L L ) ) 0 L L ) ) L L L L L L ) ) L L ) ) L L @ L L L L 0 L L { { @ 0 L L { { L L { { L L { { L L { { L L { { @ L L { { @ L L { { @ L L { { c @ @ L L P @ L L @ L L P L L @ D D J J P D D @ D D P D D { { s ( , - . / @ P ? 0 ' ? 0 S . ? 0 5 @ < P @ C @ J 0 p R 0 p S Z 0 p b p k p P t p } x x P x ` * * P ` * * ` * * @ s S S ( S S , S S - S S . S S / S S 0 0 P 0 P { { ? P ? P S ? P @ % 0 { { - { { 3 { { ; p { { C @ { { I P { { Q { { Y { { _ { { g | | o { { x { { { { { { { { 0 { { { { { { { { { { ` { { ` @ { { ` { { ` { { ` P { { ` { { ` 0 { { ` p { { ` { { & & P 3& & P " ` { { ( p { { / @ { { 5 P { { < { { C { { J ` { { Q ` ` { { X ` { { _ ` { { f ` @ { { m ` { { t ` 0 { { { ` p { { ` { { ` { { ` P { { ` { { 0 { { { { { { { { { { p { { P { { { { { { { { { { @ p { { H p { { @ { { H { { @ { { H { { { { & { { - @ { { 3 P { { : A @ P { { G H P { { N @ { { T H { { [ @ { { a H { { h @ @ { { n H @ { { u @ { { { H { { @ { { H { { @ ` { { H ` { { @ { { H { { @ { { H { { & & @ 3& & @ 0 { { { { { { p { { @ { { P { { { { { { { { @ & 1 < ` G R { { \ P { { f { { p { @ ` { { P { { { { { { 0 & @ & @ P & P & P P & @ & @ @ & P & P @ E P E P % A - A 5 C 0 = C 0 E Q N Q W S 0 ` S 0 i D @ r D @ { F ` F ` H H J J L L N | | N @ B F ` D @ H J L N X Z % \ 0 ^ ; U P D W p M P T P [ I { { b K { { i Y { { q [ { { y @ 0 B 0 D @ 0 F ` 0 H 0 { { J 0 { { L 0 { { N 0 { { @ { { B { { P 0 R 0 T @ 0 V ` 0 X 0 { { Z 0 { { \ 0 { { ^ 0 { { P { { R { { T @ { { V ` { { ` H H ( ` H H 1 ` H H ; ` 0 H H @ @ @A@A @ @ C C B (` p F @@@@ h x V ^ H H @C@C C C@B@B C C @ A A A A ` p @ B 0 @ @ P @ P 0 O P 0 0 _ _ ] 0 O _ o @ P - ` p ` p @ M O _ my_get_expression insert_reg_alias mapping_state find_real_start s_thumb_set symbol_locate parse_shift U U M encode_arm_vfp_sp_reg encode_arm_addr_mode_common encode_arm_cp_address do_fpa_ldmstm encode_thumb32_addr_mode do_t_branch do_t_ldst do_t_shift k k + + ! ! V , , , , , , , , , , , V , , , , , , , , , , , , , , , V , , , , , , , , , , , V , , , , md_convert_frag Y Y k k k k > # k k k k k Y k k Y k k k k k k k k k k k k k k k k k k k k k k k k k k k arm_relax_frag R R / " : / : " : R R F F create_unwind_entry + validate_immediate_twopart md_apply_fix $ $ $ % % 2% 9 i9 [9 b9 2- 2- 2- 2- ;9 2- D9 K9 2- R9 : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : set_constant_flonums md_begin parse_vfp_reg_list parse_operands _ a a Ek j f f g g Xg g i i `i i h h \h h l Tl n 6l l k k k m vm 2e e f e f b c b d 4d Zm ` _ l j #j e _e c _ y` cc c b b Hb a a a a da ?a ` .f A` A` ` ` ` A` A` A` A` A` A` A` A` A` A` A` A` A` A` A` A` _` _` _` A` A` A` A` A` A` A` A` A` A` A` A` A` A` A` A` A` A` _` _` _` _` A` ` A` A` A` A` A` A` A` A` A` ` A` A` A` _` _` output_inst opcode_lookup md_assemble h h R E = R E d d d d d d d d d d % d p ) O K 4 J c z r P Z L Q ; 5 5 3< ; Y X w ! w + w 0 w 7 w C = D #> 6 6Z v u u v 01 f N U 9 ` i o 9 | _ b #Z ; f I< o obj_elf_visibility u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u u # obj_elf_vtable_inherit adjust_stab_sections previous section.s sect sect.s pushsection popsection symver subsection vtable_inherit vtable_entry 2byte 4byte 8byte loc_mark_labels tls_common bss" data" bad .common segment %s .interp .strtab .symtab progbits nobits unrecognized section type ,; missing name invalid merge entity size ,comdat write alloc execinstr tls .note expected quoted string function STT_FUNC STT_OBJECT tls_object STT_TLS notype STT_NOTYPE unrecognized symbol type "%s" .comment .group can't create group: %s ../../../toolchain/android-toolchain/binutils-2.17/gas/config/obj-elf.c setting incorrect section type for %s ignoring incorrect section type for %s setting incorrect section attributes for %s ignoring changed section type for %s ignoring changed section attributes for %s ignoring changed section entity size for %s unrecognized .section attribute: want a,w,x,M,S,G,T entity size for SHF_MERGE not specified group name for SHF_GROUP not specified character following name is not '#' unrecognized section attribute .previous without corresponding .section; ignored .popsection without corresponding .pushsection; ignored expected comma after name in .symver missing version name in `%s' for symbol `%s' multiple versions [`%s'|`%s'] for symbol `%s' expected `%s' to have already been set for .vtable_inherit expected comma after name in .vtable_inherit expected comma after name in .vtable_entry expected comma after name `%s' in .size directive missing expression in .size directive .size expression too complicated to fix up invalid attempt to declare external version name as default in symbol `%s' symbol `%s' can not be both weak and common assuming all members of group `%s' are COMDAT ? ? ? ? gen_to_words C C C C C C C C C U C C C C C C C C C C C C C C C C C C C C C C C C C U C C C C C cannot create floating-point number ../../../toolchain/android-toolchain/binutils-2.17/gas/config/atof-ieee.c unknown binary UNKNOWN! i @ No error System call error Invalid bfd target File in wrong format Invalid operation Memory exhausted No symbols No more archived files Malformed archive File format not recognized File format is ambiguous Section has no contents Bad value File truncated File too big # bfd %s: %s BFD: %s(%s) %s[%s] BFD %s assertion fail %s:%d coff-go32 pe-i386 pei-i386 Archive object file in wrong format Archive has no index; run ranlib to add one Nonrepresentable section on output Symbol needs debug section which does not exist BFD %s internal error, aborting at %s line %d in %s BFD %s internal error, aborting at %s line %d ../../../toolchain/android-toolchain/binutils-2.17/bfd/bfd.c ! 3 F [ m ~ $ ../../../toolchain/android-toolchain/binutils-2.17/bfd/coffgen.c (sec %2d)(fl 0x%02x)(ty %3x)(scl %3d) (nx %d) 0x AUX scnlen 0x%lx nreloc %d nlnno %d checksum 0x%lx assoc %d comdat %d AUX tagndx %ld ttlsiz 0x%lx lnnos %ld next %ld AUX lnno %d size 0x%x tagndx %ld coff_fix_symbol_name strange .file %B: bad string table size %lu coff %s %s [%3ld] File endndx %ld %s : %4d : %-5s %s %s %s bfd_put_bits bfd_get_bits _bfd_generic_get_section_contents_in_window ../../../toolchain/android-toolchain/binutils-2.17/bfd/libbfd.c %B: compiled for a big endian system and target is little endian %B: compiled for a little endian system and target is big endian Deprecated %s called at %s line %d in %s Deprecated %s called Y j 6 = bfd_fdopenr 0 w,a Q m jp5 c d 2 y +L | ~ - d jHq A } mQ V l kdz b e O\ l cc= n;^ iL A` rqg jm Zjz ' }D h i]Wb ge q6l knv + Zz J go C ` ~ 8R O g gW ?K6 H + L J 6`z A ` U g n1y iF a f o%6 hR w G "/& U ; ( Z + j \ 1 , [ d & c ju m ?6 g r W J z + {8 |! B hn [& w owG Z pj ; f\ e i b kaE l x T N 9a&g ` MGiI wn>Jj Z f @ ; 7S G 0 0 S $ 6 )W T g #.zf Ja h] +o*7 Z -r+ .gnu_debuglink ../../../toolchain/android-toolchain/binutils-2.17/bfd/opncls.c @@uninitialized@@ BFD_RELOC_64 BFD_RELOC_32 BFD_RELOC_26 BFD_RELOC_24 BFD_RELOC_16 BFD_RELOC_14 BFD_RELOC_8 BFD_RELOC_64_PCREL BFD_RELOC_32_PCREL BFD_RELOC_24_PCREL BFD_RELOC_16_PCREL BFD_RELOC_12_PCREL BFD_RELOC_8_PCREL BFD_RELOC_32_SECREL BFD_RELOC_32_GOT_PCREL BFD_RELOC_16_GOT_PCREL BFD_RELOC_8_GOT_PCREL BFD_RELOC_32_GOTOFF BFD_RELOC_16_GOTOFF BFD_RELOC_LO16_GOTOFF BFD_RELOC_HI16_GOTOFF BFD_RELOC_HI16_S_GOTOFF BFD_RELOC_8_GOTOFF BFD_RELOC_64_PLT_PCREL BFD_RELOC_32_PLT_PCREL BFD_RELOC_24_PLT_PCREL BFD_RELOC_16_PLT_PCREL BFD_RELOC_8_PLT_PCREL BFD_RELOC_64_PLTOFF BFD_RELOC_32_PLTOFF BFD_RELOC_16_PLTOFF BFD_RELOC_LO16_PLTOFF BFD_RELOC_HI16_PLTOFF BFD_RELOC_HI16_S_PLTOFF BFD_RELOC_8_PLTOFF BFD_RELOC_68K_GLOB_DAT BFD_RELOC_68K_JMP_SLOT BFD_RELOC_68K_RELATIVE BFD_RELOC_32_BASEREL BFD_RELOC_16_BASEREL BFD_RELOC_LO16_BASEREL BFD_RELOC_HI16_BASEREL BFD_RELOC_HI16_S_BASEREL BFD_RELOC_8_BASEREL BFD_RELOC_RVA BFD_RELOC_8_FFnn BFD_RELOC_32_PCREL_S2 BFD_RELOC_16_PCREL_S2 BFD_RELOC_23_PCREL_S2 BFD_RELOC_HI22 BFD_RELOC_LO10 BFD_RELOC_GPREL16 BFD_RELOC_GPREL32 BFD_RELOC_I960_CALLJ BFD_RELOC_NONE BFD_RELOC_SPARC_WDISP22 BFD_RELOC_SPARC22 BFD_RELOC_SPARC13 BFD_RELOC_SPARC_GOT10 BFD_RELOC_SPARC_GOT13 BFD_RELOC_SPARC_GOT22 BFD_RELOC_SPARC_PC10 BFD_RELOC_SPARC_PC22 BFD_RELOC_SPARC_WPLT30 BFD_RELOC_SPARC_COPY BFD_RELOC_SPARC_GLOB_DAT BFD_RELOC_SPARC_JMP_SLOT BFD_RELOC_SPARC_RELATIVE BFD_RELOC_SPARC_UA16 BFD_RELOC_SPARC_UA32 BFD_RELOC_SPARC_UA64 BFD_RELOC_SPARC_BASE13 BFD_RELOC_SPARC_BASE22 BFD_RELOC_SPARC_10 BFD_RELOC_SPARC_11 BFD_RELOC_SPARC_OLO10 BFD_RELOC_SPARC_HH22 BFD_RELOC_SPARC_HM10 BFD_RELOC_SPARC_LM22 BFD_RELOC_SPARC_PC_HH22 BFD_RELOC_SPARC_PC_HM10 BFD_RELOC_SPARC_PC_LM22 BFD_RELOC_SPARC_WDISP16 BFD_RELOC_SPARC_WDISP19 BFD_RELOC_SPARC_7 BFD_RELOC_SPARC_6 BFD_RELOC_SPARC_5 BFD_RELOC_SPARC_PLT32 BFD_RELOC_SPARC_PLT64 BFD_RELOC_SPARC_HIX22 BFD_RELOC_SPARC_LOX10 BFD_RELOC_SPARC_H44 BFD_RELOC_SPARC_M44 BFD_RELOC_SPARC_L44 BFD_RELOC_SPARC_REGISTER BFD_RELOC_SPARC_REV32 BFD_RELOC_SPARC_TLS_GD_HI22 BFD_RELOC_SPARC_TLS_GD_LO10 BFD_RELOC_SPARC_TLS_GD_ADD BFD_RELOC_SPARC_TLS_GD_CALL BFD_RELOC_SPARC_TLS_LDM_HI22 BFD_RELOC_SPARC_TLS_LDM_LO10 BFD_RELOC_SPARC_TLS_LDM_ADD BFD_RELOC_SPARC_TLS_LDM_CALL BFD_RELOC_SPARC_TLS_LDO_HIX22 BFD_RELOC_SPARC_TLS_LDO_LOX10 BFD_RELOC_SPARC_TLS_LDO_ADD BFD_RELOC_SPARC_TLS_IE_HI22 BFD_RELOC_SPARC_TLS_IE_LO10 BFD_RELOC_SPARC_TLS_IE_LD BFD_RELOC_SPARC_TLS_IE_LDX BFD_RELOC_SPARC_TLS_IE_ADD BFD_RELOC_SPARC_TLS_LE_HIX22 BFD_RELOC_SPARC_TLS_LE_LOX10 BFD_RELOC_SPARC_TLS_DTPMOD32 BFD_RELOC_SPARC_TLS_DTPMOD64 BFD_RELOC_SPARC_TLS_DTPOFF32 BFD_RELOC_SPARC_TLS_DTPOFF64 BFD_RELOC_SPARC_TLS_TPOFF32 BFD_RELOC_SPARC_TLS_TPOFF64 BFD_RELOC_ALPHA_GPDISP_HI16 BFD_RELOC_ALPHA_GPDISP_LO16 BFD_RELOC_ALPHA_GPDISP BFD_RELOC_ALPHA_LITERAL BFD_RELOC_ALPHA_ELF_LITERAL BFD_RELOC_ALPHA_LITUSE BFD_RELOC_ALPHA_HINT BFD_RELOC_ALPHA_LINKAGE BFD_RELOC_ALPHA_CODEADDR BFD_RELOC_ALPHA_GPREL_HI16 BFD_RELOC_ALPHA_GPREL_LO16 BFD_RELOC_ALPHA_BRSGP BFD_RELOC_ALPHA_TLSGD BFD_RELOC_ALPHA_TLSLDM BFD_RELOC_ALPHA_DTPMOD64 BFD_RELOC_ALPHA_GOTDTPREL16 BFD_RELOC_ALPHA_DTPREL64 BFD_RELOC_ALPHA_DTPREL_HI16 BFD_RELOC_ALPHA_DTPREL_LO16 BFD_RELOC_ALPHA_DTPREL16 BFD_RELOC_ALPHA_GOTTPREL16 BFD_RELOC_ALPHA_TPREL64 BFD_RELOC_ALPHA_TPREL_HI16 BFD_RELOC_ALPHA_TPREL_LO16 BFD_RELOC_ALPHA_TPREL16 BFD_RELOC_MIPS_JMP BFD_RELOC_MIPS16_JMP BFD_RELOC_MIPS16_GPREL BFD_RELOC_HI16 BFD_RELOC_HI16_S BFD_RELOC_LO16 BFD_RELOC_HI16_PCREL BFD_RELOC_HI16_S_PCREL BFD_RELOC_LO16_PCREL BFD_RELOC_MIPS16_HI16 BFD_RELOC_MIPS16_HI16_S BFD_RELOC_MIPS16_LO16 BFD_RELOC_MIPS_LITERAL BFD_RELOC_MIPS_GOT16 BFD_RELOC_MIPS_CALL16 BFD_RELOC_MIPS_GOT_HI16 BFD_RELOC_MIPS_GOT_LO16 BFD_RELOC_MIPS_CALL_HI16 BFD_RELOC_MIPS_CALL_LO16 BFD_RELOC_MIPS_SUB BFD_RELOC_MIPS_GOT_PAGE BFD_RELOC_MIPS_GOT_OFST BFD_RELOC_MIPS_GOT_DISP BFD_RELOC_MIPS_SHIFT5 BFD_RELOC_MIPS_SHIFT6 BFD_RELOC_MIPS_INSERT_A BFD_RELOC_MIPS_INSERT_B BFD_RELOC_MIPS_DELETE BFD_RELOC_MIPS_HIGHEST BFD_RELOC_MIPS_HIGHER BFD_RELOC_MIPS_SCN_DISP BFD_RELOC_MIPS_REL16 BFD_RELOC_MIPS_RELGOT BFD_RELOC_MIPS_JALR BFD_RELOC_MIPS_TLS_DTPMOD32 BFD_RELOC_MIPS_TLS_DTPREL32 BFD_RELOC_MIPS_TLS_DTPMOD64 BFD_RELOC_MIPS_TLS_DTPREL64 BFD_RELOC_MIPS_TLS_GD BFD_RELOC_MIPS_TLS_LDM BFD_RELOC_MIPS_TLS_GOTTPREL BFD_RELOC_MIPS_TLS_TPREL32 BFD_RELOC_MIPS_TLS_TPREL64 BFD_RELOC_MIPS_TLS_TPREL_HI16 BFD_RELOC_MIPS_TLS_TPREL_LO16 BFD_RELOC_MIPS_COPY BFD_RELOC_MIPS_JUMP_SLOT BFD_RELOC_FRV_LABEL16 BFD_RELOC_FRV_LABEL24 BFD_RELOC_FRV_LO16 BFD_RELOC_FRV_HI16 BFD_RELOC_FRV_GPREL12 BFD_RELOC_FRV_GPRELU12 BFD_RELOC_FRV_GPREL32 BFD_RELOC_FRV_GPRELHI BFD_RELOC_FRV_GPRELLO BFD_RELOC_FRV_GOT12 BFD_RELOC_FRV_GOTHI BFD_RELOC_FRV_GOTLO BFD_RELOC_FRV_FUNCDESC BFD_RELOC_FRV_FUNCDESC_GOT12 BFD_RELOC_FRV_FUNCDESC_GOTHI BFD_RELOC_FRV_FUNCDESC_GOTLO BFD_RELOC_FRV_FUNCDESC_VALUE BFD_RELOC_FRV_GOTOFF12 BFD_RELOC_FRV_GOTOFFHI BFD_RELOC_FRV_GOTOFFLO BFD_RELOC_FRV_GETTLSOFF BFD_RELOC_FRV_TLSDESC_VALUE BFD_RELOC_FRV_GOTTLSDESC12 BFD_RELOC_FRV_GOTTLSDESCHI BFD_RELOC_FRV_GOTTLSDESCLO BFD_RELOC_FRV_TLSMOFF12 BFD_RELOC_FRV_TLSMOFFHI BFD_RELOC_FRV_TLSMOFFLO BFD_RELOC_FRV_GOTTLSOFF12 BFD_RELOC_FRV_GOTTLSOFFHI BFD_RELOC_FRV_GOTTLSOFFLO BFD_RELOC_FRV_TLSOFF BFD_RELOC_FRV_TLSDESC_RELAX BFD_RELOC_FRV_GETTLSOFF_RELAX BFD_RELOC_FRV_TLSOFF_RELAX BFD_RELOC_FRV_TLSMOFF BFD_RELOC_MN10300_GOTOFF24 BFD_RELOC_MN10300_GOT32 BFD_RELOC_MN10300_GOT24 BFD_RELOC_MN10300_GOT16 BFD_RELOC_MN10300_COPY BFD_RELOC_MN10300_GLOB_DAT BFD_RELOC_MN10300_JMP_SLOT BFD_RELOC_MN10300_RELATIVE BFD_RELOC_386_GOT32 BFD_RELOC_386_PLT32 BFD_RELOC_386_COPY BFD_RELOC_386_GLOB_DAT BFD_RELOC_386_JUMP_SLOT BFD_RELOC_386_RELATIVE BFD_RELOC_386_GOTOFF BFD_RELOC_386_GOTPC BFD_RELOC_386_TLS_TPOFF BFD_RELOC_386_TLS_IE BFD_RELOC_386_TLS_GOTIE BFD_RELOC_386_TLS_LE BFD_RELOC_386_TLS_GD BFD_RELOC_386_TLS_LDM BFD_RELOC_386_TLS_LDO_32 BFD_RELOC_386_TLS_IE_32 BFD_RELOC_386_TLS_LE_32 BFD_RELOC_386_TLS_DTPMOD32 BFD_RELOC_386_TLS_DTPOFF32 BFD_RELOC_386_TLS_TPOFF32 BFD_RELOC_386_TLS_GOTDESC BFD_RELOC_386_TLS_DESC_CALL BFD_RELOC_386_TLS_DESC BFD_RELOC_X86_64_GOT32 BFD_RELOC_X86_64_PLT32 BFD_RELOC_X86_64_COPY BFD_RELOC_X86_64_GLOB_DAT BFD_RELOC_X86_64_JUMP_SLOT BFD_RELOC_X86_64_RELATIVE BFD_RELOC_X86_64_GOTPCREL BFD_RELOC_X86_64_32S BFD_RELOC_X86_64_DTPMOD64 BFD_RELOC_X86_64_DTPOFF64 BFD_RELOC_X86_64_TPOFF64 BFD_RELOC_X86_64_TLSGD BFD_RELOC_X86_64_TLSLD BFD_RELOC_X86_64_DTPOFF32 BFD_RELOC_X86_64_GOTTPOFF BFD_RELOC_X86_64_TPOFF32 BFD_RELOC_X86_64_GOTOFF64 BFD_RELOC_X86_64_GOTPC32 BFD_RELOC_X86_64_GOT64 BFD_RELOC_X86_64_GOTPCREL64 BFD_RELOC_X86_64_GOTPC64 BFD_RELOC_X86_64_GOTPLT64 BFD_RELOC_X86_64_PLTOFF64 BFD_RELOC_X86_64_TLSDESC_CALL BFD_RELOC_X86_64_TLSDESC BFD_RELOC_NS32K_IMM_8 BFD_RELOC_NS32K_IMM_16 BFD_RELOC_NS32K_IMM_32 BFD_RELOC_NS32K_IMM_8_PCREL BFD_RELOC_NS32K_IMM_16_PCREL BFD_RELOC_NS32K_IMM_32_PCREL BFD_RELOC_NS32K_DISP_8 BFD_RELOC_NS32K_DISP_16 BFD_RELOC_NS32K_DISP_32 BFD_RELOC_NS32K_DISP_8_PCREL BFD_RELOC_NS32K_DISP_16_PCREL BFD_RELOC_NS32K_DISP_32_PCREL BFD_RELOC_PDP11_DISP_8_PCREL BFD_RELOC_PDP11_DISP_6_PCREL BFD_RELOC_PJ_CODE_HI16 BFD_RELOC_PJ_CODE_LO16 BFD_RELOC_PJ_CODE_DIR16 BFD_RELOC_PJ_CODE_DIR32 BFD_RELOC_PJ_CODE_REL16 BFD_RELOC_PJ_CODE_REL32 BFD_RELOC_PPC_B26 BFD_RELOC_PPC_BA26 BFD_RELOC_PPC_TOC16 BFD_RELOC_PPC_B16 BFD_RELOC_PPC_B16_BRTAKEN BFD_RELOC_PPC_B16_BRNTAKEN BFD_RELOC_PPC_BA16 BFD_RELOC_PPC_BA16_BRTAKEN BFD_RELOC_PPC_BA16_BRNTAKEN BFD_RELOC_PPC_COPY BFD_RELOC_PPC_GLOB_DAT BFD_RELOC_PPC_JMP_SLOT BFD_RELOC_PPC_RELATIVE BFD_RELOC_PPC_LOCAL24PC BFD_RELOC_PPC_EMB_NADDR32 BFD_RELOC_PPC_EMB_NADDR16 BFD_RELOC_PPC_EMB_NADDR16_LO BFD_RELOC_PPC_EMB_NADDR16_HI BFD_RELOC_PPC_EMB_NADDR16_HA BFD_RELOC_PPC_EMB_SDAI16 BFD_RELOC_PPC_EMB_SDA2I16 BFD_RELOC_PPC_EMB_SDA2REL BFD_RELOC_PPC_EMB_SDA21 BFD_RELOC_PPC_EMB_MRKREF BFD_RELOC_PPC_EMB_RELSEC16 BFD_RELOC_PPC_EMB_RELST_LO BFD_RELOC_PPC_EMB_RELST_HI BFD_RELOC_PPC_EMB_RELST_HA BFD_RELOC_PPC_EMB_BIT_FLD BFD_RELOC_PPC_EMB_RELSDA BFD_RELOC_PPC64_HIGHER BFD_RELOC_PPC64_HIGHER_S BFD_RELOC_PPC64_HIGHEST BFD_RELOC_PPC64_HIGHEST_S BFD_RELOC_PPC64_TOC16_LO BFD_RELOC_PPC64_TOC16_HI BFD_RELOC_PPC64_TOC16_HA BFD_RELOC_PPC64_TOC BFD_RELOC_PPC64_PLTGOT16 BFD_RELOC_PPC64_PLTGOT16_LO BFD_RELOC_PPC64_PLTGOT16_HI BFD_RELOC_PPC64_PLTGOT16_HA BFD_RELOC_PPC64_ADDR16_DS BFD_RELOC_PPC64_ADDR16_LO_DS BFD_RELOC_PPC64_GOT16_DS BFD_RELOC_PPC64_GOT16_LO_DS BFD_RELOC_PPC64_PLT16_LO_DS BFD_RELOC_PPC64_SECTOFF_DS BFD_RELOC_PPC64_SECTOFF_LO_DS BFD_RELOC_PPC64_TOC16_DS BFD_RELOC_PPC64_TOC16_LO_DS BFD_RELOC_PPC64_PLTGOT16_DS BFD_RELOC_PPC_TLS BFD_RELOC_PPC_DTPMOD BFD_RELOC_PPC_TPREL16 BFD_RELOC_PPC_TPREL16_LO BFD_RELOC_PPC_TPREL16_HI BFD_RELOC_PPC_TPREL16_HA BFD_RELOC_PPC_TPREL BFD_RELOC_PPC_DTPREL16 BFD_RELOC_PPC_DTPREL16_LO BFD_RELOC_PPC_DTPREL16_HI BFD_RELOC_PPC_DTPREL16_HA BFD_RELOC_PPC_DTPREL BFD_RELOC_PPC_GOT_TLSGD16 BFD_RELOC_PPC_GOT_TLSGD16_LO BFD_RELOC_PPC_GOT_TLSGD16_HI BFD_RELOC_PPC_GOT_TLSGD16_HA BFD_RELOC_PPC_GOT_TLSLD16 BFD_RELOC_PPC_GOT_TLSLD16_LO BFD_RELOC_PPC_GOT_TLSLD16_HI BFD_RELOC_PPC_GOT_TLSLD16_HA BFD_RELOC_PPC_GOT_TPREL16 BFD_RELOC_PPC_GOT_TPREL16_LO BFD_RELOC_PPC_GOT_TPREL16_HI BFD_RELOC_PPC_GOT_TPREL16_HA BFD_RELOC_PPC_GOT_DTPREL16 BFD_RELOC_PPC_GOT_DTPREL16_LO BFD_RELOC_PPC_GOT_DTPREL16_HI BFD_RELOC_PPC_GOT_DTPREL16_HA BFD_RELOC_PPC64_TPREL16_DS BFD_RELOC_PPC64_TPREL16_LO_DS BFD_RELOC_PPC64_DTPREL16_DS BFD_RELOC_I370_D12 BFD_RELOC_CTOR BFD_RELOC_ARM_PCREL_BRANCH BFD_RELOC_ARM_PCREL_BLX BFD_RELOC_THUMB_PCREL_BLX BFD_RELOC_ARM_PCREL_CALL BFD_RELOC_ARM_PCREL_JUMP BFD_RELOC_THUMB_PCREL_BRANCH7 BFD_RELOC_THUMB_PCREL_BRANCH9 BFD_RELOC_ARM_OFFSET_IMM BFD_RELOC_ARM_THUMB_OFFSET BFD_RELOC_ARM_TARGET1 BFD_RELOC_ARM_ROSEGREL32 BFD_RELOC_ARM_SBREL32 BFD_RELOC_ARM_TARGET2 BFD_RELOC_ARM_PREL31 BFD_RELOC_ARM_JUMP_SLOT BFD_RELOC_ARM_GLOB_DAT BFD_RELOC_ARM_GOT32 BFD_RELOC_ARM_PLT32 BFD_RELOC_ARM_RELATIVE BFD_RELOC_ARM_GOTOFF BFD_RELOC_ARM_GOTPC BFD_RELOC_ARM_TLS_GD32 BFD_RELOC_ARM_TLS_LDO32 BFD_RELOC_ARM_TLS_LDM32 BFD_RELOC_ARM_TLS_DTPOFF32 BFD_RELOC_ARM_TLS_DTPMOD32 BFD_RELOC_ARM_TLS_TPOFF32 BFD_RELOC_ARM_TLS_IE32 BFD_RELOC_ARM_TLS_LE32 BFD_RELOC_ARM_IMMEDIATE BFD_RELOC_ARM_ADRL_IMMEDIATE BFD_RELOC_ARM_T32_IMMEDIATE BFD_RELOC_ARM_T32_IMM12 BFD_RELOC_ARM_T32_ADD_PC12 BFD_RELOC_ARM_SHIFT_IMM BFD_RELOC_ARM_SMC BFD_RELOC_ARM_SWI BFD_RELOC_ARM_MULTI BFD_RELOC_ARM_CP_OFF_IMM BFD_RELOC_ARM_CP_OFF_IMM_S2 BFD_RELOC_ARM_T32_CP_OFF_IMM BFD_RELOC_ARM_ADR_IMM BFD_RELOC_ARM_LDR_IMM BFD_RELOC_ARM_LITERAL BFD_RELOC_ARM_IN_POOL BFD_RELOC_ARM_OFFSET_IMM8 BFD_RELOC_ARM_T32_OFFSET_U8 BFD_RELOC_ARM_T32_OFFSET_IMM BFD_RELOC_ARM_HWLITERAL BFD_RELOC_ARM_THUMB_ADD BFD_RELOC_ARM_THUMB_IMM BFD_RELOC_ARM_THUMB_SHIFT BFD_RELOC_SH_PCDISP8BY2 BFD_RELOC_SH_PCDISP12BY2 BFD_RELOC_SH_IMM3 BFD_RELOC_SH_IMM3U BFD_RELOC_SH_DISP12 BFD_RELOC_SH_DISP12BY2 BFD_RELOC_SH_DISP12BY4 BFD_RELOC_SH_DISP12BY8 BFD_RELOC_SH_DISP20 BFD_RELOC_SH_DISP20BY8 BFD_RELOC_SH_IMM4 BFD_RELOC_SH_IMM4BY2 BFD_RELOC_SH_IMM4BY4 BFD_RELOC_SH_IMM8 BFD_RELOC_SH_IMM8BY2 BFD_RELOC_SH_IMM8BY4 BFD_RELOC_SH_PCRELIMM8BY2 BFD_RELOC_SH_PCRELIMM8BY4 BFD_RELOC_SH_SWITCH16 BFD_RELOC_SH_SWITCH32 BFD_RELOC_SH_USES BFD_RELOC_SH_COUNT BFD_RELOC_SH_ALIGN BFD_RELOC_SH_CODE BFD_RELOC_SH_DATA BFD_RELOC_SH_LABEL BFD_RELOC_SH_LOOP_START BFD_RELOC_SH_LOOP_END BFD_RELOC_SH_COPY BFD_RELOC_SH_GLOB_DAT BFD_RELOC_SH_JMP_SLOT BFD_RELOC_SH_RELATIVE BFD_RELOC_SH_GOTPC BFD_RELOC_SH_GOT_LOW16 BFD_RELOC_SH_GOT_MEDLOW16 BFD_RELOC_SH_GOT_MEDHI16 BFD_RELOC_SH_GOT_HI16 BFD_RELOC_SH_GOTPLT_LOW16 BFD_RELOC_SH_GOTPLT_MEDLOW16 BFD_RELOC_SH_GOTPLT_MEDHI16 BFD_RELOC_SH_GOTPLT_HI16 BFD_RELOC_SH_PLT_LOW16 BFD_RELOC_SH_PLT_MEDLOW16 BFD_RELOC_SH_PLT_MEDHI16 BFD_RELOC_SH_PLT_HI16 BFD_RELOC_SH_GOTOFF_LOW16 BFD_RELOC_SH_GOTOFF_MEDLOW16 BFD_RELOC_SH_GOTOFF_MEDHI16 BFD_RELOC_SH_GOTOFF_HI16 BFD_RELOC_SH_GOTPC_LOW16 BFD_RELOC_SH_GOTPC_MEDLOW16 BFD_RELOC_SH_GOTPC_MEDHI16 BFD_RELOC_SH_GOTPC_HI16 BFD_RELOC_SH_COPY64 BFD_RELOC_SH_GLOB_DAT64 BFD_RELOC_SH_JMP_SLOT64 BFD_RELOC_SH_RELATIVE64 BFD_RELOC_SH_GOT10BY4 BFD_RELOC_SH_GOT10BY8 BFD_RELOC_SH_GOTPLT10BY4 BFD_RELOC_SH_GOTPLT10BY8 BFD_RELOC_SH_GOTPLT32 BFD_RELOC_SH_SHMEDIA_CODE BFD_RELOC_SH_IMMU5 BFD_RELOC_SH_IMMS6 BFD_RELOC_SH_IMMS6BY32 BFD_RELOC_SH_IMMU6 BFD_RELOC_SH_IMMS10 BFD_RELOC_SH_IMMS10BY2 BFD_RELOC_SH_IMMS10BY4 BFD_RELOC_SH_IMMS10BY8 BFD_RELOC_SH_IMMS16 BFD_RELOC_SH_IMMU16 BFD_RELOC_SH_IMM_LOW16 BFD_RELOC_SH_IMM_LOW16_PCREL BFD_RELOC_SH_IMM_MEDLOW16 BFD_RELOC_SH_IMM_MEDHI16 BFD_RELOC_SH_IMM_HI16 BFD_RELOC_SH_IMM_HI16_PCREL BFD_RELOC_SH_PT_16 BFD_RELOC_SH_TLS_GD_32 BFD_RELOC_SH_TLS_LD_32 BFD_RELOC_SH_TLS_LDO_32 BFD_RELOC_SH_TLS_IE_32 BFD_RELOC_SH_TLS_LE_32 BFD_RELOC_SH_TLS_DTPMOD32 BFD_RELOC_SH_TLS_DTPOFF32 BFD_RELOC_SH_TLS_TPOFF32 BFD_RELOC_ARC_B22_PCREL BFD_RELOC_ARC_B26 BFD_RELOC_BFIN_16_IMM BFD_RELOC_BFIN_16_HIGH BFD_RELOC_BFIN_4_PCREL BFD_RELOC_BFIN_5_PCREL BFD_RELOC_BFIN_16_LOW BFD_RELOC_BFIN_10_PCREL BFD_RELOC_BFIN_11_PCREL BFD_RELOC_BFIN_12_PCREL_JUMP BFD_RELOC_BFIN_GOT17M4 BFD_RELOC_BFIN_GOTHI BFD_RELOC_BFIN_GOTLO BFD_RELOC_BFIN_FUNCDESC BFD_RELOC_BFIN_FUNCDESC_GOTHI BFD_RELOC_BFIN_FUNCDESC_GOTLO BFD_RELOC_BFIN_FUNCDESC_VALUE BFD_RELOC_BFIN_GOTOFF17M4 BFD_RELOC_BFIN_GOTOFFHI BFD_RELOC_BFIN_GOTOFFLO BFD_RELOC_BFIN_GOT BFD_RELOC_BFIN_PLTPC BFD_ARELOC_BFIN_PUSH BFD_ARELOC_BFIN_CONST BFD_ARELOC_BFIN_ADD BFD_ARELOC_BFIN_SUB BFD_ARELOC_BFIN_MULT BFD_ARELOC_BFIN_DIV BFD_ARELOC_BFIN_MOD BFD_ARELOC_BFIN_LSHIFT BFD_ARELOC_BFIN_RSHIFT BFD_ARELOC_BFIN_AND BFD_ARELOC_BFIN_OR BFD_ARELOC_BFIN_XOR BFD_ARELOC_BFIN_LAND BFD_ARELOC_BFIN_LOR BFD_ARELOC_BFIN_LEN BFD_ARELOC_BFIN_NEG BFD_ARELOC_BFIN_COMP BFD_ARELOC_BFIN_PAGE BFD_ARELOC_BFIN_HWPAGE BFD_ARELOC_BFIN_ADDR BFD_RELOC_D10V_10_PCREL_R BFD_RELOC_D10V_10_PCREL_L BFD_RELOC_D10V_18 BFD_RELOC_D10V_18_PCREL BFD_RELOC_D30V_6 BFD_RELOC_D30V_9_PCREL BFD_RELOC_D30V_9_PCREL_R BFD_RELOC_D30V_15 BFD_RELOC_D30V_15_PCREL BFD_RELOC_D30V_15_PCREL_R BFD_RELOC_D30V_21 BFD_RELOC_D30V_21_PCREL BFD_RELOC_D30V_21_PCREL_R BFD_RELOC_D30V_32 BFD_RELOC_D30V_32_PCREL BFD_RELOC_DLX_HI16_S BFD_RELOC_DLX_LO16 BFD_RELOC_DLX_JMP26 BFD_RELOC_M32C_HI8 BFD_RELOC_M32C_RL_JUMP BFD_RELOC_M32C_RL_1ADDR BFD_RELOC_M32C_RL_2ADDR BFD_RELOC_M32R_24 BFD_RELOC_M32R_10_PCREL BFD_RELOC_M32R_18_PCREL BFD_RELOC_M32R_26_PCREL BFD_RELOC_M32R_HI16_ULO BFD_RELOC_M32R_HI16_SLO BFD_RELOC_M32R_LO16 BFD_RELOC_M32R_SDA16 BFD_RELOC_M32R_GOT24 BFD_RELOC_M32R_26_PLTREL BFD_RELOC_M32R_COPY BFD_RELOC_M32R_GLOB_DAT BFD_RELOC_M32R_JMP_SLOT BFD_RELOC_M32R_RELATIVE BFD_RELOC_M32R_GOTOFF BFD_RELOC_M32R_GOTOFF_HI_ULO BFD_RELOC_M32R_GOTOFF_HI_SLO BFD_RELOC_M32R_GOTOFF_LO BFD_RELOC_M32R_GOTPC24 BFD_RELOC_M32R_GOT16_HI_ULO BFD_RELOC_M32R_GOT16_HI_SLO BFD_RELOC_M32R_GOT16_LO BFD_RELOC_M32R_GOTPC_HI_ULO BFD_RELOC_M32R_GOTPC_HI_SLO BFD_RELOC_M32R_GOTPC_LO BFD_RELOC_V850_9_PCREL BFD_RELOC_V850_22_PCREL BFD_RELOC_V850_TDA_6_8_OFFSET BFD_RELOC_V850_TDA_7_8_OFFSET BFD_RELOC_V850_TDA_7_7_OFFSET BFD_RELOC_V850_TDA_4_5_OFFSET BFD_RELOC_V850_TDA_4_4_OFFSET BFD_RELOC_V850_LONGCALL BFD_RELOC_V850_LONGJUMP BFD_RELOC_V850_ALIGN BFD_RELOC_MN10300_32_PCREL BFD_RELOC_MN10300_16_PCREL BFD_RELOC_TIC30_LDP BFD_RELOC_TIC54X_PARTLS7 BFD_RELOC_TIC54X_PARTMS9 BFD_RELOC_TIC54X_23 BFD_RELOC_TIC54X_16_OF_23 BFD_RELOC_TIC54X_MS7_OF_23 BFD_RELOC_FR30_48 BFD_RELOC_FR30_20 BFD_RELOC_FR30_6_IN_4 BFD_RELOC_FR30_8_IN_8 BFD_RELOC_FR30_9_IN_8 BFD_RELOC_FR30_10_IN_8 BFD_RELOC_FR30_9_PCREL BFD_RELOC_FR30_12_PCREL BFD_RELOC_MCORE_PCREL_IMM8BY4 BFD_RELOC_MCORE_PCREL_IMM4BY2 BFD_RELOC_MCORE_PCREL_32 BFD_RELOC_MCORE_RVA BFD_RELOC_MMIX_GETA BFD_RELOC_MMIX_GETA_1 BFD_RELOC_MMIX_GETA_2 BFD_RELOC_MMIX_GETA_3 BFD_RELOC_MMIX_CBRANCH BFD_RELOC_MMIX_CBRANCH_J BFD_RELOC_MMIX_CBRANCH_1 BFD_RELOC_MMIX_CBRANCH_2 BFD_RELOC_MMIX_CBRANCH_3 BFD_RELOC_MMIX_PUSHJ BFD_RELOC_MMIX_PUSHJ_1 BFD_RELOC_MMIX_PUSHJ_2 BFD_RELOC_MMIX_PUSHJ_3 BFD_RELOC_MMIX_JMP BFD_RELOC_MMIX_JMP_1 BFD_RELOC_MMIX_JMP_2 BFD_RELOC_MMIX_JMP_3 BFD_RELOC_MMIX_ADDR19 BFD_RELOC_MMIX_ADDR27 BFD_RELOC_MMIX_REG_OR_BYTE BFD_RELOC_MMIX_REG BFD_RELOC_MMIX_LOCAL BFD_RELOC_AVR_7_PCREL BFD_RELOC_AVR_13_PCREL BFD_RELOC_AVR_16_PM BFD_RELOC_AVR_LO8_LDI BFD_RELOC_AVR_HI8_LDI BFD_RELOC_AVR_HH8_LDI BFD_RELOC_AVR_MS8_LDI BFD_RELOC_AVR_LO8_LDI_NEG BFD_RELOC_AVR_HI8_LDI_NEG BFD_RELOC_AVR_HH8_LDI_NEG BFD_RELOC_AVR_MS8_LDI_NEG BFD_RELOC_AVR_LO8_LDI_PM BFD_RELOC_AVR_HI8_LDI_PM BFD_RELOC_AVR_HH8_LDI_PM BFD_RELOC_AVR_LO8_LDI_PM_NEG BFD_RELOC_AVR_HI8_LDI_PM_NEG BFD_RELOC_AVR_HH8_LDI_PM_NEG BFD_RELOC_AVR_CALL BFD_RELOC_AVR_LDI BFD_RELOC_AVR_6 BFD_RELOC_AVR_6_ADIW BFD_RELOC_390_12 BFD_RELOC_390_GOT12 BFD_RELOC_390_PLT32 BFD_RELOC_390_COPY BFD_RELOC_390_GLOB_DAT BFD_RELOC_390_JMP_SLOT BFD_RELOC_390_RELATIVE BFD_RELOC_390_GOTPC BFD_RELOC_390_GOT16 BFD_RELOC_390_PC16DBL BFD_RELOC_390_PLT16DBL BFD_RELOC_390_PC32DBL BFD_RELOC_390_PLT32DBL BFD_RELOC_390_GOTPCDBL BFD_RELOC_390_GOT64 BFD_RELOC_390_PLT64 BFD_RELOC_390_GOTENT BFD_RELOC_390_GOTOFF64 BFD_RELOC_390_GOTPLT12 BFD_RELOC_390_GOTPLT16 BFD_RELOC_390_GOTPLT32 BFD_RELOC_390_GOTPLT64 BFD_RELOC_390_GOTPLTENT BFD_RELOC_390_PLTOFF16 BFD_RELOC_390_PLTOFF32 BFD_RELOC_390_PLTOFF64 BFD_RELOC_390_TLS_LOAD BFD_RELOC_390_TLS_GDCALL BFD_RELOC_390_TLS_LDCALL BFD_RELOC_390_TLS_GD32 BFD_RELOC_390_TLS_GD64 BFD_RELOC_390_TLS_GOTIE12 BFD_RELOC_390_TLS_GOTIE32 BFD_RELOC_390_TLS_GOTIE64 BFD_RELOC_390_TLS_LDM32 BFD_RELOC_390_TLS_LDM64 BFD_RELOC_390_TLS_IE32 BFD_RELOC_390_TLS_IE64 BFD_RELOC_390_TLS_IEENT BFD_RELOC_390_TLS_LE32 BFD_RELOC_390_TLS_LE64 BFD_RELOC_390_TLS_LDO32 BFD_RELOC_390_TLS_LDO64 BFD_RELOC_390_TLS_DTPMOD BFD_RELOC_390_TLS_DTPOFF BFD_RELOC_390_TLS_TPOFF BFD_RELOC_390_20 BFD_RELOC_390_GOT20 BFD_RELOC_390_GOTPLT20 BFD_RELOC_390_TLS_GOTIE20 BFD_RELOC_IP2K_FR9 BFD_RELOC_IP2K_BANK BFD_RELOC_IP2K_ADDR16CJP BFD_RELOC_IP2K_PAGE3 BFD_RELOC_IP2K_LO8DATA BFD_RELOC_IP2K_HI8DATA BFD_RELOC_IP2K_EX8DATA BFD_RELOC_IP2K_LO8INSN BFD_RELOC_IP2K_HI8INSN BFD_RELOC_IP2K_PC_SKIP BFD_RELOC_IP2K_TEXT BFD_RELOC_IP2K_FR_OFFSET BFD_RELOC_VPE4KMATH_DATA BFD_RELOC_VPE4KMATH_INSN BFD_RELOC_VTABLE_INHERIT BFD_RELOC_VTABLE_ENTRY BFD_RELOC_IA64_IMM14 BFD_RELOC_IA64_IMM22 BFD_RELOC_IA64_IMM64 BFD_RELOC_IA64_DIR32MSB BFD_RELOC_IA64_DIR32LSB BFD_RELOC_IA64_DIR64MSB BFD_RELOC_IA64_DIR64LSB BFD_RELOC_IA64_GPREL22 BFD_RELOC_IA64_GPREL64I BFD_RELOC_IA64_GPREL32MSB BFD_RELOC_IA64_GPREL32LSB BFD_RELOC_IA64_GPREL64MSB BFD_RELOC_IA64_GPREL64LSB BFD_RELOC_IA64_LTOFF22 BFD_RELOC_IA64_LTOFF64I BFD_RELOC_IA64_PLTOFF22 BFD_RELOC_IA64_PLTOFF64I BFD_RELOC_IA64_PLTOFF64MSB BFD_RELOC_IA64_PLTOFF64LSB BFD_RELOC_IA64_FPTR64I BFD_RELOC_IA64_FPTR32MSB BFD_RELOC_IA64_FPTR32LSB BFD_RELOC_IA64_FPTR64MSB BFD_RELOC_IA64_FPTR64LSB BFD_RELOC_IA64_PCREL21B BFD_RELOC_IA64_PCREL21BI BFD_RELOC_IA64_PCREL21M BFD_RELOC_IA64_PCREL21F BFD_RELOC_IA64_PCREL22 BFD_RELOC_IA64_PCREL60B BFD_RELOC_IA64_PCREL64I BFD_RELOC_IA64_PCREL32MSB BFD_RELOC_IA64_PCREL32LSB BFD_RELOC_IA64_PCREL64MSB BFD_RELOC_IA64_PCREL64LSB BFD_RELOC_IA64_LTOFF_FPTR22 BFD_RELOC_IA64_LTOFF_FPTR64I BFD_RELOC_IA64_SEGREL32MSB BFD_RELOC_IA64_SEGREL32LSB BFD_RELOC_IA64_SEGREL64MSB BFD_RELOC_IA64_SEGREL64LSB BFD_RELOC_IA64_SECREL32MSB BFD_RELOC_IA64_SECREL32LSB BFD_RELOC_IA64_SECREL64MSB BFD_RELOC_IA64_SECREL64LSB BFD_RELOC_IA64_REL32MSB BFD_RELOC_IA64_REL32LSB BFD_RELOC_IA64_REL64MSB BFD_RELOC_IA64_REL64LSB BFD_RELOC_IA64_LTV32MSB BFD_RELOC_IA64_LTV32LSB BFD_RELOC_IA64_LTV64MSB BFD_RELOC_IA64_LTV64LSB BFD_RELOC_IA64_IPLTMSB BFD_RELOC_IA64_IPLTLSB BFD_RELOC_IA64_COPY BFD_RELOC_IA64_LTOFF22X BFD_RELOC_IA64_LDXMOV BFD_RELOC_IA64_TPREL14 BFD_RELOC_IA64_TPREL22 BFD_RELOC_IA64_TPREL64I BFD_RELOC_IA64_TPREL64MSB BFD_RELOC_IA64_TPREL64LSB BFD_RELOC_IA64_LTOFF_TPREL22 BFD_RELOC_IA64_DTPMOD64MSB BFD_RELOC_IA64_DTPMOD64LSB BFD_RELOC_IA64_LTOFF_DTPMOD22 BFD_RELOC_IA64_DTPREL14 BFD_RELOC_IA64_DTPREL22 BFD_RELOC_IA64_DTPREL64I BFD_RELOC_IA64_DTPREL32MSB BFD_RELOC_IA64_DTPREL32LSB BFD_RELOC_IA64_DTPREL64MSB BFD_RELOC_IA64_DTPREL64LSB BFD_RELOC_IA64_LTOFF_DTPREL22 BFD_RELOC_M68HC11_HI8 BFD_RELOC_M68HC11_LO8 BFD_RELOC_M68HC11_3B BFD_RELOC_M68HC11_RL_JUMP BFD_RELOC_M68HC11_RL_GROUP BFD_RELOC_M68HC11_LO16 BFD_RELOC_M68HC11_PAGE BFD_RELOC_M68HC11_24 BFD_RELOC_M68HC12_5B BFD_RELOC_16C_NUM08 BFD_RELOC_16C_NUM08_C BFD_RELOC_16C_NUM16 BFD_RELOC_16C_NUM16_C BFD_RELOC_16C_NUM32 BFD_RELOC_16C_NUM32_C BFD_RELOC_16C_DISP04 BFD_RELOC_16C_DISP04_C BFD_RELOC_16C_DISP08 BFD_RELOC_16C_DISP08_C BFD_RELOC_16C_DISP16 BFD_RELOC_16C_DISP16_C BFD_RELOC_16C_DISP24 BFD_RELOC_16C_DISP24_C BFD_RELOC_16C_DISP24a BFD_RELOC_16C_DISP24a_C BFD_RELOC_16C_REG04 BFD_RELOC_16C_REG04_C BFD_RELOC_16C_REG04a BFD_RELOC_16C_REG04a_C BFD_RELOC_16C_REG14 BFD_RELOC_16C_REG14_C BFD_RELOC_16C_REG16 BFD_RELOC_16C_REG16_C BFD_RELOC_16C_REG20 BFD_RELOC_16C_REG20_C BFD_RELOC_16C_ABS20 BFD_RELOC_16C_ABS20_C BFD_RELOC_16C_ABS24 BFD_RELOC_16C_ABS24_C BFD_RELOC_16C_IMM04 BFD_RELOC_16C_IMM04_C BFD_RELOC_16C_IMM16 BFD_RELOC_16C_IMM16_C BFD_RELOC_16C_IMM20 BFD_RELOC_16C_IMM20_C BFD_RELOC_16C_IMM24 BFD_RELOC_16C_IMM24_C BFD_RELOC_16C_IMM32 BFD_RELOC_16C_IMM32_C BFD_RELOC_CRX_REL4 BFD_RELOC_CRX_REL8 BFD_RELOC_CRX_REL8_CMP BFD_RELOC_CRX_REL16 BFD_RELOC_CRX_REL24 BFD_RELOC_CRX_REL32 BFD_RELOC_CRX_REGREL12 BFD_RELOC_CRX_REGREL22 BFD_RELOC_CRX_REGREL28 BFD_RELOC_CRX_REGREL32 BFD_RELOC_CRX_ABS16 BFD_RELOC_CRX_ABS32 BFD_RELOC_CRX_NUM8 BFD_RELOC_CRX_NUM16 BFD_RELOC_CRX_NUM32 BFD_RELOC_CRX_IMM16 BFD_RELOC_CRX_IMM32 BFD_RELOC_CRX_SWITCH8 BFD_RELOC_CRX_SWITCH16 BFD_RELOC_CRX_SWITCH32 BFD_RELOC_CRIS_BDISP8 BFD_RELOC_CRIS_UNSIGNED_5 BFD_RELOC_CRIS_SIGNED_6 BFD_RELOC_CRIS_UNSIGNED_6 BFD_RELOC_CRIS_SIGNED_8 BFD_RELOC_CRIS_UNSIGNED_8 BFD_RELOC_CRIS_SIGNED_16 BFD_RELOC_CRIS_UNSIGNED_16 BFD_RELOC_CRIS_LAPCQ_OFFSET BFD_RELOC_CRIS_UNSIGNED_4 BFD_RELOC_CRIS_COPY BFD_RELOC_CRIS_GLOB_DAT BFD_RELOC_CRIS_JUMP_SLOT BFD_RELOC_CRIS_RELATIVE BFD_RELOC_CRIS_32_GOT BFD_RELOC_CRIS_16_GOT BFD_RELOC_CRIS_32_GOTPLT BFD_RELOC_CRIS_16_GOTPLT BFD_RELOC_CRIS_32_GOTREL BFD_RELOC_CRIS_32_PLT_GOTREL BFD_RELOC_CRIS_32_PLT_PCREL BFD_RELOC_860_COPY BFD_RELOC_860_GLOB_DAT BFD_RELOC_860_JUMP_SLOT BFD_RELOC_860_RELATIVE BFD_RELOC_860_PC26 BFD_RELOC_860_PLT26 BFD_RELOC_860_PC16 BFD_RELOC_860_LOW0 BFD_RELOC_860_SPLIT0 BFD_RELOC_860_LOW1 BFD_RELOC_860_SPLIT1 BFD_RELOC_860_LOW2 BFD_RELOC_860_SPLIT2 BFD_RELOC_860_LOW3 BFD_RELOC_860_LOGOT0 BFD_RELOC_860_SPGOT0 BFD_RELOC_860_LOGOT1 BFD_RELOC_860_SPGOT1 BFD_RELOC_860_LOGOTOFF0 BFD_RELOC_860_SPGOTOFF0 BFD_RELOC_860_LOGOTOFF1 BFD_RELOC_860_SPGOTOFF1 BFD_RELOC_860_LOGOTOFF2 BFD_RELOC_860_LOGOTOFF3 BFD_RELOC_860_LOPC BFD_RELOC_860_HIGHADJ BFD_RELOC_860_HAGOT BFD_RELOC_860_HAGOTOFF BFD_RELOC_860_HAPC BFD_RELOC_860_HIGH BFD_RELOC_860_HIGOT BFD_RELOC_860_HIGOTOFF BFD_RELOC_OPENRISC_ABS_26 BFD_RELOC_OPENRISC_REL_26 BFD_RELOC_H8_DIR16A8 BFD_RELOC_H8_DIR16R8 BFD_RELOC_H8_DIR24A8 BFD_RELOC_H8_DIR24R8 BFD_RELOC_H8_DIR32A16 BFD_RELOC_XSTORMY16_REL_12 BFD_RELOC_XSTORMY16_12 BFD_RELOC_XSTORMY16_24 BFD_RELOC_XSTORMY16_FPTR16 BFD_RELOC_XC16X_PAG BFD_RELOC_XC16X_POF BFD_RELOC_XC16X_SEG BFD_RELOC_XC16X_SOF BFD_RELOC_VAX_GLOB_DAT BFD_RELOC_VAX_JMP_SLOT BFD_RELOC_VAX_RELATIVE BFD_RELOC_MT_PC16 BFD_RELOC_MT_HI16 BFD_RELOC_MT_LO16 BFD_RELOC_MT_GNU_VTINHERIT BFD_RELOC_MT_GNU_VTENTRY BFD_RELOC_MT_PCINSN8 BFD_RELOC_MSP430_10_PCREL BFD_RELOC_MSP430_16_PCREL BFD_RELOC_MSP430_16 BFD_RELOC_MSP430_16_BYTE BFD_RELOC_MSP430_2X_PCREL BFD_RELOC_MSP430_RL_PCREL BFD_RELOC_IQ2000_OFFSET_16 BFD_RELOC_IQ2000_OFFSET_21 BFD_RELOC_IQ2000_UHI16 BFD_RELOC_XTENSA_RTLD BFD_RELOC_XTENSA_GLOB_DAT BFD_RELOC_XTENSA_JMP_SLOT BFD_RELOC_XTENSA_RELATIVE BFD_RELOC_XTENSA_PLT BFD_RELOC_XTENSA_DIFF8 BFD_RELOC_XTENSA_DIFF16 BFD_RELOC_XTENSA_DIFF32 BFD_RELOC_XTENSA_SLOT0_OP BFD_RELOC_XTENSA_SLOT1_OP BFD_RELOC_XTENSA_SLOT2_OP BFD_RELOC_XTENSA_SLOT3_OP BFD_RELOC_XTENSA_SLOT4_OP BFD_RELOC_XTENSA_SLOT5_OP BFD_RELOC_XTENSA_SLOT6_OP BFD_RELOC_XTENSA_SLOT7_OP BFD_RELOC_XTENSA_SLOT8_OP BFD_RELOC_XTENSA_SLOT9_OP BFD_RELOC_XTENSA_SLOT10_OP BFD_RELOC_XTENSA_SLOT11_OP BFD_RELOC_XTENSA_SLOT12_OP BFD_RELOC_XTENSA_SLOT13_OP BFD_RELOC_XTENSA_SLOT14_OP BFD_RELOC_XTENSA_SLOT0_ALT BFD_RELOC_XTENSA_SLOT1_ALT BFD_RELOC_XTENSA_SLOT2_ALT BFD_RELOC_XTENSA_SLOT3_ALT BFD_RELOC_XTENSA_SLOT4_ALT BFD_RELOC_XTENSA_SLOT5_ALT BFD_RELOC_XTENSA_SLOT6_ALT BFD_RELOC_XTENSA_SLOT7_ALT BFD_RELOC_XTENSA_SLOT8_ALT BFD_RELOC_XTENSA_SLOT9_ALT BFD_RELOC_XTENSA_SLOT10_ALT BFD_RELOC_XTENSA_SLOT11_ALT BFD_RELOC_XTENSA_SLOT12_ALT BFD_RELOC_XTENSA_SLOT13_ALT BFD_RELOC_XTENSA_SLOT14_ALT BFD_RELOC_XTENSA_OP0 BFD_RELOC_XTENSA_OP1 BFD_RELOC_XTENSA_OP2 BFD_RELOC_XTENSA_ASM_EXPAND BFD_RELOC_XTENSA_ASM_SIMPLIFY BFD_RELOC_Z80_DISP8 BFD_RELOC_Z8K_DISP7 BFD_RELOC_Z8K_CALLR BFD_RELOC_Z8K_IMM4L VRT32 coff-Intel-little coff-Intel-big coff-z8k BFD_RELOC_MIPS_TLS_DTPREL_HI16 BFD_RELOC_MIPS_TLS_DTPREL_LO16 BFD_RELOC_FRV_FUNCDESC_GOTOFF12 BFD_RELOC_FRV_FUNCDESC_GOTOFFHI BFD_RELOC_FRV_FUNCDESC_GOTOFFLO BFD_RELOC_X86_64_GOTPC32_TLSDESC BFD_RELOC_PPC64_PLTGOT16_LO_DS BFD_RELOC_PPC64_TPREL16_HIGHER BFD_RELOC_PPC64_TPREL16_HIGHERA BFD_RELOC_PPC64_TPREL16_HIGHEST BFD_RELOC_PPC64_TPREL16_HIGHESTA BFD_RELOC_PPC64_DTPREL16_LO_DS BFD_RELOC_PPC64_DTPREL16_HIGHER BFD_RELOC_PPC64_DTPREL16_HIGHERA BFD_RELOC_PPC64_DTPREL16_HIGHEST BFD_RELOC_PPC64_DTPREL16_HIGHESTA BFD_RELOC_THUMB_PCREL_BRANCH12 BFD_RELOC_THUMB_PCREL_BRANCH20 BFD_RELOC_THUMB_PCREL_BRANCH23 BFD_RELOC_THUMB_PCREL_BRANCH25 BFD_RELOC_ARM_T32_CP_OFF_IMM_S2 BFD_RELOC_SH_IMM_MEDLOW16_PCREL BFD_RELOC_SH_IMM_MEDHI16_PCREL BFD_RELOC_BFIN_12_PCREL_JUMP_S BFD_RELOC_BFIN_24_PCREL_CALL_X BFD_RELOC_BFIN_24_PCREL_JUMP_L BFD_RELOC_BFIN_FUNCDESC_GOT17M4 BFD_RELOC_BFIN_FUNCDESC_GOTOFF17M4 BFD_RELOC_BFIN_FUNCDESC_GOTOFFHI BFD_RELOC_BFIN_FUNCDESC_GOTOFFLO BFD_RELOC_V850_SDA_16_16_OFFSET BFD_RELOC_V850_SDA_15_16_OFFSET BFD_RELOC_V850_ZDA_16_16_OFFSET BFD_RELOC_V850_ZDA_15_16_OFFSET BFD_RELOC_V850_TDA_16_16_OFFSET BFD_RELOC_V850_SDA_16_16_SPLIT_OFFSET BFD_RELOC_V850_ZDA_16_16_SPLIT_OFFSET BFD_RELOC_V850_CALLT_6_7_OFFSET BFD_RELOC_V850_CALLT_16_16_OFFSET BFD_RELOC_V850_LO16_SPLIT_OFFSET BFD_RELOC_MCORE_PCREL_IMM11BY2 BFD_RELOC_MCORE_PCREL_JSR_IMM11BY2 BFD_RELOC_MMIX_PUSHJ_STUBBABLE BFD_RELOC_MMIX_BASE_PLUS_OFFSET BFD_RELOC_IA64_LTOFF_FPTR32MSB BFD_RELOC_IA64_LTOFF_FPTR32LSB BFD_RELOC_IA64_LTOFF_FPTR64MSB BFD_RELOC_IA64_LTOFF_FPTR64LSB BFD_RELOC_MSP430_16_PCREL_BYTE @@overflow: BFD_RELOC_UNUSED@@ ../../../toolchain/android-toolchain/binutils-2.17/bfd/reloc.c ' 4 @ S f y 1 G ] u " 6 L b z * C W e v 6 H Z p $ = R g | % = U m + ? S g " ? [ x " = X u " > Z v 9 T j 6 Q i % : Q f | 5 N a y 2 H ` u % , L < X s # 6 I _ v ( E b l . I a y . I _ z * > R e | . C Y r ( ? V m 5 N e | / H b | 0 M d | ' > U m 5 H c # @ ] z . I d ~ + D X q 1 M h - F _ s $ A ^ x # @ [ y 0 P p , G _ y @ ` 1 J ` v " 9 Q i 8 P k # 9 O e 2 K ] p 0 B W l ( ; S i { 0 J g 3 O h , B X q 5 L c w $ 7 N e } " 8 O f } @ ` ! 9 W u 0 D X m ' ; O d y + D V n 2 E \ t * ? T m 2 I e , L l 6 T r @ ) = V o 5 L d d # : S l 5 J ` v & < R l " ? \ o 7 K _ u $ ; R i & = T n / F ^ v ) = V k " ; T m # : R l 5 P g , C [ s ( H / J e 4 L d | 3 J b | 7 P k 5 P g ~ & ; R g ~ . C Z n , @ V j $ ; O c w " 6 J ^ t 6 O j ) B [ t - @ S h { 7 O g ) = T n $ ; V j ~ ! < U j h 5 L b | & @ Z t + F a | 9 T o 1 F [ p bfd_get_reloc_size ' {' ' ' ' ' ' {' {' {' ' bfd_check_overflow bfd_perform_relocation * , + + Y, + + / . / / %0 / @/ _bfd_relocate_contents bfd_generic_get_relocated_section_contents *IND* *COM* .%d 1 + @ p X @ bfd_get_unique_section_name bfd_map_over_sections ../../../toolchain/android-toolchain/binutils-2.17/bfd/section.c *DEBUG* .drectve .edata .fini .idata .init .pdata .rdata .rodata .sbss .scommon .sdata zerovars %c%c%c%c%c%c%c Unsupported .stab relocation ; b e t d % N (1 N - i 6 e = t C i J t P p W r ^ r f s l c u g t d | b H K @ $ @# `) `' , h! K {! H ! ! H ! H ! ! K ! ! H V" ! ! ! " " +" H 8" H D" H P" H `" H armeb-*-netbsdelf* arm-*-netbsdelf* arm-*-nto* nto*arm* arm-*-rtems* armeb-*-elf arm*b-*-linux-* strongarm-*-kaos* arm-*-freebsd* arm*-*-linux-* arm*-*-conix* arm*-*-uclinux* arm-*-kfreebsd*-gnu arm*-*-eabi* arm9e-*-elf thumb-*-elf strongarm-*-elf xscale-*-elf GNUTARGET default bfd_hash_replace ! ;A ../../../toolchain/android-toolchain/binutils-2.17/bfd/hash.c symbolsrec \%03o .sec%d $$ $$ %-5s %s " w [ h ; c [ h ; c |b Y U n w Ic 2 _ u I D $n 6n B o n E E $ $ Eg ig n E5 5 M 15 ;5 9A @A + + + + + # w [ h ; c [ h ; c a Y U m w Ic 2 _ u I D $n 6n B o n E E $ $ Eg ig n E5 5 M 15 ;5 9A @A + + + + + 0123456789ABCDEF m` %_ ` A` 4[ m` 4[ y` !a +a j j j j i i i j j j %B:%d: Unexpected character `%s' in S-record file ../../../toolchain/android-toolchain/binutils-2.17/bfd/srec.c _binary_%s_%s { [ h ; c [ h ; c no do Vp 2 _ u I D p Vq B D cr E E $ $ xr es E5 5 M 15 ;5 9A @A + + + + + Warning: Writing section `%s' to huge (ie negative) file offset 0x%lx. tekhex $ %0781010 C) w [ h ; c [ h ; c x w U } w z 2 _ u I D w w E E + + { { E5 5 M 15 ;5 9A @A + + + + + 0123456789ABCDEF dv .v dv dv dv u dv dv dv pass_over out tekhex_write_object_contents $ 5 $ $ 5 H Y Y Y j ../../../toolchain/android-toolchain/binutils-2.17/bfd/tekhex.c ihex p, [ h ; c [ h ; c ` U w E 2 _ u I D $ $ B D D + $ $ k K E5 5 M 15 ;5 9A @A + + + + + 0123456789ABCDEF B 7 %B:%d: unexpected character `%s' in Intel Hex file ../../../toolchain/android-toolchain/binutils-2.17/bfd/ihex.c %B: internal error in ihex_read_section %B: bad section length in ihex_read_section %s: address 0x%s out of range for Intel Hex file %B:%u: bad checksum in Intel Hex file (expected %u, found %u) %B:%u: bad extended address record length in Intel Hex file %B:%u: bad extended start address length in Intel Hex file %B:%u: bad extended linear address record length in Intel Hex file %B:%u: bad extended linear start address length in Intel Hex file %B:%u: unrecognized ihex type %u in Intel Hex file read_address c c S ~ $ O n m scan_unit_for_symbols U W 1 r > ../../../toolchain/android-toolchain/binutils-2.17/bfd/dwarf2.c Dwarf Error: Can't find .debug_str section. Dwarf Error: DW_FORM_strp offset (%lu) greater than or equal to .debug_str size (%lu). Dwarf Error: Invalid or unhandled FORM value: %u. Dwarf Error: mangled line number section (bad file number). Dwarf Error: Could not find abbrev number %u. Dwarf Error: Can't find .debug_ranges section. Dwarf Error: found dwarf version '%u', this reader only handles version 2 information. Dwarf Error: found address size '%u', this reader can not handle sizes greater than '%u'. Dwarf Error: found address size '%u', this reader can only handle address sizes '2', '4' and '8'. Dwarf Error: Can't find .debug_abbrev section. Dwarf Error: Abbrev offset (%lu) greater than or equal to .debug_abbrev size (%lu). Dwarf Error: Bad abbrev number: %u. Dwarf Error: Can't find .debug_line section. Dwarf Error: Line offset (%lu) greater than or equal to .debug_line size (%lu). Dwarf Error: mangled line number section. .debug_str .debug_ranges .gnu.linkonce.wi. elf32-littlearm-symbian .dynamic .dynstr .dynsym .hash .init_array .fini_array .preinit_array elf32-bigarm-symbian elf32-littlearm-vxworks elf32-bigarm-vxworks R_ARM_RREL32 R_ARM_RABS32 R_ARM_RPC24 R_ARM_RBASE R_ARM_MOVW_BREL_NC R_ARM_MOVT_BREL R_ARM_MOVW_BREL R_ARM_THM_MOVW_BREL_NC R_ARM_THM_MOVT_BREL R_ARM_THM_MOVW_BREL R_ARM_PLT32_ABS R_ARM_GOT_ABS R_ARM_GOT_PREL R_ARM_GOT_BREL12 R_ARM_GOTOFF12 R_ARM_GNU_VTENTRY R_ARM_GNU_VTINHERIT R_ARM_THM_JUMP11 R_ARM_THM_JUMP8 R_ARM_TLS_GD32 R_ARM_TLS_LDM32 R_ARM_TLS_LDO32 R_ARM_TLS_IE32 R_ARM_TLS_LE32 R_ARM_TLS_LDO12 R_ARM_TLS_LE12 R_ARM_TLS_IE12GP R_ARM_NONE R_ARM_PC24 R_ARM_ABS32 R_ARM_REL32 R_ARM_PC13 R_ARM_ABS16 R_ARM_ABS12 R_ARM_THM_ABS5 R_ARM_ABS8 R_ARM_SBREL32 R_ARM_THM_CALL R_ARM_THM_PC8 R_ARM_BREL_ADJ R_ARM_SWI24 R_ARM_SWI8 R_ARM_XPC25 R_ARM_THM_XPC22 R_ARM_TLS_DTPMOD32 R_ARM_TLS_DTPOFF32 R_ARM_TLS_TPOFF32 R_ARM_COPY R_ARM_GLOB_DAT R_ARM_JUMP_SLOT R_ARM_RELATIVE R_ARM_GOTOFF32 R_ARM_GOTPC R_ARM_GOT32 R_ARM_PLT32 R_ARM_CALL R_ARM_JUMP24 R_ARM_THM_JUMP24 R_ARM_BASE_ABS R_ARM_ALU_PCREL_7_0 R_ARM_ALU_PCREL_15_8 R_ARM_ALU_PCREL_23_15 R_ARM_LDR_SBREL_11_0 R_ARM_ALU_SBREL_19_12 R_ARM_ALU_SBREL_27_20 R_ARM_TARGET1 R_ARM_ROSEGREL32 R_ARM_V4BX R_ARM_TARGET2 R_ARM_PREL31 R_ARM_MOVW_ABS_NC R_ARM_MOVT_ABS R_ARM_MOVW_PREL_NC R_ARM_MOVT_PREL R_ARM_THM_MOVW_ABS_NC R_ARM_THM_MOVT_ABS R_ARM_THM_MOVW_PREL_NC R_ARM_THM_MOVT_PREL R_ARM_THM_JUMP19 R_ARM_THM_JUMP6 R_ARM_THM_ALU_PREL_11_0 R_ARM_THM_PC12 R_ARM_ABS32_NOI R_ARM_REL32_NOI .reg .rel .rela .got.plt .rel.got .rela.got .rel.plt .rela.plt .dynbss .rel.bss .rela.bss .glue_7 .glue_7t __%s_from_arm __%s_from_thumb __%s_change_to_arm got-rel (local) internal error: unknown error .note.gnu.arm.ident private flags = %lx: [interworking enabled] [APCS-26] [APCS-32] [VFP float format] [Maverick float format] [FPA float format] [position independent] [new ABI] [old ABI] [software FP] [Version1 EABI] [sorted symbol table] [unsorted symbol table] [Version2 EABI] [Version3 EABI] [Version4 EABI] [Version5 EABI] [BE8] [LE8] [relocatable executable] [has entry point] %B: bad symbol index: %d /usr/lib/ld.so.1 .gnu.version .gnu.version_d .gnu.version_r aeabi 5 ? / 5 I O 5 I O t Y p U " S w V T ] 2 T : A p #p 7p ] c h i s ~ "Y X ;! 6# V b# w# n- # v. & / E E O # ( ' E5 5 Y M 6y K n b @A W v! Y9 ! 2" B @ ( A 8 %W % r P `P P T L ( 0 8 c > G bY |P X qY j & `& O * ek | 7 7 8P $ ) * * * hU k} ^ L @A 5 5 5 ; 5 5 5 5 5 ? / [ h ; c [ h ; c t Y p U " S w V T ] 2 T : A p #p 7p ] c h i s ~ "Y X ;! 6# V b# w# n- # v. & / E E O # ( ' E5 5 Y M 6y K n b @A W v! Y9 ! 2" `> @ 6 ? / 5 I O 5 I O t Y p U " S w V T ] 2 T : A p #p 7p ] c h i s ~ "Y X ;! 6# V b# w# n- # v. & / E E O # ( ' E5 5 X M 6y K n b @A W v! Y9 ! 2" F @E ( A 8 %W % r P `P P T L ( 0 8 c > G X X W j & `& O * | 7 7 8P $ ) * * * hU k} ^ L 6 ? / [ h ; c [ h ; c t Y p U " S w V T ] 2 T : A p #p 7p ] c h i s ~ "Y X ;! 6# V b# w# n- # v. & / E E O # ( ' E5 5 X M 6y K n b @A W v! Y9 ! 2" C @E 6 ? / 5 I O 5 I O t Y p U " S w V T ] 2 T : A p #p 7p ] c h i s ~ "Y X ;! 6# V b# w# n- # v. & / E E O # ( ' E5 5 M 6y K n b @A W v! Y9 ! 2" K I ( A 8 %W % r P `P P T L ( 0 8 c > G |P X W j & `& O * ek | 7 7 8P $ ) * * * hU k} ^ L ) ? / [ h ; c [ h ; c t Y p U " S w V T ] 2 T : A p #p 7p ] c h i s ~ "Y X ;! 6# V b# w# n- # v. & / E E O # ( ' E5 5 M 6y K n b @A W v! Y9 ! 2" H I 4 ( b c ` ?W W Xn f Q` ` H_ _ _ ` - - xG F -6 :6 G6 S6 T _6 U r6 V 6 W 6 p p X 6 p p Y 6 p p Z [ \ ] ^ 6 _ 6 ` 6 a 6 b 7 c d >+ 7 e 07 f D7 g U7 h e7 i t7 j 7 k 7 l 7 m 7 n 7 o 7 7 7 7 8 8 8 '8 38 B8 M8 [8 j8 x8 8 8 8 8 8 8 8 8 8 9 9 +9 :9 F9 R9 ^9 i9 v9 / / 9 9 ! 9 " 9 # 9 $ 9 % : & : ' $: ( 5: ) @: * N: + [: , m: - |: . : / : p p 0 : p p 1 : p p 2 : p p 3 : /? /? 4 ; 5 ; p p 6 ,; p p 7 ;; 8 K; FxG 7 f 3 g 4 & ' * ) h j i k l e ! d create_got_section elf32_arm_create_dynamic_sections bfd_elf32_arm_process_before_allocation insert_thumb_branch elf32_arm_final_link_relocate W m W W W W W W W W W W W W ) w % W W W W W W ! W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W z R 1 ! R R X R R R R R R R R 1 R R R R R R R R R R R 1 1 1 R R R R R R R R R R R R u copy_eabi_attributes elf32_arm_merge_eabi_attributes _ 6 ) E' }' }' }' E' E' E' E' E' E' }' E' E' E' E' E' E' E' E' E' E' E' E' E' E' E' ^' }' }' }' E' E' E' E' E' E' E' E' E' E' E' E' }' E' E' E' E' E' E' E' E' E' E' E' E' E' E' E' E' E' E' E' E' E' E' E' E' E' E' E' E' E' E' E' E' E' E' E' E' E' E' E' E' E' E' E' E' E' E' E' E' E' E' E' E' E' ^' E' E' E' E' E' E' E' ^' ' E' ^' ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) o* o* * ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) * ) ) ) + * ) ) * `* ) * allocate_dynrelocs ../../../toolchain/android-toolchain/binutils-2.17/bfd/elf32-arm.c %B: BE8 images only valid in big-endian mode. Invalid TARGET2 relocation type '%s'. %B(%A+0x%lx): %s relocation against SEC_MERGE section %B(%A+0x%lx): %s used with TLS symbol %s %B(%A+0x%lx): %s used with non-TLS symbol %s %B: Warning: Arm BLX instruction targets Arm function '%s'. %B: unable to find ARM glue '%s' for `%s' %B(%s): warning: interworking not enabled. first occurrence: %B: arm call to thumb %B: Warning: Thumb BLX instruction targets thumb function '%s'. %B: unable to find THUMB glue '%s' for `%s' %B(%s): warning: interworking not enabled. first occurrence: %B: thumb call to arm %B(%A+0x%lx): R_ARM_TLS_LE32 relocation not permitted in shared object %B(%A+0x%lx): unresolvable %s relocation against symbol `%s' internal error: out of range error internal error: unsupported relocation error internal error: dangerous error Warning: Not setting interworking flag of %B since it has already been specified as non-interworking Warning: Clearing the interworking flag of %B due to outside request Warning: Clearing the interworking flag of %B because non-interworking code in %B has been linked with it ERROR: %B uses VFP register arguments, %B does not ERROR: %B: Conflicting architecture profiles %c/%c Warning: %B: Conflicting platform configuration ERROR: %B: Conflicting use of R9 ERROR: %B: SB relative addressing conflicts with use of R9 ERROR: %B: Conflicting definitions of wchar_t ERROR: %B: Conflicting enum sizes ERROR: %B uses iWMMXt register arguments, %B does not ERROR: %B: Must be processed by '%s' toolchain ERROR: %B: Incompatible object tag '%s':%d Warning: %B: Unknown EABI object attribute %d ERROR: Source object %B has EABI version %d, but target %B has EABI version %d ERROR: %B is compiled for APCS-%d, whereas target %B uses APCS-%d ERROR: %B passes floats in float registers, whereas %B passes them in integer registers ERROR: %B passes floats in integer registers, whereas %B passes them in float registers ERROR: %B uses VFP instructions, whereas %B does not ERROR: %B uses FPA instructions, whereas %B does not ERROR: %B uses Maverick instructions, whereas %B does not ERROR: %B does not use Maverick instructions, whereas %B does ERROR: %B uses software FP, whereas %B uses hardware FP ERROR: %B uses hardware FP, whereas %B uses software FP Warning: %B supports interworking, whereas %B does not Warning: %B does not support interworking, whereas %B does [floats passed in float registers] [dynamic symbols use segment index] [mapping symbols precede others] dynamic variable `%s' is zero size 4 ( b c ` Y Z Xn f Q` ` H_ _ _ ` bfd_elf32_swap_symbol_in bfd_elf32_swap_symbol_out bfd_elf32_write_relocs i Vj _j ej uj i i ../../../toolchain/android-toolchain/binutils-2.17/bfd/elfcode.h %s: version count (%ld) does not match symbol count (%ld) %s(%s): relocation %d has invalid symbol index %ld warning: %s has a corrupt string table index - ignoring __GOTT_INDEX__ __GOTT_BASE__ .rela.plt.unloaded .rel.plt.unloaded LARGE_COMMON SHT_NULL SHT_PROGBITS SHT_SYMTAB SHT_STRTAB SHT_RELA SHT_HASH SHT_DYNAMIC SHT_NOTE SHT_NOBITS SHT_REL SHT_SHLIB SHT_DYNSYM .tbss .tdata .shstrtab .rodata1 .gnu.linkonce.b .gnu.liblist .gnu.conflict .data1 (null) RELRO INTERP PHDR EH_FRAME STACK elf (*none*) %s Base %-11s (%s) .internal .hidden .protected 0x%02x %B: invalid SHT_GROUP entry %s%d%s %s%db Program Header: 0x%lx %8s off 0x vaddr 0x paddr 0x align 2**%u filesz 0x memsz 0x flags %c%c%c Dynamic Section: USED FILTER NEEDED PLTRELSZ PLTGOT RELASZ RELAENT STRSZ SYMENT INIT FINI SONAME RPATH SYMBOLIC RELENT DEBUG TEXTREL JMPREL BIND_NOW FINI_ARRAY FINI_ARRAYSZ RUNPATH FLAGS PREINIT_ARRAY PREINIT_ARRAYSZ CHECKSUM PLTPADSZ MOVEENT MOVESZ FEATURE POSFLAG_1 SYMINSZ SYMINENT CONFIG DEPAUDIT PLTPAD MOVETAB SYMINFO RELACOUNT RELCOUNT FLAGS_1 VERSYM VERDEF VERDEFNUM VERNEED VERNEEDNUM AUXILIARY %-11s Version definitions: %d 0x%2.2x 0x%8.8lx %s %s Version References: required from %s: Section to Segment mapping: LOPROC+%7.7x LOOS+%7.7x %8.8x %2.2d: %14.14s: *unknown* .symtab_shndx .gnu.libstr %s/%d %s/%ld null load NetBSD-CORE .note.netbsdcore.procinfo .reg2 QNX .qnx_core_info .qnx_core_status/%ld .qnx_core_status LINUX .reg-xfp .auxv shlib phdr relro t t t t t u u u &u 1u 9u Cu Nu Tu [u Q ^ eu e; `; 5 ; \ /1 J 5 5 nu ; > o +> o :> o ~u o u = 5 u (1 + 5 5 5 ; = %lu for section `%s' %B: warning: sh_link not set for section `%A' %B: sh_link [%d] in section `%A' is incorrect %B: unknown [%d] section `%s' in group [%s] ../../../toolchain/android-toolchain/binutils-2.17/bfd/elf.c %B: invalid link %lu for reloc section %s (index %u) %B: no group info for section %A 0x%8.8lx 0x%2.2x %2.2d %s %B: Not enough room for program headers (allocated %u, need %u) Segment Sections... %B: The first section in the PT_DYNAMIC segment is not the .dynamic section %B: Not enough room for program headers, try linking with -N %B: section %A lma 0x%lx overlaps previous sections %B: warning: allocated section `%s' not in segment %B: symbol `%s' required but not present %B: warning: Empty loadable segment detected, is this intentional ? %B: sh_link of section `%A' points to discarded section `%A' of `%B' %B: sh_link of section `%A' points to removed section `%A' of `%B' Unable to find equivalent output section for symbol '%s' from section '%s' %B: unsupported relocation type %s % C a @ N nT nT T T T _bfd_elf_link_output_relocs elf_link_add_object_symbols bfd_elf_size_dynsym_hash_dynstr elf_link_adjust_relocs elf_link_check_versioned_symbol ; ; f elf_link_output_extsym B B 9 elf_reloc_link_order _bfd_elf_section_already_linked .eh_frame_hdr _PROCEDURE_LINKAGE_TABLE_ .gnu.warning. .tcommon %s: undefined version: %s .gcc_except_table .rela.dyn .rel.dyn .gcc_except_table. .gnu.linkonce. %s: TLS definition in %B section %A mismatches non-TLS definition in %B section %A %s: TLS reference in %B mismatches non-TLS reference in %B %s: TLS definition in %B section %A mismatches non-TLS reference in %B %s: TLS reference in %B mismatches non-TLS definition in %B section %A ../../../toolchain/android-toolchain/binutils-2.17/bfd/elflink.c %B: unexpected redefinition of indirect versioned symbol `%s' %B: undefined versioned symbol name %s %B: bad reloc symbol index (0x%lx >= 0x%lx) for offset 0x%lx in section `%A' %B: relocation size mismatch in %B section %A warning: type and size of dynamic symbol `%s' are not defined %B: %s: invalid version %u (max %d) %B: %s: invalid needed version %d Warning: alignment %u of symbol `%s' in %B is smaller than %u in %B Warning: size of symbol `%s' changed from %lu in %B to %lu in %B Warning: type of symbol `%s' changed from %d to %d in %B %s: invalid DSO for symbol `%s' definition %B: .preinit_array section is not allowed in DSO %B: Too many sections: %d (>= %d) %B: %s symbol `%s' in %B is referenced by DSO %B: could not find output section %A for input section %A %B: %s symbol `%s' isn't defined %A has both ordered [`%A' in %B] and unordered [`%A' in %B] sections %A has both ordered and unordered sections error: %B contains a reloc (0x%s) for section %A that references a non-existent global symbol %X`%s' referenced in section `%A' of %B: defined in discarded section `%A' of %B Not enough memory to sort relocations %B: could not find output section %s warning: %s section has zero size warning: creating a DT_TEXTREL in a shared object. Warning: gc-sections option ignored %B: %A+%lu: No symbol found for INHERIT %B: ignoring duplicate section `%A' %B: duplicate section `%A' has different size %B: warning: could not read contents of section `%A' %B: warning: duplicate section `%A' has different contents ../../../toolchain/android-toolchain/binutils-2.17/bfd/elf-strtab.c ../../../toolchain/android-toolchain/binutils-2.17/bfd/elf-eh-frame.c _bfd_elf_write_section_eh_frame @ @ @ A @ @ zA zA zA @ = = @ zA zA %A 6@ @ @ zA = = = = = = = = = bA = = = = = = = = = = = = = = = = zA @ = = = = = = = = = = = = = = = = @ = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = zA = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = @ H H %I H I I %I MI H elf32-little elf32-big UNKNOWN ? / 5 I O 5 I O t Y p U " S w * g ] 2 | T : A p #p 7p ] c h i s ~ "Y X ;! 6# V b# w# # % & & E E u4 # ( ' E5 5 M iO K n b @A W v! Y9 ! 2" A N N r L j ek 7 7 7 $ ) * * * k} ^ r ? / [ h ; c [ h ; c t Y p U " S w * g ] 2 | T : A p #p 7p ] c h i s ~ "Y X ;! 6# V b# w# # % & & E E u4 # ( ' E5 5 M iO K n b @A W v! Y9 ! 2" @ %B: Relocations in generic ELF (EM: %d) sa1 armv3M XScale iWMMXt arch: ; ; O O ; dd O O ; |d O O ; d O O ; d O O @ ; d O O p ; d O O ; d O O ; e O O ; ,e O O 0 ; &d O O ` ; j O O ; ?d O O R gS pS |S S S S S S S S S S ERROR: %B is compiled for the EP9312, whereas %B is compiled for XScale warning: unable to update contents of %s section in %s ! ! __.SYMDEF __.SYMDEF/ / /SYM64/ ARFILENAMES/ // %-ld // ARFILENAMES/ __.SYMDEF %-10ld %-7lo %-12ld %-8lo ` bfd_dont_truncate_arname ../../../toolchain/android-toolchain/binutils-2.17/bfd/archive.c Reading archive file mod timestamp Writing updated armap timestamp Warning: writing archive was slow: rewriting timestamp bfd_stat ../../../toolchain/android-toolchain/binutils-2.17/bfd/bfdio.c 2 D p . bfd_cache_lookup_worker ../../../toolchain/android-toolchain/binutils-2.17/bfd/cache.c w+ reopening %B: %s _bfd_generic_link_add_one_symbol S S ] u & 3 & u _bfd_generic_link_output_symbols P set_symbol_from_hash Y _bfd_generic_link_write_global_symbol _bfd_generic_reloc_link_order _bfd_default_link_order _bfd_generic_section_already_linked __real_ __imp_%s GLOBAL_ ../../../toolchain/android-toolchain/binutils-2.17/bfd/linker.c %B: indirect symbol `%s' to `%s' is a loop Attempt to do relocatable link with %s input and %s output %B: warning: ignoring duplicate section `%A' %B: warning: duplicate section `%A' has different size %B(%A+0x%lx): Stabs entry has invalid string index. ../../../toolchain/android-toolchain/binutils-2.17/bfd/stabs.c _bfd_add_merge_section _bfd_merged_section_offset ../../../toolchain/android-toolchain/binutils-2.17/bfd/merge.c %s: access beyond end of merged section (%ld) out of memory PWD %I $ < ;G ]t B { = 0 $ ~ `2 fC O m A oE! a 0 P A A ? & * " @ ` 0 P H X ? " A ! ) ? Cannot find prime bigger than %lu cccccccccccccccccccccccccccccccccccccccccccccccc ccccccc cccccccccccccccccccccccccc ccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccc !"#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_`ABCDEFGHIJKLMNOPQRSTUVWXYZ{|}~ !"#$%&'()*+,-./0123456789:;<=>?@abcdefghijklmnopqrstuvwxyz[\]^_`abcdefghijklmnopqrstuvwxyz{|}~ C B B B B Q 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 %s%sout of memory allocating %lu bytes after a total of %lu bytes undocumented error #%d
d ? d < $% ` \ I &` K -` L 3` L ?` $ L h e D e e C e x C e C e C e C e e D f f C %f 1f @ If Xf @ sf f f f 0 f 8 f h g g h h h h h ; j ; > j ) k n k k k _ k "k )k 0k 3k 9k
