1 //===-- ARMMCTargetDesc.cpp - ARM Target Descriptions -----------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file provides ARM specific target descriptions. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "ARMMCTargetDesc.h" 15 #include "ARMMCAsmInfo.h" 16 #include "ARMBaseInfo.h" 17 #include "InstPrinter/ARMInstPrinter.h" 18 #include "llvm/MC/MCCodeGenInfo.h" 19 #include "llvm/MC/MCInstrAnalysis.h" 20 #include "llvm/MC/MCInstrInfo.h" 21 #include "llvm/MC/MCRegisterInfo.h" 22 #include "llvm/MC/MCStreamer.h" 23 #include "llvm/MC/MCSubtargetInfo.h" 24 #include "llvm/Support/ErrorHandling.h" 25 #include "llvm/Support/TargetRegistry.h" 26 27 #define GET_REGINFO_MC_DESC 28 #include "ARMGenRegisterInfo.inc" 29 30 #define GET_INSTRINFO_MC_DESC 31 #include "ARMGenInstrInfo.inc" 32 33 #define GET_SUBTARGETINFO_MC_DESC 34 #include "ARMGenSubtargetInfo.inc" 35 36 using namespace llvm; 37 38 std::string ARM_MC::ParseARMTriple(StringRef TT) { 39 // Set the boolean corresponding to the current target triple, or the default 40 // if one cannot be determined, to true. 41 unsigned Len = TT.size(); 42 unsigned Idx = 0; 43 44 // FIXME: Enhance Triple helper class to extract ARM version. 45 bool isThumb = false; 46 if (Len >= 5 && TT.substr(0, 4) == "armv") 47 Idx = 4; 48 else if (Len >= 6 && TT.substr(0, 5) == "thumb") { 49 isThumb = true; 50 if (Len >= 7 && TT[5] == 'v') 51 Idx = 6; 52 } 53 54 std::string ARMArchFeature; 55 if (Idx) { 56 unsigned SubVer = TT[Idx]; 57 if (SubVer >= '7' && SubVer <= '9') { 58 if (Len >= Idx+2 && TT[Idx+1] == 'm') { 59 // v7m: FeatureNoARM, FeatureDB, FeatureHWDiv, FeatureMClass 60 ARMArchFeature = "+v7,+noarm,+db,+hwdiv,+mclass"; 61 } else if (Len >= Idx+3 && TT[Idx+1] == 'e'&& TT[Idx+2] == 'm') { 62 // v7em: FeatureNoARM, FeatureDB, FeatureHWDiv, FeatureDSPThumb2, 63 // FeatureT2XtPk, FeatureMClass 64 ARMArchFeature = "+v7,+noarm,+db,+hwdiv,+t2dsp,t2xtpk,+mclass"; 65 } else 66 // v7a: FeatureNEON, FeatureDB, FeatureDSPThumb2, FeatureT2XtPk 67 ARMArchFeature = "+v7,+neon,+db,+t2dsp,+t2xtpk"; 68 } else if (SubVer == '6') { 69 if (Len >= Idx+3 && TT[Idx+1] == 't' && TT[Idx+2] == '2') 70 ARMArchFeature = "+v6t2"; 71 else if (Len >= Idx+2 && TT[Idx+1] == 'm') 72 // v6m: FeatureNoARM, FeatureMClass 73 ARMArchFeature = "+v6t2,+noarm,+mclass"; 74 else 75 ARMArchFeature = "+v6"; 76 } else if (SubVer == '5') { 77 if (Len >= Idx+3 && TT[Idx+1] == 't' && TT[Idx+2] == 'e') 78 ARMArchFeature = "+v5te"; 79 else 80 ARMArchFeature = "+v5t"; 81 } else if (SubVer == '4' && Len >= Idx+2 && TT[Idx+1] == 't') 82 ARMArchFeature = "+v4t"; 83 } 84 85 if (isThumb) { 86 if (ARMArchFeature.empty()) 87 ARMArchFeature = "+thumb-mode"; 88 else 89 ARMArchFeature += ",+thumb-mode"; 90 } 91 92 return ARMArchFeature; 93 } 94 95 MCSubtargetInfo *ARM_MC::createARMMCSubtargetInfo(StringRef TT, StringRef CPU, 96 StringRef FS) { 97 std::string ArchFS = ARM_MC::ParseARMTriple(TT); 98 if (!FS.empty()) { 99 if (!ArchFS.empty()) 100 ArchFS = ArchFS + "," + FS.str(); 101 else 102 ArchFS = FS; 103 } 104 105 MCSubtargetInfo *X = new MCSubtargetInfo(); 106 InitARMMCSubtargetInfo(X, TT, CPU, ArchFS); 107 return X; 108 } 109 110 static MCInstrInfo *createARMMCInstrInfo() { 111 MCInstrInfo *X = new MCInstrInfo(); 112 InitARMMCInstrInfo(X); 113 return X; 114 } 115 116 static MCRegisterInfo *createARMMCRegisterInfo(StringRef Triple) { 117 MCRegisterInfo *X = new MCRegisterInfo(); 118 InitARMMCRegisterInfo(X, ARM::LR); 119 return X; 120 } 121 122 static MCAsmInfo *createARMMCAsmInfo(const Target &T, StringRef TT) { 123 Triple TheTriple(TT); 124 125 if (TheTriple.isOSDarwin()) 126 return new ARMMCAsmInfoDarwin(); 127 128 return new ARMELFMCAsmInfo(); 129 } 130 131 static MCCodeGenInfo *createARMMCCodeGenInfo(StringRef TT, Reloc::Model RM, 132 CodeModel::Model CM) { 133 MCCodeGenInfo *X = new MCCodeGenInfo(); 134 if (RM == Reloc::Default) { 135 Triple TheTriple(TT); 136 // Default relocation model on Darwin is PIC, not DynamicNoPIC. 137 RM = TheTriple.isOSDarwin() ? Reloc::PIC_ : Reloc::DynamicNoPIC; 138 } 139 X->InitMCCodeGenInfo(RM, CM); 140 return X; 141 } 142 143 // This is duplicated code. Refactor this. 144 static MCStreamer *createMCStreamer(const Target &T, StringRef TT, 145 MCContext &Ctx, MCAsmBackend &MAB, 146 raw_ostream &OS, 147 MCCodeEmitter *Emitter, 148 bool RelaxAll, 149 bool NoExecStack) { 150 Triple TheTriple(TT); 151 152 if (TheTriple.isOSDarwin()) 153 return createMachOStreamer(Ctx, MAB, OS, Emitter, RelaxAll); 154 155 if (TheTriple.isOSWindows()) { 156 llvm_unreachable("ARM does not support Windows COFF format"); 157 return NULL; 158 } 159 160 return createELFStreamer(Ctx, MAB, OS, Emitter, RelaxAll, NoExecStack); 161 } 162 163 static MCInstPrinter *createARMMCInstPrinter(const Target &T, 164 unsigned SyntaxVariant, 165 const MCAsmInfo &MAI, 166 const MCSubtargetInfo &STI) { 167 if (SyntaxVariant == 0) 168 return new ARMInstPrinter(MAI, STI); 169 return 0; 170 } 171 172 namespace { 173 174 class ARMMCInstrAnalysis : public MCInstrAnalysis { 175 public: 176 ARMMCInstrAnalysis(const MCInstrInfo *Info) : MCInstrAnalysis(Info) {} 177 178 virtual bool isUnconditionalBranch(const MCInst &Inst) const { 179 // BCCs with the "always" predicate are unconditional branches. 180 if (Inst.getOpcode() == ARM::Bcc && Inst.getOperand(1).getImm()==ARMCC::AL) 181 return true; 182 return MCInstrAnalysis::isUnconditionalBranch(Inst); 183 } 184 185 virtual bool isConditionalBranch(const MCInst &Inst) const { 186 // BCCs with the "always" predicate are unconditional branches. 187 if (Inst.getOpcode() == ARM::Bcc && Inst.getOperand(1).getImm()==ARMCC::AL) 188 return false; 189 return MCInstrAnalysis::isConditionalBranch(Inst); 190 } 191 192 uint64_t evaluateBranch(const MCInst &Inst, uint64_t Addr, 193 uint64_t Size) const { 194 // We only handle PCRel branches for now. 195 if (Info->get(Inst.getOpcode()).OpInfo[0].OperandType!=MCOI::OPERAND_PCREL) 196 return -1ULL; 197 198 int64_t Imm = Inst.getOperand(0).getImm(); 199 // FIXME: This is not right for thumb. 200 return Addr+Imm+8; // In ARM mode the PC is always off by 8 bytes. 201 } 202 }; 203 204 } 205 206 static MCInstrAnalysis *createARMMCInstrAnalysis(const MCInstrInfo *Info) { 207 return new ARMMCInstrAnalysis(Info); 208 } 209 210 // Force static initialization. 211 extern "C" void LLVMInitializeARMTargetMC() { 212 // Register the MC asm info. 213 RegisterMCAsmInfoFn A(TheARMTarget, createARMMCAsmInfo); 214 RegisterMCAsmInfoFn B(TheThumbTarget, createARMMCAsmInfo); 215 216 // Register the MC codegen info. 217 TargetRegistry::RegisterMCCodeGenInfo(TheARMTarget, createARMMCCodeGenInfo); 218 TargetRegistry::RegisterMCCodeGenInfo(TheThumbTarget, createARMMCCodeGenInfo); 219 220 // Register the MC instruction info. 221 TargetRegistry::RegisterMCInstrInfo(TheARMTarget, createARMMCInstrInfo); 222 TargetRegistry::RegisterMCInstrInfo(TheThumbTarget, createARMMCInstrInfo); 223 224 // Register the MC register info. 225 TargetRegistry::RegisterMCRegInfo(TheARMTarget, createARMMCRegisterInfo); 226 TargetRegistry::RegisterMCRegInfo(TheThumbTarget, createARMMCRegisterInfo); 227 228 // Register the MC subtarget info. 229 TargetRegistry::RegisterMCSubtargetInfo(TheARMTarget, 230 ARM_MC::createARMMCSubtargetInfo); 231 TargetRegistry::RegisterMCSubtargetInfo(TheThumbTarget, 232 ARM_MC::createARMMCSubtargetInfo); 233 234 // Register the MC instruction analyzer. 235 TargetRegistry::RegisterMCInstrAnalysis(TheARMTarget, 236 createARMMCInstrAnalysis); 237 TargetRegistry::RegisterMCInstrAnalysis(TheThumbTarget, 238 createARMMCInstrAnalysis); 239 240 // Register the MC Code Emitter 241 TargetRegistry::RegisterMCCodeEmitter(TheARMTarget, createARMMCCodeEmitter); 242 TargetRegistry::RegisterMCCodeEmitter(TheThumbTarget, createARMMCCodeEmitter); 243 244 // Register the asm backend. 245 TargetRegistry::RegisterMCAsmBackend(TheARMTarget, createARMAsmBackend); 246 TargetRegistry::RegisterMCAsmBackend(TheThumbTarget, createARMAsmBackend); 247 248 // Register the object streamer. 249 TargetRegistry::RegisterMCObjectStreamer(TheARMTarget, createMCStreamer); 250 TargetRegistry::RegisterMCObjectStreamer(TheThumbTarget, createMCStreamer); 251 252 // Register the MCInstPrinter. 253 TargetRegistry::RegisterMCInstPrinter(TheARMTarget, createARMMCInstPrinter); 254 TargetRegistry::RegisterMCInstPrinter(TheThumbTarget, createARMMCInstPrinter); 255 } 256
