1 //===- X86RegisterInfo.cpp - X86 Register Information -----------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the X86 implementation of the TargetRegisterInfo class. 11 // This file is responsible for the frame pointer elimination optimization 12 // on X86. 13 // 14 //===----------------------------------------------------------------------===// 15 16 #include "X86.h" 17 #include "X86RegisterInfo.h" 18 #include "X86InstrBuilder.h" 19 #include "X86MachineFunctionInfo.h" 20 #include "X86Subtarget.h" 21 #include "X86TargetMachine.h" 22 #include "llvm/Constants.h" 23 #include "llvm/Function.h" 24 #include "llvm/Type.h" 25 #include "llvm/CodeGen/ValueTypes.h" 26 #include "llvm/CodeGen/MachineInstrBuilder.h" 27 #include "llvm/CodeGen/MachineFunction.h" 28 #include "llvm/CodeGen/MachineFunctionPass.h" 29 #include "llvm/CodeGen/MachineFrameInfo.h" 30 #include "llvm/CodeGen/MachineModuleInfo.h" 31 #include "llvm/CodeGen/MachineRegisterInfo.h" 32 #include "llvm/MC/MCAsmInfo.h" 33 #include "llvm/Target/TargetFrameLowering.h" 34 #include "llvm/Target/TargetInstrInfo.h" 35 #include "llvm/Target/TargetMachine.h" 36 #include "llvm/Target/TargetOptions.h" 37 #include "llvm/ADT/BitVector.h" 38 #include "llvm/ADT/STLExtras.h" 39 #include "llvm/Support/ErrorHandling.h" 40 #include "llvm/Support/CommandLine.h" 41 42 #define GET_REGINFO_TARGET_DESC 43 #include "X86GenRegisterInfo.inc" 44 45 using namespace llvm; 46 47 cl::opt<bool> 48 ForceStackAlign("force-align-stack", 49 cl::desc("Force align the stack to the minimum alignment" 50 " needed for the function."), 51 cl::init(false), cl::Hidden); 52 53 X86RegisterInfo::X86RegisterInfo(X86TargetMachine &tm, 54 const TargetInstrInfo &tii) 55 : X86GenRegisterInfo(tm.getSubtarget<X86Subtarget>().is64Bit() 56 ? X86::RIP : X86::EIP, 57 X86_MC::getDwarfRegFlavour(tm.getTargetTriple(), false), 58 X86_MC::getDwarfRegFlavour(tm.getTargetTriple(), true)), 59 TM(tm), TII(tii) { 60 X86_MC::InitLLVM2SEHRegisterMapping(this); 61 62 // Cache some information. 63 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>(); 64 Is64Bit = Subtarget->is64Bit(); 65 IsWin64 = Subtarget->isTargetWin64(); 66 67 if (Is64Bit) { 68 SlotSize = 8; 69 StackPtr = X86::RSP; 70 FramePtr = X86::RBP; 71 } else { 72 SlotSize = 4; 73 StackPtr = X86::ESP; 74 FramePtr = X86::EBP; 75 } 76 } 77 78 /// getCompactUnwindRegNum - This function maps the register to the number for 79 /// compact unwind encoding. Return -1 if the register isn't valid. 80 int X86RegisterInfo::getCompactUnwindRegNum(unsigned RegNum, bool isEH) const { 81 switch (getLLVMRegNum(RegNum, isEH)) { 82 case X86::EBX: case X86::RBX: return 1; 83 case X86::ECX: case X86::R12: return 2; 84 case X86::EDX: case X86::R13: return 3; 85 case X86::EDI: case X86::R14: return 4; 86 case X86::ESI: case X86::R15: return 5; 87 case X86::EBP: case X86::RBP: return 6; 88 } 89 90 return -1; 91 } 92 93 int 94 X86RegisterInfo::getSEHRegNum(unsigned i) const { 95 int reg = X86_MC::getX86RegNum(i); 96 switch (i) { 97 case X86::R8: case X86::R8D: case X86::R8W: case X86::R8B: 98 case X86::R9: case X86::R9D: case X86::R9W: case X86::R9B: 99 case X86::R10: case X86::R10D: case X86::R10W: case X86::R10B: 100 case X86::R11: case X86::R11D: case X86::R11W: case X86::R11B: 101 case X86::R12: case X86::R12D: case X86::R12W: case X86::R12B: 102 case X86::R13: case X86::R13D: case X86::R13W: case X86::R13B: 103 case X86::R14: case X86::R14D: case X86::R14W: case X86::R14B: 104 case X86::R15: case X86::R15D: case X86::R15W: case X86::R15B: 105 case X86::XMM8: case X86::XMM9: case X86::XMM10: case X86::XMM11: 106 case X86::XMM12: case X86::XMM13: case X86::XMM14: case X86::XMM15: 107 case X86::YMM8: case X86::YMM9: case X86::YMM10: case X86::YMM11: 108 case X86::YMM12: case X86::YMM13: case X86::YMM14: case X86::YMM15: 109 reg += 8; 110 } 111 return reg; 112 } 113 114 const TargetRegisterClass * 115 X86RegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, 116 unsigned Idx) const { 117 // The sub_8bit sub-register index is more constrained in 32-bit mode. 118 // It behaves just like the sub_8bit_hi index. 119 if (!Is64Bit && Idx == X86::sub_8bit) 120 Idx = X86::sub_8bit_hi; 121 122 // Forward to TableGen's default version. 123 return X86GenRegisterInfo::getSubClassWithSubReg(RC, Idx); 124 } 125 126 const TargetRegisterClass * 127 X86RegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A, 128 const TargetRegisterClass *B, 129 unsigned SubIdx) const { 130 switch (SubIdx) { 131 default: return 0; 132 case X86::sub_8bit: 133 if (B == &X86::GR8RegClass) { 134 if (A->getSize() == 2 || A->getSize() == 4 || A->getSize() == 8) 135 return A; 136 } else if (B == &X86::GR8_ABCD_LRegClass || B == &X86::GR8_ABCD_HRegClass) { 137 if (A == &X86::GR64RegClass || A == &X86::GR64_ABCDRegClass || 138 A == &X86::GR64_NOREXRegClass || 139 A == &X86::GR64_NOSPRegClass || 140 A == &X86::GR64_NOREX_NOSPRegClass) 141 return &X86::GR64_ABCDRegClass; 142 else if (A == &X86::GR32RegClass || A == &X86::GR32_ABCDRegClass || 143 A == &X86::GR32_NOREXRegClass || 144 A == &X86::GR32_NOSPRegClass) 145 return &X86::GR32_ABCDRegClass; 146 else if (A == &X86::GR16RegClass || A == &X86::GR16_ABCDRegClass || 147 A == &X86::GR16_NOREXRegClass) 148 return &X86::GR16_ABCDRegClass; 149 } else if (B == &X86::GR8_NOREXRegClass) { 150 if (A == &X86::GR64RegClass || A == &X86::GR64_NOREXRegClass || 151 A == &X86::GR64_NOSPRegClass || A == &X86::GR64_NOREX_NOSPRegClass) 152 return &X86::GR64_NOREXRegClass; 153 else if (A == &X86::GR64_ABCDRegClass) 154 return &X86::GR64_ABCDRegClass; 155 else if (A == &X86::GR32RegClass || A == &X86::GR32_NOREXRegClass || 156 A == &X86::GR32_NOSPRegClass) 157 return &X86::GR32_NOREXRegClass; 158 else if (A == &X86::GR32_ABCDRegClass) 159 return &X86::GR32_ABCDRegClass; 160 else if (A == &X86::GR16RegClass || A == &X86::GR16_NOREXRegClass) 161 return &X86::GR16_NOREXRegClass; 162 else if (A == &X86::GR16_ABCDRegClass) 163 return &X86::GR16_ABCDRegClass; 164 } 165 break; 166 case X86::sub_8bit_hi: 167 if (B->hasSubClassEq(&X86::GR8_ABCD_HRegClass)) 168 switch (A->getSize()) { 169 case 2: return getCommonSubClass(A, &X86::GR16_ABCDRegClass); 170 case 4: return getCommonSubClass(A, &X86::GR32_ABCDRegClass); 171 case 8: return getCommonSubClass(A, &X86::GR64_ABCDRegClass); 172 default: return 0; 173 } 174 break; 175 case X86::sub_16bit: 176 if (B == &X86::GR16RegClass) { 177 if (A->getSize() == 4 || A->getSize() == 8) 178 return A; 179 } else if (B == &X86::GR16_ABCDRegClass) { 180 if (A == &X86::GR64RegClass || A == &X86::GR64_ABCDRegClass || 181 A == &X86::GR64_NOREXRegClass || 182 A == &X86::GR64_NOSPRegClass || 183 A == &X86::GR64_NOREX_NOSPRegClass) 184 return &X86::GR64_ABCDRegClass; 185 else if (A == &X86::GR32RegClass || A == &X86::GR32_ABCDRegClass || 186 A == &X86::GR32_NOREXRegClass || A == &X86::GR32_NOSPRegClass) 187 return &X86::GR32_ABCDRegClass; 188 } else if (B == &X86::GR16_NOREXRegClass) { 189 if (A == &X86::GR64RegClass || A == &X86::GR64_NOREXRegClass || 190 A == &X86::GR64_NOSPRegClass || A == &X86::GR64_NOREX_NOSPRegClass) 191 return &X86::GR64_NOREXRegClass; 192 else if (A == &X86::GR64_ABCDRegClass) 193 return &X86::GR64_ABCDRegClass; 194 else if (A == &X86::GR32RegClass || A == &X86::GR32_NOREXRegClass || 195 A == &X86::GR32_NOSPRegClass) 196 return &X86::GR32_NOREXRegClass; 197 else if (A == &X86::GR32_ABCDRegClass) 198 return &X86::GR64_ABCDRegClass; 199 } 200 break; 201 case X86::sub_32bit: 202 if (B == &X86::GR32RegClass) { 203 if (A->getSize() == 8) 204 return A; 205 } else if (B == &X86::GR32_NOSPRegClass) { 206 if (A == &X86::GR64RegClass || A == &X86::GR64_NOSPRegClass) 207 return &X86::GR64_NOSPRegClass; 208 if (A->getSize() == 8) 209 return getCommonSubClass(A, &X86::GR64_NOSPRegClass); 210 } else if (B == &X86::GR32_ABCDRegClass) { 211 if (A == &X86::GR64RegClass || A == &X86::GR64_ABCDRegClass || 212 A == &X86::GR64_NOREXRegClass || 213 A == &X86::GR64_NOSPRegClass || 214 A == &X86::GR64_NOREX_NOSPRegClass) 215 return &X86::GR64_ABCDRegClass; 216 } else if (B == &X86::GR32_NOREXRegClass) { 217 if (A == &X86::GR64RegClass || A == &X86::GR64_NOREXRegClass) 218 return &X86::GR64_NOREXRegClass; 219 else if (A == &X86::GR64_NOSPRegClass || A == &X86::GR64_NOREX_NOSPRegClass) 220 return &X86::GR64_NOREX_NOSPRegClass; 221 else if (A == &X86::GR64_ABCDRegClass) 222 return &X86::GR64_ABCDRegClass; 223 } else if (B == &X86::GR32_NOREX_NOSPRegClass) { 224 if (A == &X86::GR64RegClass || A == &X86::GR64_NOREXRegClass || 225 A == &X86::GR64_NOSPRegClass || A == &X86::GR64_NOREX_NOSPRegClass) 226 return &X86::GR64_NOREX_NOSPRegClass; 227 else if (A == &X86::GR64_ABCDRegClass) 228 return &X86::GR64_ABCDRegClass; 229 } 230 break; 231 case X86::sub_ss: 232 if (B == &X86::FR32RegClass) 233 return A; 234 break; 235 case X86::sub_sd: 236 if (B == &X86::FR64RegClass) 237 return A; 238 break; 239 case X86::sub_xmm: 240 if (B == &X86::VR128RegClass) 241 return A; 242 break; 243 } 244 return 0; 245 } 246 247 const TargetRegisterClass* 248 X86RegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC) const{ 249 // Don't allow super-classes of GR8_NOREX. This class is only used after 250 // extrating sub_8bit_hi sub-registers. The H sub-registers cannot be copied 251 // to the full GR8 register class in 64-bit mode, so we cannot allow the 252 // reigster class inflation. 253 // 254 // The GR8_NOREX class is always used in a way that won't be constrained to a 255 // sub-class, so sub-classes like GR8_ABCD_L are allowed to expand to the 256 // full GR8 class. 257 if (RC == X86::GR8_NOREXRegisterClass) 258 return RC; 259 260 const TargetRegisterClass *Super = RC; 261 TargetRegisterClass::sc_iterator I = RC->getSuperClasses(); 262 do { 263 switch (Super->getID()) { 264 case X86::GR8RegClassID: 265 case X86::GR16RegClassID: 266 case X86::GR32RegClassID: 267 case X86::GR64RegClassID: 268 case X86::FR32RegClassID: 269 case X86::FR64RegClassID: 270 case X86::RFP32RegClassID: 271 case X86::RFP64RegClassID: 272 case X86::RFP80RegClassID: 273 case X86::VR128RegClassID: 274 case X86::VR256RegClassID: 275 // Don't return a super-class that would shrink the spill size. 276 // That can happen with the vector and float classes. 277 if (Super->getSize() == RC->getSize()) 278 return Super; 279 } 280 Super = *I++; 281 } while (Super); 282 return RC; 283 } 284 285 const TargetRegisterClass * 286 X86RegisterInfo::getPointerRegClass(unsigned Kind) const { 287 switch (Kind) { 288 default: llvm_unreachable("Unexpected Kind in getPointerRegClass!"); 289 case 0: // Normal GPRs. 290 if (TM.getSubtarget<X86Subtarget>().is64Bit()) 291 return &X86::GR64RegClass; 292 return &X86::GR32RegClass; 293 case 1: // Normal GPRs except the stack pointer (for encoding reasons). 294 if (TM.getSubtarget<X86Subtarget>().is64Bit()) 295 return &X86::GR64_NOSPRegClass; 296 return &X86::GR32_NOSPRegClass; 297 case 2: // Available for tailcall (not callee-saved GPRs). 298 if (TM.getSubtarget<X86Subtarget>().isTargetWin64()) 299 return &X86::GR64_TCW64RegClass; 300 if (TM.getSubtarget<X86Subtarget>().is64Bit()) 301 return &X86::GR64_TCRegClass; 302 return &X86::GR32_TCRegClass; 303 } 304 } 305 306 const TargetRegisterClass * 307 X86RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const { 308 if (RC == &X86::CCRRegClass) { 309 if (Is64Bit) 310 return &X86::GR64RegClass; 311 else 312 return &X86::GR32RegClass; 313 } 314 return RC; 315 } 316 317 unsigned 318 X86RegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC, 319 MachineFunction &MF) const { 320 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 321 322 unsigned FPDiff = TFI->hasFP(MF) ? 1 : 0; 323 switch (RC->getID()) { 324 default: 325 return 0; 326 case X86::GR32RegClassID: 327 return 4 - FPDiff; 328 case X86::GR64RegClassID: 329 return 12 - FPDiff; 330 case X86::VR128RegClassID: 331 return TM.getSubtarget<X86Subtarget>().is64Bit() ? 10 : 4; 332 case X86::VR64RegClassID: 333 return 4; 334 } 335 } 336 337 const unsigned * 338 X86RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { 339 bool callsEHReturn = false; 340 bool ghcCall = false; 341 342 if (MF) { 343 callsEHReturn = MF->getMMI().callsEHReturn(); 344 const Function *F = MF->getFunction(); 345 ghcCall = (F ? F->getCallingConv() == CallingConv::GHC : false); 346 } 347 348 static const unsigned GhcCalleeSavedRegs[] = { 349 0 350 }; 351 352 static const unsigned CalleeSavedRegs32Bit[] = { 353 X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0 354 }; 355 356 static const unsigned CalleeSavedRegs32EHRet[] = { 357 X86::EAX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0 358 }; 359 360 static const unsigned CalleeSavedRegs64Bit[] = { 361 X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0 362 }; 363 364 static const unsigned CalleeSavedRegs64EHRet[] = { 365 X86::RAX, X86::RDX, X86::RBX, X86::R12, 366 X86::R13, X86::R14, X86::R15, X86::RBP, 0 367 }; 368 369 static const unsigned CalleeSavedRegsWin64[] = { 370 X86::RBX, X86::RBP, X86::RDI, X86::RSI, 371 X86::R12, X86::R13, X86::R14, X86::R15, 372 X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, 373 X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, 374 X86::XMM14, X86::XMM15, 0 375 }; 376 377 if (ghcCall) { 378 return GhcCalleeSavedRegs; 379 } else if (Is64Bit) { 380 if (IsWin64) 381 return CalleeSavedRegsWin64; 382 else 383 return (callsEHReturn ? CalleeSavedRegs64EHRet : CalleeSavedRegs64Bit); 384 } else { 385 return (callsEHReturn ? CalleeSavedRegs32EHRet : CalleeSavedRegs32Bit); 386 } 387 } 388 389 BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const { 390 BitVector Reserved(getNumRegs()); 391 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 392 393 // Set the stack-pointer register and its aliases as reserved. 394 Reserved.set(X86::RSP); 395 Reserved.set(X86::ESP); 396 Reserved.set(X86::SP); 397 Reserved.set(X86::SPL); 398 399 // Set the instruction pointer register and its aliases as reserved. 400 Reserved.set(X86::RIP); 401 Reserved.set(X86::EIP); 402 Reserved.set(X86::IP); 403 404 // Set the frame-pointer register and its aliases as reserved if needed. 405 if (TFI->hasFP(MF)) { 406 Reserved.set(X86::RBP); 407 Reserved.set(X86::EBP); 408 Reserved.set(X86::BP); 409 Reserved.set(X86::BPL); 410 } 411 412 // Mark the segment registers as reserved. 413 Reserved.set(X86::CS); 414 Reserved.set(X86::SS); 415 Reserved.set(X86::DS); 416 Reserved.set(X86::ES); 417 Reserved.set(X86::FS); 418 Reserved.set(X86::GS); 419 420 // Reserve the registers that only exist in 64-bit mode. 421 if (!Is64Bit) { 422 // These 8-bit registers are part of the x86-64 extension even though their 423 // super-registers are old 32-bits. 424 Reserved.set(X86::SIL); 425 Reserved.set(X86::DIL); 426 Reserved.set(X86::BPL); 427 Reserved.set(X86::SPL); 428 429 for (unsigned n = 0; n != 8; ++n) { 430 // R8, R9, ... 431 const unsigned GPR64[] = { 432 X86::R8, X86::R9, X86::R10, X86::R11, 433 X86::R12, X86::R13, X86::R14, X86::R15 434 }; 435 for (const unsigned *AI = getOverlaps(GPR64[n]); unsigned Reg = *AI; ++AI) 436 Reserved.set(Reg); 437 438 // XMM8, XMM9, ... 439 assert(X86::XMM15 == X86::XMM8+7); 440 for (const unsigned *AI = getOverlaps(X86::XMM8 + n); unsigned Reg = *AI; 441 ++AI) 442 Reserved.set(Reg); 443 } 444 } 445 446 return Reserved; 447 } 448 449 //===----------------------------------------------------------------------===// 450 // Stack Frame Processing methods 451 //===----------------------------------------------------------------------===// 452 453 bool X86RegisterInfo::canRealignStack(const MachineFunction &MF) const { 454 const MachineFrameInfo *MFI = MF.getFrameInfo(); 455 return (RealignStack && 456 !MFI->hasVarSizedObjects()); 457 } 458 459 bool X86RegisterInfo::needsStackRealignment(const MachineFunction &MF) const { 460 const MachineFrameInfo *MFI = MF.getFrameInfo(); 461 const Function *F = MF.getFunction(); 462 unsigned StackAlign = TM.getFrameLowering()->getStackAlignment(); 463 bool requiresRealignment = ((MFI->getMaxAlignment() > StackAlign) || 464 F->hasFnAttr(Attribute::StackAlignment)); 465 466 // FIXME: Currently we don't support stack realignment for functions with 467 // variable-sized allocas. 468 // FIXME: It's more complicated than this... 469 if (0 && requiresRealignment && MFI->hasVarSizedObjects()) 470 report_fatal_error( 471 "Stack realignment in presence of dynamic allocas is not supported"); 472 473 // If we've requested that we force align the stack do so now. 474 if (ForceStackAlign) 475 return canRealignStack(MF); 476 477 return requiresRealignment && canRealignStack(MF); 478 } 479 480 bool X86RegisterInfo::hasReservedSpillSlot(const MachineFunction &MF, 481 unsigned Reg, int &FrameIdx) const { 482 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 483 484 if (Reg == FramePtr && TFI->hasFP(MF)) { 485 FrameIdx = MF.getFrameInfo()->getObjectIndexBegin(); 486 return true; 487 } 488 return false; 489 } 490 491 static unsigned getSUBriOpcode(unsigned is64Bit, int64_t Imm) { 492 if (is64Bit) { 493 if (isInt<8>(Imm)) 494 return X86::SUB64ri8; 495 return X86::SUB64ri32; 496 } else { 497 if (isInt<8>(Imm)) 498 return X86::SUB32ri8; 499 return X86::SUB32ri; 500 } 501 } 502 503 static unsigned getADDriOpcode(unsigned is64Bit, int64_t Imm) { 504 if (is64Bit) { 505 if (isInt<8>(Imm)) 506 return X86::ADD64ri8; 507 return X86::ADD64ri32; 508 } else { 509 if (isInt<8>(Imm)) 510 return X86::ADD32ri8; 511 return X86::ADD32ri; 512 } 513 } 514 515 void X86RegisterInfo:: 516 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, 517 MachineBasicBlock::iterator I) const { 518 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 519 bool reseveCallFrame = TFI->hasReservedCallFrame(MF); 520 int Opcode = I->getOpcode(); 521 bool isDestroy = Opcode == TII.getCallFrameDestroyOpcode(); 522 DebugLoc DL = I->getDebugLoc(); 523 uint64_t Amount = !reseveCallFrame ? I->getOperand(0).getImm() : 0; 524 uint64_t CalleeAmt = isDestroy ? I->getOperand(1).getImm() : 0; 525 I = MBB.erase(I); 526 527 if (!reseveCallFrame) { 528 // If the stack pointer can be changed after prologue, turn the 529 // adjcallstackup instruction into a 'sub ESP, <amt>' and the 530 // adjcallstackdown instruction into 'add ESP, <amt>' 531 // TODO: consider using push / pop instead of sub + store / add 532 if (Amount == 0) 533 return; 534 535 // We need to keep the stack aligned properly. To do this, we round the 536 // amount of space needed for the outgoing arguments up to the next 537 // alignment boundary. 538 unsigned StackAlign = TM.getFrameLowering()->getStackAlignment(); 539 Amount = (Amount + StackAlign - 1) / StackAlign * StackAlign; 540 541 MachineInstr *New = 0; 542 if (Opcode == TII.getCallFrameSetupOpcode()) { 543 New = BuildMI(MF, DL, TII.get(getSUBriOpcode(Is64Bit, Amount)), 544 StackPtr) 545 .addReg(StackPtr) 546 .addImm(Amount); 547 } else { 548 assert(Opcode == TII.getCallFrameDestroyOpcode()); 549 550 // Factor out the amount the callee already popped. 551 Amount -= CalleeAmt; 552 553 if (Amount) { 554 unsigned Opc = getADDriOpcode(Is64Bit, Amount); 555 New = BuildMI(MF, DL, TII.get(Opc), StackPtr) 556 .addReg(StackPtr).addImm(Amount); 557 } 558 } 559 560 if (New) { 561 // The EFLAGS implicit def is dead. 562 New->getOperand(3).setIsDead(); 563 564 // Replace the pseudo instruction with a new instruction. 565 MBB.insert(I, New); 566 } 567 568 return; 569 } 570 571 if (Opcode == TII.getCallFrameDestroyOpcode() && CalleeAmt) { 572 // If we are performing frame pointer elimination and if the callee pops 573 // something off the stack pointer, add it back. We do this until we have 574 // more advanced stack pointer tracking ability. 575 unsigned Opc = getSUBriOpcode(Is64Bit, CalleeAmt); 576 MachineInstr *New = BuildMI(MF, DL, TII.get(Opc), StackPtr) 577 .addReg(StackPtr).addImm(CalleeAmt); 578 579 // The EFLAGS implicit def is dead. 580 New->getOperand(3).setIsDead(); 581 582 // We are not tracking the stack pointer adjustment by the callee, so make 583 // sure we restore the stack pointer immediately after the call, there may 584 // be spill code inserted between the CALL and ADJCALLSTACKUP instructions. 585 MachineBasicBlock::iterator B = MBB.begin(); 586 while (I != B && !llvm::prior(I)->getDesc().isCall()) 587 --I; 588 MBB.insert(I, New); 589 } 590 } 591 592 void 593 X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, 594 int SPAdj, RegScavenger *RS) const{ 595 assert(SPAdj == 0 && "Unexpected"); 596 597 unsigned i = 0; 598 MachineInstr &MI = *II; 599 MachineFunction &MF = *MI.getParent()->getParent(); 600 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 601 602 while (!MI.getOperand(i).isFI()) { 603 ++i; 604 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!"); 605 } 606 607 int FrameIndex = MI.getOperand(i).getIndex(); 608 unsigned BasePtr; 609 610 unsigned Opc = MI.getOpcode(); 611 bool AfterFPPop = Opc == X86::TAILJMPm64 || Opc == X86::TAILJMPm; 612 if (needsStackRealignment(MF)) 613 BasePtr = (FrameIndex < 0 ? FramePtr : StackPtr); 614 else if (AfterFPPop) 615 BasePtr = StackPtr; 616 else 617 BasePtr = (TFI->hasFP(MF) ? FramePtr : StackPtr); 618 619 // This must be part of a four operand memory reference. Replace the 620 // FrameIndex with base register with EBP. Add an offset to the offset. 621 MI.getOperand(i).ChangeToRegister(BasePtr, false); 622 623 // Now add the frame object offset to the offset from EBP. 624 int FIOffset; 625 if (AfterFPPop) { 626 // Tail call jmp happens after FP is popped. 627 const MachineFrameInfo *MFI = MF.getFrameInfo(); 628 FIOffset = MFI->getObjectOffset(FrameIndex) - TFI->getOffsetOfLocalArea(); 629 } else 630 FIOffset = TFI->getFrameIndexOffset(MF, FrameIndex); 631 632 if (MI.getOperand(i+3).isImm()) { 633 // Offset is a 32-bit integer. 634 int Imm = (int)(MI.getOperand(i + 3).getImm()); 635 int Offset = FIOffset + Imm; 636 assert((!Is64Bit || isInt<32>((long long)FIOffset + Imm)) && 637 "Requesting 64-bit offset in 32-bit immediate!"); 638 MI.getOperand(i + 3).ChangeToImmediate(Offset); 639 } else { 640 // Offset is symbolic. This is extremely rare. 641 uint64_t Offset = FIOffset + (uint64_t)MI.getOperand(i+3).getOffset(); 642 MI.getOperand(i+3).setOffset(Offset); 643 } 644 } 645 646 unsigned X86RegisterInfo::getFrameRegister(const MachineFunction &MF) const { 647 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 648 return TFI->hasFP(MF) ? FramePtr : StackPtr; 649 } 650 651 unsigned X86RegisterInfo::getEHExceptionRegister() const { 652 llvm_unreachable("What is the exception register"); 653 return 0; 654 } 655 656 unsigned X86RegisterInfo::getEHHandlerRegister() const { 657 llvm_unreachable("What is the exception handler register"); 658 return 0; 659 } 660 661 namespace llvm { 662 unsigned getX86SubSuperRegister(unsigned Reg, EVT VT, bool High) { 663 switch (VT.getSimpleVT().SimpleTy) { 664 default: return Reg; 665 case MVT::i8: 666 if (High) { 667 switch (Reg) { 668 default: return 0; 669 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: 670 return X86::AH; 671 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX: 672 return X86::DH; 673 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX: 674 return X86::CH; 675 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: 676 return X86::BH; 677 } 678 } else { 679 switch (Reg) { 680 default: return 0; 681 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: 682 return X86::AL; 683 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX: 684 return X86::DL; 685 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX: 686 return X86::CL; 687 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: 688 return X86::BL; 689 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI: 690 return X86::SIL; 691 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI: 692 return X86::DIL; 693 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP: 694 return X86::BPL; 695 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP: 696 return X86::SPL; 697 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8: 698 return X86::R8B; 699 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9: 700 return X86::R9B; 701 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10: 702 return X86::R10B; 703 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11: 704 return X86::R11B; 705 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12: 706 return X86::R12B; 707 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13: 708 return X86::R13B; 709 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14: 710 return X86::R14B; 711 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15: 712 return X86::R15B; 713 } 714 } 715 case MVT::i16: 716 switch (Reg) { 717 default: return Reg; 718 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: 719 return X86::AX; 720 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX: 721 return X86::DX; 722 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX: 723 return X86::CX; 724 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: 725 return X86::BX; 726 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI: 727 return X86::SI; 728 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI: 729 return X86::DI; 730 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP: 731 return X86::BP; 732 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP: 733 return X86::SP; 734 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8: 735 return X86::R8W; 736 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9: 737 return X86::R9W; 738 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10: 739 return X86::R10W; 740 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11: 741 return X86::R11W; 742 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12: 743 return X86::R12W; 744 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13: 745 return X86::R13W; 746 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14: 747 return X86::R14W; 748 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15: 749 return X86::R15W; 750 } 751 case MVT::i32: 752 switch (Reg) { 753 default: return Reg; 754 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: 755 return X86::EAX; 756 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX: 757 return X86::EDX; 758 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX: 759 return X86::ECX; 760 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: 761 return X86::EBX; 762 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI: 763 return X86::ESI; 764 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI: 765 return X86::EDI; 766 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP: 767 return X86::EBP; 768 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP: 769 return X86::ESP; 770 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8: 771 return X86::R8D; 772 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9: 773 return X86::R9D; 774 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10: 775 return X86::R10D; 776 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11: 777 return X86::R11D; 778 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12: 779 return X86::R12D; 780 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13: 781 return X86::R13D; 782 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14: 783 return X86::R14D; 784 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15: 785 return X86::R15D; 786 } 787 case MVT::i64: 788 switch (Reg) { 789 default: return Reg; 790 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: 791 return X86::RAX; 792 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX: 793 return X86::RDX; 794 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX: 795 return X86::RCX; 796 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX: 797 return X86::RBX; 798 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI: 799 return X86::RSI; 800 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI: 801 return X86::RDI; 802 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP: 803 return X86::RBP; 804 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP: 805 return X86::RSP; 806 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8: 807 return X86::R8; 808 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9: 809 return X86::R9; 810 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10: 811 return X86::R10; 812 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11: 813 return X86::R11; 814 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12: 815 return X86::R12; 816 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13: 817 return X86::R13; 818 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14: 819 return X86::R14; 820 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15: 821 return X86::R15; 822 } 823 } 824 825 return Reg; 826 } 827 } 828 829 namespace { 830 struct MSAH : public MachineFunctionPass { 831 static char ID; 832 MSAH() : MachineFunctionPass(ID) {} 833 834 virtual bool runOnMachineFunction(MachineFunction &MF) { 835 const X86TargetMachine *TM = 836 static_cast<const X86TargetMachine *>(&MF.getTarget()); 837 const TargetFrameLowering *TFI = TM->getFrameLowering(); 838 MachineRegisterInfo &RI = MF.getRegInfo(); 839 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 840 unsigned StackAlignment = TFI->getStackAlignment(); 841 842 // Be over-conservative: scan over all vreg defs and find whether vector 843 // registers are used. If yes, there is a possibility that vector register 844 // will be spilled and thus require dynamic stack realignment. 845 for (unsigned i = 0, e = RI.getNumVirtRegs(); i != e; ++i) { 846 unsigned Reg = TargetRegisterInfo::index2VirtReg(i); 847 if (RI.getRegClass(Reg)->getAlignment() > StackAlignment) { 848 FuncInfo->setForceFramePointer(true); 849 return true; 850 } 851 } 852 // Nothing to do 853 return false; 854 } 855 856 virtual const char *getPassName() const { 857 return "X86 Maximal Stack Alignment Check"; 858 } 859 860 virtual void getAnalysisUsage(AnalysisUsage &AU) const { 861 AU.setPreservesCFG(); 862 MachineFunctionPass::getAnalysisUsage(AU); 863 } 864 }; 865 866 char MSAH::ID = 0; 867 } 868 869 FunctionPass* 870 llvm::createX86MaxStackAlignmentHeuristicPass() { return new MSAH(); } 871
