1 //===- AlphaInstrInfo.h - Alpha Instruction Information ---------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the Alpha implementation of the TargetInstrInfo class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef ALPHAINSTRUCTIONINFO_H 15 #define ALPHAINSTRUCTIONINFO_H 16 17 #include "llvm/Target/TargetInstrInfo.h" 18 #include "AlphaRegisterInfo.h" 19 20 #define GET_INSTRINFO_HEADER 21 #include "AlphaGenInstrInfo.inc" 22 23 namespace llvm { 24 25 class AlphaInstrInfo : public AlphaGenInstrInfo { 26 const AlphaRegisterInfo RI; 27 public: 28 AlphaInstrInfo(); 29 30 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As 31 /// such, whenever a client has an instance of instruction info, it should 32 /// always be able to get register info as well (through this method). 33 /// 34 virtual const AlphaRegisterInfo &getRegisterInfo() const { return RI; } 35 36 virtual unsigned isLoadFromStackSlot(const MachineInstr *MI, 37 int &FrameIndex) const; 38 virtual unsigned isStoreToStackSlot(const MachineInstr *MI, 39 int &FrameIndex) const; 40 41 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 42 MachineBasicBlock *FBB, 43 const SmallVectorImpl<MachineOperand> &Cond, 44 DebugLoc DL) const; 45 virtual void copyPhysReg(MachineBasicBlock &MBB, 46 MachineBasicBlock::iterator MI, DebugLoc DL, 47 unsigned DestReg, unsigned SrcReg, 48 bool KillSrc) const; 49 virtual void storeRegToStackSlot(MachineBasicBlock &MBB, 50 MachineBasicBlock::iterator MBBI, 51 unsigned SrcReg, bool isKill, int FrameIndex, 52 const TargetRegisterClass *RC, 53 const TargetRegisterInfo *TRI) const; 54 55 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB, 56 MachineBasicBlock::iterator MBBI, 57 unsigned DestReg, int FrameIndex, 58 const TargetRegisterClass *RC, 59 const TargetRegisterInfo *TRI) const; 60 61 bool AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB, 62 MachineBasicBlock *&FBB, 63 SmallVectorImpl<MachineOperand> &Cond, 64 bool AllowModify) const; 65 unsigned RemoveBranch(MachineBasicBlock &MBB) const; 66 void insertNoop(MachineBasicBlock &MBB, 67 MachineBasicBlock::iterator MI) const; 68 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const; 69 70 /// getGlobalBaseReg - Return a virtual register initialized with the 71 /// the global base register value. Output instructions required to 72 /// initialize the register in the function entry block, if necessary. 73 /// 74 unsigned getGlobalBaseReg(MachineFunction *MF) const; 75 76 /// getGlobalRetAddr - Return a virtual register initialized with the 77 /// the global return address register value. Output instructions required to 78 /// initialize the register in the function entry block, if necessary. 79 /// 80 unsigned getGlobalRetAddr(MachineFunction *MF) const; 81 }; 82 83 } 84 85 #endif 86
