| /external/llvm/lib/Target/ARM/ |
| ARMSelectionDAGInfo.h | 22 namespace ARM_AM {
25 default: return ARM_AM::no_shift;
26 case ISD::SHL: return ARM_AM::lsl;
27 case ISD::SRL: return ARM_AM::lsr;
28 case ISD::SRA: return ARM_AM::asr;
29 case ISD::ROTR: return ARM_AM::ror;
33 //case ARMISD::RRX: return ARM_AM::rrx;
36 } // end namespace ARM_AM
|
| ARMLoadStoreOptimizer.cpp | 132 static int getLoadStoreMultipleOpcode(int Opcode, ARM_AM::AMSubMode Mode) {
139 case ARM_AM::ia: return ARM::LDMIA;
140 case ARM_AM::da: return ARM::LDMDA;
141 case ARM_AM::db: return ARM::LDMDB;
142 case ARM_AM::ib: return ARM::LDMIB;
149 case ARM_AM::ia: return ARM::STMIA;
150 case ARM_AM::da: return ARM::STMDA;
151 case ARM_AM::db: return ARM::STMDB;
152 case ARM_AM::ib: return ARM::STMIB;
160 case ARM_AM::ia: return ARM::t2LDMIA
[all...] |
| ARMISelDAGToDAG.cpp | 97 ARM_AM::ShiftOpc ShOpcVal, unsigned ShAmt);
184 return ARM_AM::getSOImmVal(Imm) != -1;
188 return ARM_AM::getSOImmVal(~Imm) != -1;
192 return ARM_AM::getT2SOImmVal(Imm) != -1;
196 return ARM_AM::getT2SOImmVal(~Imm) != -1;
380 ARM_AM::ShiftOpc ShOpcVal,
387 return ShOpcVal == ARM_AM::lsl && ShAmt == 2;
397 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOpcode());
401 if (ShOpcVal == ARM_AM::no_shift) return false
[all...] |
| ARMCodeEmitter.cpp | 321 if (uint32_t ImmOffs = ARM_AM::getAM5Offset(MO1.getImm())) {
322 if (ARM_AM::getAM5Op(MO1.getImm()) == ARM_AM::add)
416 switch (ARM_AM::getAM2ShiftOpc(Imm)) {
418 case ARM_AM::asr: return 2;
419 case ARM_AM::lsl: return 0;
420 case ARM_AM::lsr: return 1;
421 case ARM_AM::ror:
422 case ARM_AM::rrx: return 3;
770 assert(MO1.isImm() && ARM_AM::isSOImmTwoPartVal(MO1.getImm()) &
[all...] |
| Thumb2InstrInfo.cpp | 186 ARM_AM::getT2SOImmVal(NumBytes) == -1) {
246 if (ARM_AM::getT2SOImmVal(NumBytes) != -1) {
251 ThisVal = ThisVal & ARM_AM::rotr32(0xff000000U, RotAmt);
253 assert(ARM_AM::getT2SOImmVal(ThisVal) != -1 &&
259 if (ARM_AM::getT2SOImmVal(NumBytes) != -1) {
268 ThisVal = ThisVal & ARM_AM::rotr32(0xff000000U, RotAmt);
270 assert(ARM_AM::getT2SOImmVal(ThisVal) != -1 &&
424 if (ARM_AM::getT2SOImmVal(Offset) != -1) {
450 unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xff000000U, RotAmt);
455 assert(ARM_AM::getT2SOImmVal(ThisImmVal) != -1 &
[all...] |
| ARMJITInfo.cpp | 312 int SoImmVal = ARM_AM::getSOImmVal(ResultPtr);
314 *((intptr_t*)RelocPos) |= (ARM_AM::getSOImmValRot((unsigned)SoImmVal) >> 1)
316 *((intptr_t*)RelocPos) |= ARM_AM::getSOImmValImm((unsigned)SoImmVal);
|
| ARMBaseInstrInfo.cpp | 164 bool isSub = ARM_AM::getAM2Op(OffImm) == ARM_AM::sub;
165 unsigned Amt = ARM_AM::getAM2Offset(OffImm);
167 if (ARM_AM::getSOImmVal(Amt) == -1)
176 ARM_AM::ShiftOpc ShOpc = ARM_AM::getAM2ShiftOpc(OffImm);
177 unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt);
190 bool isSub = ARM_AM::getAM3Op(OffImm) == ARM_AM::sub;
191 unsigned Amt = ARM_AM::getAM3Offset(OffImm)
[all...] |
| ARMBaseRegisterInfo.cpp | 892 InstrOffs = ARM_AM::getAM5Offset(OffOp.getImm());
893 if (ARM_AM::getAM5Op(OffOp.getImm()) == ARM_AM::sub)
900 InstrOffs = ARM_AM::getAM2Offset(MI->getOperand(ImmIdx).getImm());
901 if (ARM_AM::getAM2Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub)
907 InstrOffs = ARM_AM::getAM3Offset(MI->getOperand(ImmIdx).getImm());
908 if (ARM_AM::getAM3Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub)
[all...] |
| ARMExpandPseudoInsts.cpp | 665 unsigned SOImmValV1 = ARM_AM::getSOImmTwoPartFirst(ImmVal);
666 unsigned SOImmValV2 = ARM_AM::getSOImmTwoPartSecond(ImmVal);
[all...] |
| ARMFrameLowering.cpp | 670 MIB.addImm(ARM_AM::getAM2Opc(ARM_AM::add, 4, ARM_AM::no_shift));
[all...] |
| ARMISelLowering.cpp | [all...] |
| ARMFastISel.cpp | 508 Imm = ARM_AM::getFP64Imm(Val);
511 Imm = ARM_AM::getFP32Imm(Val);
[all...] |
| /external/llvm/lib/Target/ARM/InstPrinter/ |
| ARMInstPrinter.cpp | 65 O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO3.getImm()));
73 assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
84 O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO2.getImm()));
91 if (ARM_AM::getSORegShOp(MO2.getImm()) == ARM_AM::rrx) {
96 O << ", #" << translateShiftImm(ARM_AM::getSORegOffset(MO2.getImm()));
249 ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO3.getImm())
[all...] |
| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| ARMMCCodeEmitter.cpp | 167 ARM_AM::AMSubMode Mode = (ARM_AM::AMSubMode)MI.getOperand(OpIdx).getImm();
170 case ARM_AM::da: return 0;
171 case ARM_AM::ia: return 1;
172 case ARM_AM::db: return 2;
173 case ARM_AM::ib: return 3;
178 unsigned getShiftOp(ARM_AM::ShiftOpc ShOpc) const {
181 case ARM_AM::no_shift:
182 case ARM_AM::lsl: return 0;
183 case ARM_AM::lsr: return 1
[all...] |
| ARMAddressingModes.h | 24 /// ARM_AM - ARM Addressing Mode Stuff
25 namespace ARM_AM {
47 case ARM_AM::asr: return "asr";
48 case ARM_AM::lsl: return "lsl";
49 case ARM_AM::lsr: return "lsr";
50 case ARM_AM::ror: return "ror";
51 case ARM_AM::rrx: return "rrx";
58 case ARM_AM::asr: return 2;
59 case ARM_AM::lsl: return 0;
60 case ARM_AM::lsr: return 1
[all...] |
| ARMAsmBackend.cpp | 246 assert(ARM_AM::getSOImmVal(Value) != -1 &&
249 return ARM_AM::getSOImmVal(Value) | (opc << 21);
|
| /external/llvm/lib/Target/ARM/AsmParser/ |
| ARMAsmParser.cpp | 90 bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType,
341 ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg
351 ARM_AM::ShiftOpc ShiftTy;
360 ARM_AM::ShiftOpc ShiftTy;
366 ARM_AM::ShiftOpc ShiftTy;
654 return ARM_AM::getSOImmVal(Value) != -1;
662 return ARM_AM::getT2SOImmVal(Value) != -1;
686 return Kind == k_PostIndexRegister && PostIdxReg.ShiftTy == ARM_AM::no_shift;
719 if (Memory.ShiftType != ARM_AM::no_shift) return false;
731 return PostIdxReg.ShiftTy == ARM_AM::no_shift
[all...] |
| /external/llvm/lib/Target/ARM/Disassembler/ |
| ARMDisassembler.cpp | [all...] |
