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    Searched refs:CondCodes (Results 1 - 25 of 35) sorted by null

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  /external/llvm/lib/Target/MSP430/
MSP430.h 23 enum CondCodes {
MSP430InstrInfo.cpp 133 MSP430CC::CondCodes CC = static_cast<MSP430CC::CondCodes>(Cond[0].getImm());
231 MSP430CC::CondCodes BranchCode =
232 static_cast<MSP430CC::CondCodes>(I->getOperand(1).getImm());
254 MSP430CC::CondCodes OldBranchCode = (MSP430CC::CondCodes)Cond[0].getImm();
  /external/llvm/lib/Target/SystemZ/
SystemZ.h 29 enum CondCodes {
SystemZInstrInfo.h 98 SystemZCC::CondCodes getOppositeCondition(SystemZCC::CondCodes CC) const;
99 SystemZCC::CondCodes getCondFromBranchOpc(unsigned Opc) const;
100 const MCInstrDesc& getBrCond(SystemZCC::CondCodes CC) const;
SystemZInstrInfo.cpp 200 SystemZCC::CondCodes CC = static_cast<SystemZCC::CondCodes>(Cond[0].getImm());
266 SystemZCC::CondCodes BranchCode = getCondFromBranchOpc(I->getOpcode());
288 SystemZCC::CondCodes OldBranchCode = (SystemZCC::CondCodes)Cond[0].getImm();
338 SystemZCC::CondCodes CC = (SystemZCC::CondCodes)Cond[0].getImm();
351 SystemZInstrInfo::getBrCond(SystemZCC::CondCodes CC) const {
372 SystemZCC::CondCodes
393 SystemZCC::CondCodes
    [all...]
SystemZISelLowering.cpp 615 SystemZCC::CondCodes TCC;
834 SystemZCC::CondCodes CC = (SystemZCC::CondCodes)MI->getOperand(3).getImm();
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  /external/llvm/lib/Target/ARM/
Thumb2RegisterInfo.h 37 ARMCC::CondCodes Pred = ARMCC::AL,
Thumb2ITBlockPass.cpp 44 ARMCC::CondCodes CC, ARMCC::CondCodes OCC,
108 ARMCC::CondCodes CC, ARMCC::CondCodes OCC,
156 ARMCC::CondCodes NCC = llvm::getITInstrPredicate(I, NPredReg);
173 ARMCC::CondCodes CC = llvm::getITInstrPredicate(MI, PredReg);
196 ARMCC::CondCodes OCC = ARMCC::getOppositeCondition(CC);
209 ARMCC::CondCodes NCC = llvm::getITInstrPredicate(NMI, NPredReg);
Thumb2InstrInfo.h 73 ARMCC::CondCodes getITInstrPredicate(const MachineInstr *MI, unsigned &PredReg);
Thumb2RegisterInfo.cpp 40 ARMCC::CondCodes Pred, unsigned PredReg,
Thumb1RegisterInfo.h 42 ARMCC::CondCodes Pred = ARMCC::AL,
ARMBaseInstrInfo.h 77 ARMCC::CondCodes getPredicate(const MachineInstr *MI) const {
79 return PIdx != -1 ? (ARMCC::CondCodes)MI->getOperand(PIdx).getImm()
338 ARMCC::CondCodes getInstrPredicate(const MachineInstr *MI, unsigned &PredReg);
354 ARMCC::CondCodes Pred, unsigned PredReg,
360 ARMCC::CondCodes Pred, unsigned PredReg,
Thumb2InstrInfo.cpp 56 ARMCC::CondCodes CC = llvm::getInstrPredicate(Tail, PredReg);
177 ARMCC::CondCodes Pred, unsigned PredReg,
573 ARMCC::CondCodes CC = llvm::getInstrPredicate(UseMI, PredReg);
580 ARMCC::CondCodes OCC = ARMCC::getOppositeCondition(CC);
589 ARMCC::CondCodes NCC = llvm::getInstrPredicate(NMI, PredReg);
605 ARMCC::CondCodes
ARMLoadStoreOptimizer.cpp 92 ARMCC::CondCodes Pred, unsigned PredReg, unsigned Scratch,
103 ARMCC::CondCodes Pred,
110 ARMCC::CondCodes Pred, unsigned PredReg,
292 int Opcode, ARMCC::CondCodes Pred,
373 ARMCC::CondCodes Pred, unsigned PredReg,
440 ARMCC::CondCodes Pred, unsigned PredReg,
511 ARMCC::CondCodes Pred, unsigned PredReg){
534 ARMCC::CondCodes Pred, unsigned PredReg){
689 ARMCC::CondCodes Pred = llvm::getInstrPredicate(MI, PredReg);
844 ARMCC::CondCodes Pred = llvm::getInstrPredicate(MI, PredReg)
    [all...]
ARMBaseRegisterInfo.h 173 ARMCC::CondCodes Pred = ARMCC::AL,
MLxExpansionPass.cpp 218 ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NextOp).getImm();
ARMBaseRegisterInfo.cpp 787 ARMCC::CondCodes Pred,
822 ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0) {
858 ARMCC::CondCodes Pred = (PIdx == -1)
859 ? ARMCC::AL : (ARMCC::CondCodes)Old->getOperand(PIdx).getImm();
    [all...]
Thumb2SizeReduction.cpp 152 bool is2Addr, ARMCC::CondCodes Pred,
243 bool is2Addr, ARMCC::CondCodes Pred,
615 ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg);
706 ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg);
ARMBaseInstrInfo.cpp 158 ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NumOps-1).getImm();
438 ARMCC::CondCodes CC = (ARMCC::CondCodes)(int)Cond[0].getImm();
470 ARMCC::CondCodes CC1 = (ARMCC::CondCodes)Pred1[0].getImm();
471 ARMCC::CondCodes CC2 = (ARMCC::CondCodes)Pred2[0].getImm();
    [all...]
ARMISelDAGToDAG.cpp 248 ARMCC::CondCodes CCVal, SDValue CCR,
251 ARMCC::CondCodes CCVal, SDValue CCR,
254 ARMCC::CondCodes CCVal, SDValue CCR,
257 ARMCC::CondCodes CCVal, SDValue CCR,
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  /external/llvm/lib/Target/Sparc/
Sparc.h 38 enum CondCodes {
75 inline static const char *SPARCCondCodeToString(SPCC::CondCodes CC) {
SparcInstrInfo.cpp 79 static SPCC::CondCodes GetOppositeBranchCondition(SPCC::CondCodes CC)
170 SPCC::CondCodes BranchCode = (SPCC::CondCodes)I->getOperand(1).getImm();
SparcAsmPrinter.cpp 176 O << SPARCCondCodeToString((SPCC::CondCodes)CC);
  /external/llvm/lib/Target/ARM/MCTargetDesc/
ARMBaseInfo.h 27 // The CondCodes constants map directly to the 4-bit encoding of the
29 enum CondCodes { // Meaning (integer) Meaning (floating-point)
47 inline static CondCodes getOppositeCondition(CondCodes CC) {
68 inline static const char *ARMCondCodeToString(ARMCC::CondCodes CC) {
  /external/llvm/lib/Target/ARM/InstPrinter/
ARMInstPrinter.cpp 686 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
694 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();

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