1 //===- Thumb2InstrInfo.h - Thumb-2 Instruction Information ------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the Thumb-2 implementation of the TargetInstrInfo class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef THUMB2INSTRUCTIONINFO_H 15 #define THUMB2INSTRUCTIONINFO_H 16 17 #include "llvm/Target/TargetInstrInfo.h" 18 #include "ARM.h" 19 #include "ARMInstrInfo.h" 20 #include "Thumb2RegisterInfo.h" 21 22 namespace llvm { 23 class ARMSubtarget; 24 class ScheduleHazardRecognizer; 25 26 class Thumb2InstrInfo : public ARMBaseInstrInfo { 27 Thumb2RegisterInfo RI; 28 public: 29 explicit Thumb2InstrInfo(const ARMSubtarget &STI); 30 31 // Return the non-pre/post incrementing version of 'Opc'. Return 0 32 // if there is not such an opcode. 33 unsigned getUnindexedOpcode(unsigned Opc) const; 34 35 void ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail, 36 MachineBasicBlock *NewDest) const; 37 38 bool isLegalToSplitMBBAt(MachineBasicBlock &MBB, 39 MachineBasicBlock::iterator MBBI) const; 40 41 void copyPhysReg(MachineBasicBlock &MBB, 42 MachineBasicBlock::iterator I, DebugLoc DL, 43 unsigned DestReg, unsigned SrcReg, 44 bool KillSrc) const; 45 46 void storeRegToStackSlot(MachineBasicBlock &MBB, 47 MachineBasicBlock::iterator MBBI, 48 unsigned SrcReg, bool isKill, int FrameIndex, 49 const TargetRegisterClass *RC, 50 const TargetRegisterInfo *TRI) const; 51 52 void loadRegFromStackSlot(MachineBasicBlock &MBB, 53 MachineBasicBlock::iterator MBBI, 54 unsigned DestReg, int FrameIndex, 55 const TargetRegisterClass *RC, 56 const TargetRegisterInfo *TRI) const; 57 58 /// scheduleTwoAddrSource - Schedule the copy / re-mat of the source of the 59 /// two-addrss instruction inserted by two-address pass. 60 void scheduleTwoAddrSource(MachineInstr *SrcMI, MachineInstr *UseMI, 61 const TargetRegisterInfo &TRI) const; 62 63 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As 64 /// such, whenever a client has an instance of instruction info, it should 65 /// always be able to get register info as well (through this method). 66 /// 67 const Thumb2RegisterInfo &getRegisterInfo() const { return RI; } 68 }; 69 70 /// getITInstrPredicate - Valid only in Thumb2 mode. This function is identical 71 /// to llvm::getInstrPredicate except it returns AL for conditional branch 72 /// instructions which are "predicated", but are not in IT blocks. 73 ARMCC::CondCodes getITInstrPredicate(const MachineInstr *MI, unsigned &PredReg); 74 75 76 } 77 78 #endif // THUMB2INSTRUCTIONINFO_H 79
