| /external/llvm/include/llvm/Target/ |
| TargetOpcodes.h | 47 /// defined by an IMPLICIT_DEF, because it is commonly used to implement
51 /// IMPLICIT_DEF - This is the MachineInstr-level equivalent of undef.
52 IMPLICIT_DEF = 8,
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| TargetInstrInfo.h | 66 return MI->getOpcode() == TargetOpcode::IMPLICIT_DEF ||
[all...] |
| /external/llvm/lib/CodeGen/ |
| MachineSSAUpdater.cpp | 108 /// InsertNewDef - Insert an empty PHI or IMPLICIT_DEF instruction which define
148 // Insert an implicit_def to represent an undef value.
149 MachineInstr *NewDef = InsertNewDef(TargetOpcode::IMPLICIT_DEF,
298 /// GetUndefVal - Create an IMPLICIT_DEF instruction with a new register.
302 // Insert an implicit_def to represent an undef value.
303 MachineInstr *NewDef = InsertNewDef(TargetOpcode::IMPLICIT_DEF,
|
| ProcessImplicitDefs.cpp | 76 /// processImplicitDefs - Process IMPLICIT_DEF instructions and make sure
77 /// there is one implicit_def for each use. Add isUndef marker to
78 /// implicit_def defs and their uses.
150 // Use is a copy, just turn it into an implicit_def.
153 MI->setDesc(TII->get(TargetOpcode::IMPLICIT_DEF));
186 // Backtrack to process this new implicit_def.
198 // Any outstanding liveout implicit_def's?
204 // Delete all "local" implicit_def's. That include those which define
212 // is not an implicit_def, do not insert implicit_def's before th
[all...] |
| PHIElimination.cpp | 80 // Defs of PHI sources which are implicit_def.
131 // Remove dead IMPLICIT_DEF instructions.
171 /// are implicit_def's.
212 // If all sources of a PHI node are implicit_def, just emit an
213 // implicit_def instead of a copy.
215 TII->get(TargetOpcode::IMPLICIT_DEF), DestReg);
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| TwoAddressInstructionPass.cpp | [all...] |
| VirtRegRewriter.cpp | [all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| InstrEmitter.cpp | 191 assert(Node->getMachineOpcode() != TargetOpcode::IMPLICIT_DEF &&
192 "IMPLICIT_DEF should have been handled as a special case elsewhere!");
249 Op.getMachineOpcode() == TargetOpcode::IMPLICIT_DEF) {
250 // Add an IMPLICIT_DEF instruction before every use.
252 // IMPLICIT_DEF can produce any type of result so its MCInstrDesc
259 TII->get(TargetOpcode::IMPLICIT_DEF), VReg);
681 if (Opc == TargetOpcode::IMPLICIT_DEF)
682 // We want a unique VR for each IMPLICIT_DEF use.
[all...] |
| ScheduleDAGSDNodes.cpp | 74 N->getMachineOpcode() == TargetOpcode::IMPLICIT_DEF))
498 if (POpc == TargetOpcode::IMPLICIT_DEF) {
|
| ScheduleDAGRRList.cpp | [all...] |
| FastISel.cpp | 209 TII.get(TargetOpcode::IMPLICIT_DEF), Reg);
[all...] |
| SelectionDAGISel.cpp | [all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCCodeEmitter.cpp | 124 case TargetOpcode::IMPLICIT_DEF:
|
| /external/llvm/include/llvm/CodeGen/ |
| MachineInstr.h | 272 bool isImplicitDef() const { return getOpcode()==TargetOpcode::IMPLICIT_DEF; }
|
| /external/llvm/lib/Target/MSP430/ |
| MSP430InstrInfo.cpp | 308 case TargetOpcode::IMPLICIT_DEF:
|
| /external/llvm/lib/Target/SystemZ/ |
| SystemZISelDAGToDAG.cpp | 634 SDNode *Tmp = CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,
712 SDNode *Tmp = CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,
|
| /external/llvm/lib/Target/ARM/ |
| ARMISelDAGToDAG.cpp | [all...] |
| ARMCodeEmitter.cpp | [all...] |
| ARMBaseInstrInfo.cpp | 493 // FIXME: This confuses implicit_def with optional CPSR def.
554 case TargetOpcode::IMPLICIT_DEF:
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86CodeEmitter.cpp | 739 case TargetOpcode::IMPLICIT_DEF:
[all...] |
| X86ISelDAGToDAG.cpp | [all...] |
| X86FloatingPoint.cpp | [all...] |
| X86InstrInfo.cpp | [all...] |
| /external/llvm/lib/CodeGen/AsmPrinter/ |
| AsmPrinter.cpp | 705 case TargetOpcode::IMPLICIT_DEF:
[all...] |
