| /frameworks/opt/vcard/tests/src/com/android/vcard/tests/ |
| VCardParserTests.java | 37 private enum Order {
46 private final List<Order> mHistory = new ArrayList<Order>();
47 private final List<Order> mExpectedOrder = new ArrayList<Order>();
49 public MockVCardInterpreter addExpectedOrder(Order order) {
50 mExpectedOrder.add(order);
54 private void inspectOrder(Order order) {
[all...] |
| /external/llvm/lib/CodeGen/ |
| AllocationOrder.cpp | 1 //===-- llvm/CodeGen/AllocationOrder.cpp - Allocation Order ---------------===//
10 // This file implements an allocation order for virtual registers.
12 // The preferred allocation order for a virtual register depends on allocation
43 // The remaining allocation order may depend on the hint.
44 ArrayRef<unsigned> Order =
47 if (Order.empty())
50 // Copy the allocation order with reserved registers removed.
52 unsigned *P = new unsigned[Order.size()];
54 for (unsigned i = 0; i != Order.size(); ++i)
55 if (!RCI.isReserved(Order[i])
[all...] |
| RegisterClassInfo.cpp | 67 /// compute - Compute the preferred allocation order for RC with reserved
69 /// aliases ordered according to the CSR order specified by the target.
76 if (!RCI.Order)
77 RCI.Order.reset(new unsigned[NumRegs]);
83 // allocation order, we can simply use begin/end here.
87 // Remove reserved registers from the allocation order.
94 RCI.Order[N++] = PhysReg;
97 assert (RCI.NumRegs <= NumRegs && "Allocation order larger than regclass");
99 // CSR aliases go after the volatile registers, preserve the target's order.
100 std::copy(CSRAlias.begin(), CSRAlias.end(), &RCI.Order[N])
[all...] |
| RegisterClassInfo.h | 32 OwningArrayPtr<unsigned> Order;
36 return makeArrayRef(Order.get(), NumRegs);
84 /// getOrder - Returns the preferred allocation order for RC. The order
122 /// Allocatable registers may show up in the allocation order of some virtual
|
| RegAllocGreedy.cpp | 418 // Everything is allocated in long->short order. Long ranges that don't fit
445 AllocationOrder &Order,
447 Order.rewind();
449 while ((PhysReg = Order.next()))
452 if (!PhysReg || Order.isHint(PhysReg))
460 if (Order.isHint(Hint)) {
478 unsigned CheapReg = tryEvict(VirtReg, Order, NewVRegs, Cost);
488 /// eviction policy defined by this function together with the allocation order
611 /// @param Order Physregs to try.
614 AllocationOrder &Order,
[all...] |
| ScheduleDAGInstrs.cpp | 265 // Defs are push in the order they are visited and never reordered.
374 ExitSU.addPred(SDep(SU, SDep::Order, Latency,
412 // Chain dependencies used to enforce memory order should have
429 I->second->addPred(SDep(SU, SDep::Order, /*Latency=*/0));
434 I->second[i]->addPred(SDep(SU, SDep::Order, TrueMemOrderLatency));
440 BarrierChain->addPred(SDep(SU, SDep::Order, /*Latency=*/0));
447 AliasChain->addPred(SDep(SU, SDep::Order, /*Latency=*/0));
450 PendingLoads[k]->addPred(SDep(SU, SDep::Order, TrueMemOrderLatency));
453 I->second->addPred(SDep(SU, SDep::Order, /*Latency=*/0));
458 I->second[i]->addPred(SDep(SU, SDep::Order, TrueMemOrderLatency))
[all...] |
| RegAllocLinearScan.cpp | 147 /// handled_ - Intervals are added to the handled_ set in the order of their
612 // physical register or spill an interval (possibly this one) in order to
[all...] |
| AggressiveAntiDepBreaker.cpp | 613 // order. If that register is available, and the corresponding
623 ArrayRef<unsigned> Order = RegClassInfo.getOrder(SuperRC);
624 if (Order.empty()) {
632 RenameOrder.insert(RenameOrderType::value_type(SuperRC, Order.size()));
635 unsigned EndR = ((OrigR == Order.size()) ? 0 : OrigR);
638 if (R == 0) R = Order.size();
640 const unsigned NewSuperReg = Order[R];
[all...] |
| CriticalAntiDepBreaker.cpp | 388 ArrayRef<unsigned> Order = RegClassInfo.getOrder(RC);
389 for (unsigned i = 0; i != Order.size(); ++i) {
390 unsigned NewReg = Order[i];
525 // the anti-dependencies in an instruction in order to be effective.
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| SDNodeDbgValue.h | 50 unsigned Order;
55 unsigned O) : mdPtr(mdP), Offset(off), DL(dl), Order(O),
65 mdPtr(mdP), Offset(off), DL(dl), Order(O), Invalid(false) {
72 mdPtr(mdP), Offset(off), DL(dl), Order(O), Invalid(false) {
101 // Returns the SDNodeOrder. This is the order of the preceding node in the
103 unsigned getOrder() { return Order; }
|
| ScheduleDAGSDNodes.cpp | 169 /// outputs to ensure they are scheduled together and in order. This
209 // Sort them in increasing order.
231 // ensure they are scheduled in order of increasing addresses.
284 // Add all nodes in depth first order.
448 const SDep &dep = SDep(OpSU, isChain ? SDep::Order : SDep::Data,
638 unsigned Order) {
643 // order number right after the N.
651 if (!Order || DVOrder == ++Order) {
662 // ProcessSourceNode - Process nodes with source order numbers. These are adde
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| ScheduleDAG.h | 51 Order ///< Any other ordering dependency.
66 /// Order - Additional information about Order dependencies.
80 } Order;
106 assert(!isMustAlias && "isMustAlias only applies with SDep::Order!");
107 assert(!isArtificial && "isArtificial only applies with SDep::Order!");
110 case Order:
112 Contents.Order.isNormalMemory = isNormalMemory;
113 Contents.Order.isMustAlias = isMustAlias;
114 Contents.Order.isArtificial = isArtificial
[all...] |
| /external/icu4c/test/intltest/ |
| tscoll.h | 26 struct Order
28 int32_t order; member in struct:IntlTestCollator::Order
51 Order *getOrders(CollationElementIterator &iter, int32_t &orderLength);
|
| tscoll.cpp | 404 LocalArray<Order> orders(getOrders(iter, orderLength));
429 if (o != orders[index].order) {
433 while (index > 0 && orders[--index].order == 0) {
437 if (o != orders[index].order) {
438 errln("Mismatched order at index %d: 0x%0:8X vs. 0x%0:8X", index,
439 orders[index].order, o);
457 while (index != 0 && orders[index - 1].order == 0)
497 IntlTestCollator::Order *IntlTestCollator::getOrders(CollationElementIterator &iter, int32_t &orderLength)
501 LocalArray<Order> orders(new Order[maxSize])
505 int32_t order; local
[all...] |
| ssearch.cpp | 674 struct Order
676 int32_t order; member in struct:Order
689 void add(int32_t order, int32_t low, int32_t high);
690 const Order *get(int32_t index) const;
699 Order *list;
707 list = new Order[listMax];
716 int32_t order, low, high; local
732 list = new Order[listMax];
738 order = ucol_next(elems, &status);
741 if (order != UCOL_NULLORDER)
788 const Order *order = get(index); local
799 const Order *order = get(index); local
810 const Order *order = get(index); local
875 const Order *order = list.get(i); local
893 const Order *order = list.get(i); local
991 int32_t order, low, high; local
1116 uint64_t order; local
[all...] |
| /external/llvm/lib/Target/ |
| TargetRegisterInfo.cpp | 76 ArrayRef<unsigned> Order = RC->getRawAllocationOrder(MF);
77 for (unsigned i = 0; i != Order.size(); ++i)
78 R.set(Order[i]);
|
| /external/webkit/LayoutTests/http/conf/ |
| apache2-debian-httpd.conf | 188 # Note: The order in which modules are loaded is important. Don't change
189 # the order below without expert advice.
295 Order allow,deny
317 Order allow,deny
327 Order allow,deny
333 Order allow,deny
524 # Just list the languages in decreasing order of preference. We have
637 # Order deny,allow
|
| apache2-httpd.conf | 184 # Note: The order in which modules are loaded is important. Don't change
185 # the order below without expert advice.
316 Order allow,deny
338 Order allow,deny
348 Order allow,deny
354 Order allow,deny
545 # Just list the languages in decreasing order of preference. We have
658 # Order deny,allow
|
| apache2-msys-httpd.conf | 184 # Note: The order in which modules are loaded is important. Don't change
185 # the order below without expert advice.
317 Order allow,deny
339 Order allow,deny
349 Order allow,deny
355 Order allow,deny
546 # Just list the languages in decreasing order of preference. We have
659 # Order deny,allow
|
| cygwin-httpd.conf | 93 # in that order. The latter two files are now distributed empty, as it is
198 # Note: The order in which modules are loaded is important. Don't change
199 # the order below without expert advice.
242 # (static and shared ones) to achieve correct module execution order.
348 Order allow,deny
370 Order allow,deny
380 Order allow,deny
386 Order allow,deny
577 # Just list the languages in decreasing order of preference. We have
690 # Order deny,allo
[all...] |
| fedora-httpd.conf | 336 Order allow,deny
350 # Order allow,deny
354 # Order deny,allow
381 Order allow,deny
391 Order allow,deny
397 Order allow,deny
629 # Just list the languages in decreasing order of preference. We have
778 # Order deny,allow
790 # Order deny,allow
803 # Order deny,allo
[all...] |
| httpd.conf | 93 # in that order. The latter two files are now distributed empty, as it is
200 # Note: The order in which modules are loaded is important. Don't change
201 # the order below without expert advice.
245 # (static and shared ones) to achieve correct module execution order.
351 Order allow,deny
373 Order allow,deny
383 Order allow,deny
389 Order allow,deny
580 # Just list the languages in decreasing order of preference. We have
693 # Order deny,allo
[all...] |
| /external/llvm/utils/TableGen/ |
| RegisterInfoEmitter.cpp | 187 // Sort by name to get a stable order.
286 // getSubRegs() orders by SubRegIndex. We want a topological order.
341 ArrayRef<Record*> Order = RC.getOrder();
350 for (unsigned i = 0, e = Order.size(); i != e; ++i) {
351 Record *Reg = Order[i];
360 for (unsigned i = 0, e = Order.size(); i != e; ++i) {
361 Record *Reg = Order[i];
504 ArrayRef<Record*> Order = RC.getOrder();
507 AllocatableRegs.insert(Order.begin(), Order.end())
[all...] |
| CodeGenRegisters.cpp | 73 // Here the order is important - earlier subregs take precedence.
79 // This creates a topological ordering, the exact order depends on the
80 // order getSubRegs is called on all registers.
276 // Allocation order 0 is the full set. AltOrders provides others.
281 // Default allocation order always contains all registers.
288 SetTheory::RecSet Order;
290 RegBank.getSets().evaluate(AltOrders->getElement(i), Order);
291 Orders[1 + i].append(Order.begin(), Order.end());
293 while (!Order.empty())
[all...] |
| /external/llvm/lib/Support/ |
| Dwarf.cpp | [all...] |
