/external/llvm/lib/CodeGen/ |
RegisterCoalescer.h | 42 unsigned SubIdx; 60 : TII(tii), TRI(tri), DstReg(0), SrcReg(0), SubIdx(0), 68 /// because DstReg is a physical register, or SubIdx is set. 99 unsigned getSubIdx() const { return SubIdx; }
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LiveDebugVariables.h | 40 /// renameRegister - Move any user variables in OldReg to NewReg:SubIdx. 43 /// @param SubIdx If NewReg is a virtual register, SubIdx may indicate a sub- 45 void renameRegister(unsigned OldReg, unsigned NewReg, unsigned SubIdx);
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ExpandPostRAPseudos.cpp | 109 assert(!MI->getOperand(2).getSubReg() && "SubIdx on physreg?"); 110 unsigned SubIdx = MI->getOperand(3).getImm(); 112 assert(SubIdx != 0 && "Invalid index for insert_subreg"); 113 unsigned DstSubReg = TRI->getSubReg(DstReg, SubIdx); 129 MI->RemoveOperand(3); // SubIdx
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VirtRegRewriter.cpp | 704 /// where its SubIdx sub-register is SubReg. 706 unsigned SubIdx, const TargetRegisterInfo *TRI) { 710 if (TRI->getSubReg(Reg, SubIdx) == SubReg) [all...] |
LiveDebugVariables.cpp | 250 /// renameRegister - Update locations to rewrite OldReg as NewReg:SubIdx. 251 void renameRegister(unsigned OldReg, unsigned NewReg, unsigned SubIdx, 337 /// renameRegister - Replace all references to OldReg with NewReg:SubIdx. 338 void renameRegister(unsigned OldReg, unsigned NewReg, unsigned SubIdx); 701 renameRegister(unsigned OldReg, unsigned NewReg, unsigned SubIdx, 711 Loc.substVirtReg(NewReg, SubIdx, *TRI); 717 renameRegister(unsigned OldReg, unsigned NewReg, unsigned SubIdx) { 727 UV->renameRegister(OldReg, NewReg, SubIdx, TRI); 733 renameRegister(unsigned OldReg, unsigned NewReg, unsigned SubIdx) { 735 static_cast<LDVImpl*>(pImpl)->renameRegister(OldReg, NewReg, SubIdx); [all...] |
TwoAddressInstructionPass.cpp | [all...] |
PeepholeOptimizer.cpp | 134 unsigned SrcReg, DstReg, SubIdx; 135 if (!TII->isCoalescableExtInstr(*MI, SrcReg, DstReg, SubIdx)) 246 .addReg(DstReg, 0, SubIdx);
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MachineVerifier.cpp | 735 unsigned SubIdx = MO->getSubReg(); 738 if (SubIdx) { 752 if (SubIdx) { 754 TRI->getSubClassWithSubReg(RC, SubIdx); 758 << " does not support subreg index " << SubIdx << "\n"; 764 << " does not fully support subreg index " << SubIdx << "\n"; 769 if (SubIdx) { 776 DRC = TRI->getMatchingSuperRegClass(SuperRC, DRC, SubIdx); [all...] |
MachineInstr.cpp | 117 void MachineOperand::substVirtReg(unsigned Reg, unsigned SubIdx, 120 if (SubIdx && getSubReg()) 121 SubIdx = TRI.composeSubRegIndices(SubIdx, getSubReg()); 123 if (SubIdx) 124 setSubReg(SubIdx); [all...] |
RegisterCoalescer.cpp | 243 SrcReg = DstReg = SubIdx = 0; 319 "Cannot have a physical SubIdx"); 322 SubIdx = DstSub; 327 if (SubIdx || TargetRegisterInfo::isPhysicalRegister(DstReg)) 353 assert(!SubIdx && "Inconsistent CoalescerPair state."); 367 return compose(TRI, SubIdx, SrcSub) == DstSub; [all...] |
TargetInstrInfoImpl.cpp | 204 unsigned SubIdx, 208 MI->substituteRegister(MI->getOperand(0).getReg(), DestReg, SubIdx, TRI);
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/external/llvm/lib/Target/ARM/ |
Thumb2RegisterInfo.cpp | 38 unsigned DestReg, unsigned SubIdx, 49 .addReg(DestReg, getDefRegState(true), SubIdx)
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Thumb2RegisterInfo.h | 36 unsigned DestReg, unsigned SubIdx, int Val,
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Thumb1RegisterInfo.h | 41 unsigned DestReg, unsigned SubIdx, int Val,
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ARMBaseRegisterInfo.h | 171 unsigned DestReg, unsigned SubIdx,
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ARMBaseInstrInfo.h | 136 unsigned DestReg, unsigned SubIdx,
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/external/llvm/lib/Target/ |
TargetRegisterInfo.cpp | 43 if (SubIdx) { 45 OS << ':' << TRI->getSubRegIndexName(SubIdx); 47 OS << ":sub(" << SubIdx << ')';
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/external/llvm/include/llvm/Target/ |
TargetRegisterInfo.h | 324 const char *getSubRegIndexName(unsigned SubIdx) const { 325 assert(SubIdx && "This is not a subregister index"); 326 return SubRegIndexNames[SubIdx-1]; 381 /// Reg so its sub-register of index SubIdx is Reg. 382 unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx, 385 if (Reg == getSubReg(SR, SubIdx) && RC->contains(SR)) 703 unsigned SubIdx; 705 PrintReg(unsigned reg, const TargetRegisterInfo *tri = 0, unsigned subidx = 0) 706 : TRI(tri), Reg(reg), SubIdx(subidx) {} [all...] |
TargetInstrInfo.h | 108 /// SubIdx. 111 unsigned &SubIdx) const { 179 /// DestReg:SubIdx. Any existing subreg index is preserved or composed with 180 /// SubIdx. 183 unsigned DestReg, unsigned SubIdx, [all...] |
/external/llvm/utils/TableGen/ |
CodeGenRegisters.h | 152 // registers have a SubIdx sub-register. 153 CodeGenRegisterClass *getSubClassWithSubReg(Record *SubIdx) const { 154 return SubClassWithSubReg.lookup(SubIdx); 157 void setSubClassWithSubReg(Record *SubIdx, CodeGenRegisterClass *SubRC) { 158 SubClassWithSubReg[SubIdx] = SubRC;
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CodeGenRegisters.cpp | 771 Record *SubIdx = SubRegIndices[sri]; 772 SubReg2SetMap::const_iterator I = SRSets.find(SubIdx); 778 RC.setSubClassWithSubReg(SubIdx, &RC); 786 RC.setSubClassWithSubReg(SubIdx, FoundI->second); 795 RC.setSubClassWithSubReg(SubIdx, NewRC);
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/external/llvm/lib/CodeGen/SelectionDAG/ |
InstrEmitter.cpp | 400 unsigned InstrEmitter::ConstrainForSubReg(unsigned VReg, unsigned SubIdx, 403 const TargetRegisterClass *RC = TRI->getSubClassWithSubReg(VRC, SubIdx); 405 // RC is a sub-class of VRC that supports SubIdx. Try to constrain VReg 410 // VReg has been adjusted. It can be used with SubIdx operands now. 416 RC = TRI->getSubClassWithSubReg(TLI->getRegClassFor(VT), SubIdx); 417 assert(RC && "No legal register class for VT supports that SubIdx"); 451 unsigned SubIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue(); 459 SubIdx == DefSubIdx) { 469 // VReg may not support a SubIdx sub-register, and we may need to 472 VReg = ConstrainForSubReg(VReg, SubIdx, [all...] |
InstrEmitter.h | 81 /// supports SubIdx sub-registers. Emit a copy if that isn't possible. 83 unsigned ConstrainForSubReg(unsigned VReg, unsigned SubIdx,
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/external/llvm/lib/Target/X86/ |
X86InstrInfo.h | 165 /// SubIdx. 168 unsigned &SubIdx) const; 187 unsigned DestReg, unsigned SubIdx,
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/external/llvm/include/llvm/CodeGen/ |
MachineInstr.h | 438 /// substituteRegister - Replace all occurrences of FromReg with ToReg:SubIdx, 440 void substituteRegister(unsigned FromReg, unsigned ToReg, unsigned SubIdx,
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