| /external/llvm/lib/Target/CellSPU/ |
| SPUHazardRecognizers.h | 28 const TargetInstrInfo &TII;
32 SPUHazardRecognizer(const TargetInstrInfo &TII);
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| SPUFrameLowering.cpp | 94 const SPUInstrInfo &TII =
119 BuildMI(MBB, MBBI, dl, TII.get(SPU::PROLOG_LABEL)).addSym(FrameLabel);
124 BuildMI(MBB, MBBI, dl, TII.get(SPU::STQDr32), SPU::R0).addImm(16)
128 BuildMI(MBB, MBBI, dl, TII.get(SPU::STQDr32), SPU::R1).addImm(FrameSize)
131 BuildMI(MBB, MBBI, dl, TII.get(SPU::AIr32), SPU::R1).addReg(SPU::R1)
136 BuildMI(MBB, MBBI, dl, TII.get(SPU::STQDr128), SPU::R2)
139 BuildMI(MBB, MBBI, dl, TII.get(SPU::ILr32), SPU::R2)
141 BuildMI(MBB, MBBI, dl, TII.get(SPU::STQXr32), SPU::R1)
144 BuildMI(MBB, MBBI, dl, TII.get(SPU::Ar32), SPU::R1)
147 BuildMI(MBB, MBBI, dl, TII.get(SPU::SFIr32), SPU::R2
[all...] |
| SPUNopFiller.cpp | 31 const TargetInstrInfo *TII;
37 : MachineFunctionPass(ID), TM(tm), TII(tm.getInstrInfo()),
96 BuildMI(MBB, I, I->getDebugLoc(), TII->get(SPU::ENOP));
105 BuildMI(MBB, I, I->getDebugLoc(), TII->get(SPU::LNOP));
121 BuildMI(MBB, J, J->getDebugLoc(), TII->get(SPU::ENOP));
126 BuildMI(MBB, J, DebugLoc(), TII->get(SPU::LNOP));
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| /external/llvm/lib/Target/Sparc/ |
| SparcFrameLowering.cpp | 32 const SparcInstrInfo &TII =
55 BuildMI(MBB, MBBI, dl, TII.get(SP::SAVEri), SP::O6)
61 BuildMI(MBB, MBBI, dl, TII.get(SP::SETHIi), SP::G1).addImm(OffHi);
63 BuildMI(MBB, MBBI, dl, TII.get(SP::ORri), SP::G1)
65 BuildMI(MBB, MBBI, dl, TII.get(SP::SAVErr), SP::O6)
73 const SparcInstrInfo &TII =
78 BuildMI(MBB, MBBI, dl, TII.get(SP::RESTORErr), SP::G0).addReg(SP::G0)
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| /external/llvm/lib/Target/ARM/ |
| ARMHazardRecognizer.h | 27 const ARMBaseInstrInfo &TII;
38 const ARMBaseInstrInfo &tii,
42 ScoreboardHazardRecognizer(ItinData, DAG, "post-RA-sched"), TII(tii),
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| Thumb1FrameLowering.cpp | 40 const TargetInstrInfo &TII, DebugLoc dl,
43 emitThumbRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes, TII,
54 const Thumb1InstrInfo &TII =
74 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -VARegSaveSize,
79 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -NumBytes,
136 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tADDrSPi), FramePtr)
147 emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -NumBytes,
169 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::R4)
171 AddDefaultPred(AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tLSRri),
175 AddDefaultPred(AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tLSLri)
[all...] |
| Thumb1RegisterInfo.cpp | 43 Thumb1RegisterInfo::Thumb1RegisterInfo(const ARMBaseInstrInfo &tii,
45 : ARMBaseRegisterInfo(tii, sti) {
77 BuildMI(MBB, MBBI, dl, TII.get(ARM::tLDRpci))
94 const TargetInstrInfo &TII,
116 AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8), LdReg))
119 AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8), LdReg))
121 AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tRSB), LdReg))
130 BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg);
170 int NumBytes, const TargetInstrInfo &TII,
230 TII, MRI, MIFlags)
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsFrameLowering.cpp | 121 const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
128 BuildMI(MBB, I, DL, TII->get(Mips::NOAT));
129 BuildMI(MBB, I, DL, TII->get(Mips::LUi), Mips::AT).addImm(ImmHi);
130 BuildMI(MBB, I, DL, TII->get(Mips::ADDu), Mips::AT).addReg(OrigReg)
144 const MipsInstrInfo &TII =
165 BuildMI(MBB, MBBI, dl, TII.get(Mips::NOREORDER));
169 BuildMI(MBB, MBBI, dl, TII.get(Mips::CPLOAD))
171 BuildMI(MBB, MBBI, dl, TII.get(Mips::NOMACRO));
183 BuildMI(MBB, MBBI, dl, TII.get(Mips::ADDiu), Mips::SP)
188 BuildMI(MBB, MBBI, dl, TII.get(Mips::ATMACRO))
[all...] |
| MipsEmitGPRestore.cpp | 31 const TargetInstrInfo *TII;
35 : MachineFunctionPass(ID), TM(tm), TII(tm.getInstrInfo()) { }
67 BuildMI(MBB, I, dl, TII->get(Mips::LW), Mips::GP).addFrameIndex(FI)
80 BuildMI(MBB, ++I, dl, TII->get(Mips::LW), Mips::GP).addFrameIndex(FI)
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| /external/llvm/lib/Target/Alpha/ |
| AlphaFrameLowering.cpp | 50 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
56 BuildMI(MBB, MBBI, dl, TII.get(Alpha::LDAHg), Alpha::R29)
58 BuildMI(MBB, MBBI, dl, TII.get(Alpha::LDAg), Alpha::R29)
61 BuildMI(MBB, MBBI, dl, TII.get(Alpha::ALTENT))
82 BuildMI(MBB, MBBI, dl, TII.get(Alpha::LDA), Alpha::R30).addImm(NumBytes)
85 BuildMI(MBB, MBBI, dl, TII.get(Alpha::LDAH), Alpha::R30)
87 BuildMI(MBB, MBBI, dl, TII.get(Alpha::LDA), Alpha::R30)
95 BuildMI(MBB, MBBI, dl, TII.get(Alpha::STQ))
98 BuildMI(MBB, MBBI, dl, TII.get(Alpha::BISr), Alpha::R15)
108 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo()
[all...] |
| AlphaBranchSelector.cpp | 58 const TargetInstrInfo *TII = Fn.getTarget().getInstrInfo();
59 MBBI->setDesc(TII->get(MBBI->getOperand(0).getImm()));
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| AlphaLLRP.cpp | 49 const TargetInstrInfo *TII = F.getTarget().getInstrInfo();
77 BuildMI(MBB, MI, dl, TII->get(Alpha::BISr), Alpha::R31)
89 BuildMI(MBB, MI, dl, TII->get(Alpha::BISr), Alpha::R31)
92 BuildMI(MBB, MI, dl, TII->get(Alpha::BISr), Alpha::R31)
103 BuildMI(MBB, MI, dl, TII->get(Alpha::BISr), Alpha::R31)
105 BuildMI(MBB, MI, dl, TII->get(Alpha::BISr), Alpha::R31)
107 BuildMI(MBB, MI, dl, TII->get(Alpha::BISr), Alpha::R31)
140 BuildMI(MBB, MBB.end(), dl, TII->get(Alpha::BISr), Alpha::R31)
|
| /external/llvm/lib/Target/XCore/ |
| XCoreFrameLowering.cpp | 48 const TargetInstrInfo &TII) {
55 BuildMI(MBB, I, dl, TII.get(Opcode), DstReg)
63 const TargetInstrInfo &TII) {
70 BuildMI(MBB, I, dl, TII.get(Opcode))
97 const XCoreInstrInfo &TII =
107 loadFromStack(MBB, MBBI, XCore::R11, 0, dl, TII);
136 BuildMI(MBB, MBBI, dl, TII.get(Opcode)).addImm(FrameSize);
143 BuildMI(MBB, MBBI, dl, TII.get(XCore::PROLOG_LABEL)).addSym(FrameLabel);
157 storeToStack(MBB, MBBI, XCore::LR, LRSpillOffset + FrameSize*4, dl, TII);
162 BuildMI(MBB, MBBI, dl, TII.get(XCore::PROLOG_LABEL)).addSym(SaveLRLabel)
[all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430BranchSelector.cpp | 55 const MSP430InstrInfo *TII =
70 BlockSize += TII->GetInstSizeInBytes(MBBI);
107 MBBStartOffset += TII->GetInstSizeInBytes(I);
154 TII->ReverseBranchCondition(Cond);
155 BuildMI(MBB, I, dl, TII->get(MSP430::JCC))
161 I = BuildMI(MBB, I, dl, TII->get(MSP430::Bi)).addMBB(Dest);
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| MSP430FrameLowering.cpp | 45 const MSP430InstrInfo &TII =
66 BuildMI(MBB, MBBI, DL, TII.get(MSP430::PUSH16r))
70 BuildMI(MBB, MBBI, DL, TII.get(MSP430::MOV16rr), MSP430::FPW)
98 BuildMI(MBB, MBBI, DL, TII.get(MSP430::SUB16ri), MSP430::SPW)
110 const MSP430InstrInfo &TII =
135 BuildMI(MBB, MBBI, DL, TII.get(MSP430::POP16r), MSP430::FPW);
157 TII.get(MSP430::MOV16rr), MSP430::SPW).addReg(MSP430::FPW);
161 TII.get(MSP430::SUB16ri), MSP430::SPW)
170 BuildMI(MBB, MBBI, DL, TII.get(MSP430::ADD16ri), MSP430::SPW)
191 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo()
[all...] |
| MSP430RegisterInfo.cpp | 36 const TargetInstrInfo &tii)
37 : MSP430GenRegisterInfo(MSP430::PCW), TM(tm), TII(tii) {
122 if (Old->getOpcode() == TII.getCallFrameSetupOpcode()) {
124 TII.get(MSP430::SUB16ri), MSP430::SPW)
127 assert(Old->getOpcode() == TII.getCallFrameDestroyOpcode());
133 TII.get(MSP430::ADD16ri), MSP430::SPW)
145 } else if (I->getOpcode() == TII.getCallFrameDestroyOpcode()) {
151 BuildMI(MF, Old->getDebugLoc(), TII.get(MSP430::SUB16ri),
200 MI.setDesc(TII.get(MSP430::MOV16rr))
[all...] |
| /external/llvm/lib/CodeGen/ |
| RegisterCoalescer.h | 29 const TargetInstrInfo &TII;
59 CoalescerPair(const TargetInstrInfo &tii, const TargetRegisterInfo &tri)
60 : TII(tii), TRI(tri), DstReg(0), SrcReg(0), SubIdx(0),
|
| ScheduleDAGEmit.cpp | 32 TII->insertNoop(*BB, InsertPos);
54 BuildMI(*BB, InsertPos, DebugLoc(), TII->get(TargetOpcode::COPY), Reg)
63 BuildMI(*BB, InsertPos, DebugLoc(), TII->get(TargetOpcode::COPY), VRBase)
|
| /external/llvm/lib/Target/Blackfin/ |
| BlackfinFrameLowering.cpp | 49 const BlackfinInstrInfo &TII =
69 BuildMI(MBB, MBBI, dl, TII.get(BF::LINK)).addImm(FrameSize);
79 BuildMI(MBB, MBBI, dl, TII.get(BF::PUSH))
81 BuildMI(MBB, MBBI, dl, TII.get(BF::PUSH))
83 BuildMI(MBB, MBBI, dl, TII.get(BF::MOVE), BF::FP)
86 BuildMI(MBB, MBBI, dl, TII.get(BF::ADDpp), BF::SP)
97 const BlackfinInstrInfo &TII =
113 BuildMI(MBB, MBBI, dl, TII.get(BF::UNLINK));
|
| BlackfinRegisterInfo.cpp | 38 const TargetInstrInfo &tii)
39 : BlackfinGenRegisterInfo(BF::RETS), Subtarget(st), TII(tii) {}
97 BuildMI(MBB, I, DL, TII.get(BF::ADDpp_imm7), Reg)
108 BuildMI(MBB, I, DL, TII.get(BF::ADDpp), Reg)
115 BuildMI(MBB, I, DL, TII.get(BF::ADD), Reg)
128 BuildMI(MBB, I, DL, TII.get(BF::LOADimm7), Reg).addImm(value);
133 BuildMI(MBB, I, DL, TII.get(BF::LOADuimm16), Reg).addImm(value);
138 BuildMI(MBB, I, DL, TII.get(BF::LOADimm16), Reg).addImm(value);
144 TII.get(BF::LOAD16i), getSubReg(Reg, BF::hi16)
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCHazardRecognizers.h | 43 const TargetInstrInfo &TII;
63 PPCHazardRecognizer970(const TargetInstrInfo &TII);
|
| PPCFrameLowering.cpp | 98 static void HandleVRSaveUpdate(MachineInstr *MI, const TargetInstrInfo &TII) {
136 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
140 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
145 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
149 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
154 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
158 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
162 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
256 const PPCInstrInfo &TII =
271 HandleVRSaveUpdate(MBBI, TII);
[all...] |
| PPCBranchSelector.cpp | 56 const PPCInstrInfo *TII =
71 BlockSize += TII->GetInstSizeInBytes(MBBI);
107 MBBStartOffset += TII->GetInstSizeInBytes(I);
151 BuildMI(MBB, I, dl, TII->get(PPC::BCC))
155 I = BuildMI(MBB, I, dl, TII->get(PPC::B)).addMBB(Dest);
|
| /external/llvm/include/llvm/CodeGen/ |
| ProcessImplicitDefs.h | 28 const TargetInstrInfo *TII;
|
| /external/llvm/lib/Target/PTX/ |
| PTXRegisterInfo.h | 29 const TargetInstrInfo &TII;
33 const TargetInstrInfo &tii);
|
