1 //===-- PPCHazardRecognizers.h - PowerPC Hazard Recognizers -----*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file defines hazard recognizers for scheduling on PowerPC processors. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef PPCHAZRECS_H 15 #define PPCHAZRECS_H 16 17 #include "llvm/CodeGen/ScheduleHazardRecognizer.h" 18 #include "llvm/CodeGen/ScoreboardHazardRecognizer.h" 19 #include "llvm/CodeGen/SelectionDAGNodes.h" 20 #include "PPCInstrInfo.h" 21 22 namespace llvm { 23 24 /// PPCHazardRecognizer440 - This class implements a scoreboard-based 25 /// hazard recognizer for the PPC 440 and friends. 26 class PPCHazardRecognizer440 : public ScoreboardHazardRecognizer { 27 const ScheduleDAG *DAG; 28 public: 29 PPCHazardRecognizer440(const InstrItineraryData *ItinData, 30 const ScheduleDAG *DAG_) : 31 ScoreboardHazardRecognizer(ItinData, DAG_), DAG(DAG_) {} 32 33 virtual void EmitInstruction(SUnit *SU); 34 }; 35 36 /// PPCHazardRecognizer970 - This class defines a finite state automata that 37 /// models the dispatch logic on the PowerPC 970 (aka G5) processor. This 38 /// promotes good dispatch group formation and implements noop insertion to 39 /// avoid structural hazards that cause significant performance penalties (e.g. 40 /// setting the CTR register then branching through it within a dispatch group), 41 /// or storing then loading from the same address within a dispatch group. 42 class PPCHazardRecognizer970 : public ScheduleHazardRecognizer { 43 const TargetInstrInfo &TII; 44 45 unsigned NumIssued; // Number of insts issued, including advanced cycles. 46 47 // Various things that can cause a structural hazard. 48 49 // HasCTRSet - If the CTR register is set in this group, disallow BCTRL. 50 bool HasCTRSet; 51 52 // StoredPtr - Keep track of the address of any store. If we see a load from 53 // the same address (or one that aliases it), disallow the store. We can have 54 // up to four stores in one dispatch group, hence we track up to 4. 55 // 56 // This is null if we haven't seen a store yet. We keep track of both 57 // operands of the store here, since we support [r+r] and [r+i] addressing. 58 SDValue StorePtr1[4], StorePtr2[4]; 59 unsigned StoreSize[4]; 60 unsigned NumStores; 61 62 public: 63 PPCHazardRecognizer970(const TargetInstrInfo &TII); 64 virtual HazardType getHazardType(SUnit *SU, int Stalls); 65 virtual void EmitInstruction(SUnit *SU); 66 virtual void AdvanceCycle(); 67 68 private: 69 /// EndDispatchGroup - Called when we are finishing a new dispatch group. 70 /// 71 void EndDispatchGroup(); 72 73 /// GetInstrType - Classify the specified powerpc opcode according to its 74 /// pipeline. 75 PPCII::PPC970_Unit GetInstrType(unsigned Opcode, 76 bool &isFirst, bool &isSingle,bool &isCracked, 77 bool &isLoad, bool &isStore); 78 79 bool isLoadOfStoredAddress(unsigned LoadSize, 80 SDValue Ptr1, SDValue Ptr2) const; 81 }; 82 83 } // end namespace llvm 84 85 #endif 86 87
