1 //===-- PPCHazardRecognizers.cpp - PowerPC Hazard Recognizer Impls --------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements hazard recognizers for scheduling on PowerPC processors. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #define DEBUG_TYPE "pre-RA-sched" 15 #include "PPCHazardRecognizers.h" 16 #include "PPC.h" 17 #include "PPCInstrInfo.h" 18 #include "llvm/CodeGen/ScheduleDAG.h" 19 #include "llvm/Support/Debug.h" 20 #include "llvm/Support/ErrorHandling.h" 21 #include "llvm/Support/raw_ostream.h" 22 using namespace llvm; 23 24 //===----------------------------------------------------------------------===// 25 // PowerPC 440 Hazard Recognizer 26 void PPCHazardRecognizer440::EmitInstruction(SUnit *SU) { 27 const MCInstrDesc *MCID = DAG->getInstrDesc(SU); 28 if (!MCID) { 29 // This is a PPC pseudo-instruction. 30 // FIXME: Should something else be done? 31 return; 32 } 33 34 ScoreboardHazardRecognizer::EmitInstruction(SU); 35 } 36 37 //===----------------------------------------------------------------------===// 38 // PowerPC 970 Hazard Recognizer 39 // 40 // This models the dispatch group formation of the PPC970 processor. Dispatch 41 // groups are bundles of up to five instructions that can contain various mixes 42 // of instructions. The PPC970 can dispatch a peak of 4 non-branch and one 43 // branch instruction per-cycle. 44 // 45 // There are a number of restrictions to dispatch group formation: some 46 // instructions can only be issued in the first slot of a dispatch group, & some 47 // instructions fill an entire dispatch group. Additionally, only branches can 48 // issue in the 5th (last) slot. 49 // 50 // Finally, there are a number of "structural" hazards on the PPC970. These 51 // conditions cause large performance penalties due to misprediction, recovery, 52 // and replay logic that has to happen. These cases include setting a CTR and 53 // branching through it in the same dispatch group, and storing to an address, 54 // then loading from the same address within a dispatch group. To avoid these 55 // conditions, we insert no-op instructions when appropriate. 56 // 57 // FIXME: This is missing some significant cases: 58 // 1. Modeling of microcoded instructions. 59 // 2. Handling of serialized operations. 60 // 3. Handling of the esoteric cases in "Resource-based Instruction Grouping". 61 // 62 63 PPCHazardRecognizer970::PPCHazardRecognizer970(const TargetInstrInfo &tii) 64 : TII(tii) { 65 EndDispatchGroup(); 66 } 67 68 void PPCHazardRecognizer970::EndDispatchGroup() { 69 DEBUG(errs() << "=== Start of dispatch group\n"); 70 NumIssued = 0; 71 72 // Structural hazard info. 73 HasCTRSet = false; 74 NumStores = 0; 75 } 76 77 78 PPCII::PPC970_Unit 79 PPCHazardRecognizer970::GetInstrType(unsigned Opcode, 80 bool &isFirst, bool &isSingle, 81 bool &isCracked, 82 bool &isLoad, bool &isStore) { 83 if ((int)Opcode >= 0) { 84 isFirst = isSingle = isCracked = isLoad = isStore = false; 85 return PPCII::PPC970_Pseudo; 86 } 87 Opcode = ~Opcode; 88 89 const MCInstrDesc &MCID = TII.get(Opcode); 90 91 isLoad = MCID.mayLoad(); 92 isStore = MCID.mayStore(); 93 94 uint64_t TSFlags = MCID.TSFlags; 95 96 isFirst = TSFlags & PPCII::PPC970_First; 97 isSingle = TSFlags & PPCII::PPC970_Single; 98 isCracked = TSFlags & PPCII::PPC970_Cracked; 99 return (PPCII::PPC970_Unit)(TSFlags & PPCII::PPC970_Mask); 100 } 101 102 /// isLoadOfStoredAddress - If we have a load from the previously stored pointer 103 /// as indicated by StorePtr1/StorePtr2/StoreSize, return true. 104 bool PPCHazardRecognizer970:: 105 isLoadOfStoredAddress(unsigned LoadSize, SDValue Ptr1, SDValue Ptr2) const { 106 for (unsigned i = 0, e = NumStores; i != e; ++i) { 107 // Handle exact and commuted addresses. 108 if (Ptr1 == StorePtr1[i] && Ptr2 == StorePtr2[i]) 109 return true; 110 if (Ptr2 == StorePtr1[i] && Ptr1 == StorePtr2[i]) 111 return true; 112 113 // Okay, we don't have an exact match, if this is an indexed offset, see if 114 // we have overlap (which happens during fp->int conversion for example). 115 if (StorePtr2[i] == Ptr2) { 116 if (ConstantSDNode *StoreOffset = dyn_cast<ConstantSDNode>(StorePtr1[i])) 117 if (ConstantSDNode *LoadOffset = dyn_cast<ConstantSDNode>(Ptr1)) { 118 // Okay the base pointers match, so we have [c1+r] vs [c2+r]. Check 119 // to see if the load and store actually overlap. 120 int StoreOffs = StoreOffset->getZExtValue(); 121 int LoadOffs = LoadOffset->getZExtValue(); 122 if (StoreOffs < LoadOffs) { 123 if (int(StoreOffs+StoreSize[i]) > LoadOffs) return true; 124 } else { 125 if (int(LoadOffs+LoadSize) > StoreOffs) return true; 126 } 127 } 128 } 129 } 130 return false; 131 } 132 133 /// getHazardType - We return hazard for any non-branch instruction that would 134 /// terminate the dispatch group. We turn NoopHazard for any 135 /// instructions that wouldn't terminate the dispatch group that would cause a 136 /// pipeline flush. 137 ScheduleHazardRecognizer::HazardType PPCHazardRecognizer970:: 138 getHazardType(SUnit *SU, int Stalls) { 139 assert(Stalls == 0 && "PPC hazards don't support scoreboard lookahead"); 140 141 const SDNode *Node = SU->getNode()->getGluedMachineNode(); 142 bool isFirst, isSingle, isCracked, isLoad, isStore; 143 PPCII::PPC970_Unit InstrType = 144 GetInstrType(Node->getOpcode(), isFirst, isSingle, isCracked, 145 isLoad, isStore); 146 if (InstrType == PPCII::PPC970_Pseudo) return NoHazard; 147 unsigned Opcode = Node->getMachineOpcode(); 148 149 // We can only issue a PPC970_First/PPC970_Single instruction (such as 150 // crand/mtspr/etc) if this is the first cycle of the dispatch group. 151 if (NumIssued != 0 && (isFirst || isSingle)) 152 return Hazard; 153 154 // If this instruction is cracked into two ops by the decoder, we know that 155 // it is not a branch and that it cannot issue if 3 other instructions are 156 // already in the dispatch group. 157 if (isCracked && NumIssued > 2) 158 return Hazard; 159 160 switch (InstrType) { 161 default: llvm_unreachable("Unknown instruction type!"); 162 case PPCII::PPC970_FXU: 163 case PPCII::PPC970_LSU: 164 case PPCII::PPC970_FPU: 165 case PPCII::PPC970_VALU: 166 case PPCII::PPC970_VPERM: 167 // We can only issue a branch as the last instruction in a group. 168 if (NumIssued == 4) return Hazard; 169 break; 170 case PPCII::PPC970_CRU: 171 // We can only issue a CR instruction in the first two slots. 172 if (NumIssued >= 2) return Hazard; 173 break; 174 case PPCII::PPC970_BRU: 175 break; 176 } 177 178 // Do not allow MTCTR and BCTRL to be in the same dispatch group. 179 if (HasCTRSet && (Opcode == PPC::BCTRL_Darwin || Opcode == PPC::BCTRL_SVR4)) 180 return NoopHazard; 181 182 // If this is a load following a store, make sure it's not to the same or 183 // overlapping address. 184 if (isLoad && NumStores) { 185 unsigned LoadSize; 186 switch (Opcode) { 187 default: llvm_unreachable("Unknown load!"); 188 case PPC::LBZ: case PPC::LBZU: 189 case PPC::LBZX: 190 case PPC::LBZ8: case PPC::LBZU8: 191 case PPC::LBZX8: 192 case PPC::LVEBX: 193 LoadSize = 1; 194 break; 195 case PPC::LHA: case PPC::LHAU: 196 case PPC::LHAX: 197 case PPC::LHZ: case PPC::LHZU: 198 case PPC::LHZX: 199 case PPC::LVEHX: 200 case PPC::LHBRX: 201 case PPC::LHA8: case PPC::LHAU8: 202 case PPC::LHAX8: 203 case PPC::LHZ8: case PPC::LHZU8: 204 case PPC::LHZX8: 205 LoadSize = 2; 206 break; 207 case PPC::LFS: case PPC::LFSU: 208 case PPC::LFSX: 209 case PPC::LWZ: case PPC::LWZU: 210 case PPC::LWZX: 211 case PPC::LWA: 212 case PPC::LWAX: 213 case PPC::LVEWX: 214 case PPC::LWBRX: 215 case PPC::LWZ8: 216 case PPC::LWZX8: 217 LoadSize = 4; 218 break; 219 case PPC::LFD: case PPC::LFDU: 220 case PPC::LFDX: 221 case PPC::LD: case PPC::LDU: 222 case PPC::LDX: 223 LoadSize = 8; 224 break; 225 case PPC::LVX: 226 case PPC::LVXL: 227 LoadSize = 16; 228 break; 229 } 230 231 if (isLoadOfStoredAddress(LoadSize, 232 Node->getOperand(0), Node->getOperand(1))) 233 return NoopHazard; 234 } 235 236 return NoHazard; 237 } 238 239 void PPCHazardRecognizer970::EmitInstruction(SUnit *SU) { 240 const SDNode *Node = SU->getNode()->getGluedMachineNode(); 241 bool isFirst, isSingle, isCracked, isLoad, isStore; 242 PPCII::PPC970_Unit InstrType = 243 GetInstrType(Node->getOpcode(), isFirst, isSingle, isCracked, 244 isLoad, isStore); 245 if (InstrType == PPCII::PPC970_Pseudo) return; 246 unsigned Opcode = Node->getMachineOpcode(); 247 248 // Update structural hazard information. 249 if (Opcode == PPC::MTCTR || Opcode == PPC::MTCTR8) HasCTRSet = true; 250 251 // Track the address stored to. 252 if (isStore) { 253 unsigned ThisStoreSize; 254 switch (Opcode) { 255 default: llvm_unreachable("Unknown store instruction!"); 256 case PPC::STB: case PPC::STB8: 257 case PPC::STBU: case PPC::STBU8: 258 case PPC::STBX: case PPC::STBX8: 259 case PPC::STVEBX: 260 ThisStoreSize = 1; 261 break; 262 case PPC::STH: case PPC::STH8: 263 case PPC::STHU: case PPC::STHU8: 264 case PPC::STHX: case PPC::STHX8: 265 case PPC::STVEHX: 266 case PPC::STHBRX: 267 ThisStoreSize = 2; 268 break; 269 case PPC::STFS: 270 case PPC::STFSU: 271 case PPC::STFSX: 272 case PPC::STWX: case PPC::STWX8: 273 case PPC::STWUX: 274 case PPC::STW: case PPC::STW8: 275 case PPC::STWU: 276 case PPC::STVEWX: 277 case PPC::STFIWX: 278 case PPC::STWBRX: 279 ThisStoreSize = 4; 280 break; 281 case PPC::STD_32: 282 case PPC::STDX_32: 283 case PPC::STD: 284 case PPC::STDU: 285 case PPC::STFD: 286 case PPC::STFDX: 287 case PPC::STDX: 288 case PPC::STDUX: 289 ThisStoreSize = 8; 290 break; 291 case PPC::STVX: 292 case PPC::STVXL: 293 ThisStoreSize = 16; 294 break; 295 } 296 297 StoreSize[NumStores] = ThisStoreSize; 298 StorePtr1[NumStores] = Node->getOperand(1); 299 StorePtr2[NumStores] = Node->getOperand(2); 300 ++NumStores; 301 } 302 303 if (InstrType == PPCII::PPC970_BRU || isSingle) 304 NumIssued = 4; // Terminate a d-group. 305 ++NumIssued; 306 307 // If this instruction is cracked into two ops by the decoder, remember that 308 // we issued two pieces. 309 if (isCracked) 310 ++NumIssued; 311 312 if (NumIssued == 5) 313 EndDispatchGroup(); 314 } 315 316 void PPCHazardRecognizer970::AdvanceCycle() { 317 assert(NumIssued < 5 && "Illegal dispatch group!"); 318 ++NumIssued; 319 if (NumIssued == 5) 320 EndDispatchGroup(); 321 } 322