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    Searched refs:setDesc (Results 1 - 25 of 26) sorted by null

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  /external/llvm/lib/Target/Alpha/
AlphaBranchSelector.cpp 59 MBBI->setDesc(TII->get(MBBI->getOperand(0).getImm()));
  /external/llvm/lib/Target/Sparc/
FPMover.cpp 107 MI->setDesc(TII->get(SP::FMOVS));
109 MI->setDesc(TII->get(SP::FNEGS));
111 MI->setDesc(TII->get(SP::FABSS));
DelaySlotFiller.cpp 147 slot->setDesc(TII->get(SP::RET));
  /external/icu4c/i18n/unicode/
numsys.h 177 void setDesc(UnicodeString desc);
  /external/llvm/lib/Target/Blackfin/
BlackfinRegisterInfo.cpp 226 MI.setDesc(TII.get(isStore
232 MI.setDesc(TII.get(isStore
239 MI.setDesc(TII.get(isStore
273 MI.setDesc(TII.get(isStore ? BF::STORE16pi : BF::LOAD16pi));
294 MI.setDesc(TII.get(BF::STORE8p_imm16));
306 MI.setDesc(TII.get(BF::LOAD32p_imm16_8z));
  /external/llvm/lib/Target/ARM/
Thumb2InstrInfo.cpp 403 MI.setDesc(TII.get(ARM::tMOVr));
418 MI.setDesc(TII.get(ARM::t2SUBri));
420 MI.setDesc(TII.get(ARM::t2ADDri));
437 MI.setDesc(TII.get(NewOpc));
519 MI.setDesc(TII.get(NewOpc));
552 MI.setDesc(TII.get(positiveOffsetOpcode(NewOpc)));
Thumb1RegisterInfo.cpp 415 MI.setDesc(TII.get(ARM::tMOVr));
428 MI.setDesc(TII.get(Opcode));
457 MI.setDesc(TII.get(Opcode));
475 MI.setDesc(TII.get(ARM::tADDhirr));
506 MI.setDesc(TII.get(NewOpc));
670 MI.setDesc(TII.get(UseRR ? ARM::tLDRr : ARM::tLDRi));
691 MI.setDesc(TII.get(UseRR ? ARM::tSTRr : ARM::tSTRi));
Thumb1FrameLowering.cpp 374 (*MIB).setDesc(TII.get(ARM::tPOP_RET));
ARMConstantIslandPass.cpp     [all...]
ARMBaseInstrInfo.cpp 448 MI->setDesc(get(getMatchingCondBranchOpcode(Opc)));
    [all...]
ARMLoadStoreOptimizer.cpp     [all...]
  /external/llvm/lib/Target/SystemZ/
SystemZRegisterInfo.cpp 124 MI.setDesc(TII.getMemoryInstr(MI.getOpcode(), Offset));
  /external/llvm/lib/Target/X86/
X86CodeEmitter.cpp 599 case X86::ADD16rr_DB: Desc = &II->get(X86::OR16rr); MI.setDesc(*Desc);break;
600 case X86::ADD32rr_DB: Desc = &II->get(X86::OR32rr); MI.setDesc(*Desc);break;
601 case X86::ADD64rr_DB: Desc = &II->get(X86::OR64rr); MI.setDesc(*Desc);break;
602 case X86::ADD16ri_DB: Desc = &II->get(X86::OR16ri); MI.setDesc(*Desc);break;
603 case X86::ADD32ri_DB: Desc = &II->get(X86::OR32ri); MI.setDesc(*Desc);break;
604 case X86::ADD64ri32_DB:Desc = &II->get(X86::OR64ri32);MI.setDesc(*Desc);break;
605 case X86::ADD16ri8_DB: Desc = &II->get(X86::OR16ri8);MI.setDesc(*Desc);break;
606 case X86::ADD32ri8_DB: Desc = &II->get(X86::OR32ri8);MI.setDesc(*Desc);break;
607 case X86::ADD64ri8_DB: Desc = &II->get(X86::OR64ri8);MI.setDesc(*Desc);break;
    [all...]
X86FloatingPoint.cpp 839 I->setDesc(TII->get(Opcode));
    [all...]
X86InstrInfo.cpp     [all...]
  /external/icu4c/i18n/
numsys.cpp 92 ns->setDesc(desc_in);
210 void NumberingSystem::setDesc(UnicodeString d) {
  /external/llvm/lib/CodeGen/
ExpandPostRAPseudos.cpp 128 MI->setDesc(TII->get(TargetOpcode::KILL));
163 MI->setDesc(TII->get(TargetOpcode::KILL));
ProcessImplicitDefs.cpp 153 MI->setDesc(TII->get(TargetOpcode::IMPLICIT_DEF));
249 RMI->setDesc(TII->get(TargetOpcode::IMPLICIT_DEF));
VirtRegMap.cpp 342 MI->setDesc(TII->get(TargetOpcode::KILL));
TwoAddressInstructionPass.cpp     [all...]
InlineSpiller.cpp 786 MI->setDesc(TII.get(TargetOpcode::KILL));
    [all...]
RegisterCoalescer.cpp     [all...]
  /external/llvm/lib/Target/MSP430/
MSP430RegisterInfo.cpp 200 MI.setDesc(TII.get(MSP430::MOV16rr));
  /external/llvm/include/llvm/CodeGen/
MachineInstr.h 529 /// setDesc - Replace the instruction descriptor (thus opcode) of
532 void setDesc(const MCInstrDesc &tid) { MCID = &tid; }
  /external/llvm/lib/Target/PowerPC/
PPCRegisterInfo.cpp 619 MI.setDesc(TII.get(NewOpcode));

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