| /external/llvm/lib/Target/PowerPC/ |
| PPCHazardRecognizers.cpp | 141 const SDNode *Node = SU->getNode()->getGluedMachineNode();
240 const SDNode *Node = SU->getNode()->getGluedMachineNode();
|
| PPCISelLowering.cpp | 576 int PPC::isVSLDOIShuffleMask(SDNode *N, bool isUnary) {
641 bool PPC::isAllNegativeZeroVector(SDNode *N) {
657 unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize) {
667 SDValue PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| ScheduleDAGRRList.cpp | 251 SUnit *CreateNewSUnit(SDNode *N) {
293 const SDNode *Node = RegDefPos.GetNode();
768 static bool isOperandOf(const SUnit *SU, SDNode *N) {
769 for (const SDNode *SUNode = SU->getNode(); SUNode;
780 SDNode *N = SU->getNode();
804 SmallVector<SDNode*, 2> NewNodes;
812 SDNode *LoadNode = NewNodes[0];
[all...] |
| LegalizeVectorOps.cpp | 119 SDNode* Node = Op.getNode();
157 for (SDNode::value_iterator J = Node->value_begin(), E = Node->value_end();
|
| SelectionDAGBuilder.h | 381 void AssignOrderingToNode(const SDNode *Node);
|
| TargetLowering.cpp | [all...] |
| SelectionDAGBuilder.cpp | [all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsISelLowering.h | 113 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
|
| MipsISelLowering.cpp | 251 static bool SelectMadd(SDNode* ADDENode, SelectionDAG* CurDAG) {
254 SDNode* ADDCNode = ADDENode->getOperand(2).getNode();
261 SDNode* MultNode = MultHi.getNode();
325 static bool SelectMsub(SDNode* SUBENode, SelectionDAG* CurDAG) {
328 SDNode* SUBCNode = SUBENode->getOperand(2).getNode();
335 SDNode* MultNode = MultHi.getNode();
391 static SDValue PerformADDECombine(SDNode *N, SelectionDAG& DAG,
403 static SDValue PerformSUBECombine(SDNode *N, SelectionDAG& DAG,
415 static SDValue PerformDivRemCombine(SDNode *N, SelectionDAG& DAG,
525 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG& DAG
[all...] |
| /external/llvm/lib/Target/Blackfin/ |
| BlackfinISelLowering.cpp | 432 SDNode* CarryIn = DAG.getMachineNode(BF::MOVE_cc_ac0, dl, MVT::i32,
438 SDNode *Sum = DAG.getMachineNode(Opcode, dl, MVT::i32, MVT::Glue,
442 SDNode* Carry1 = DAG.getMachineNode(BF::MOVE_cc_ac0, dl, MVT::i32,
450 SDNode *CarryOut = DAG.getMachineNode(BF::OR_ac0_cc, dl, MVT::Glue,
477 BlackfinTargetLowering::ReplaceNodeResults(SDNode *N,
|
| /external/llvm/lib/Target/ARM/ |
| ARMISelLowering.cpp | [all...] |
| ARMBaseInstrInfo.cpp | [all...] |
| /external/llvm/lib/Target/X86/ |
| X86ISelLowering.cpp | [all...] |
| X86InstrInfo.cpp | [all...] |
| /external/llvm/lib/CodeGen/ |
| Analysis.cpp | 287 bool llvm::isInTailCallPosition(SelectionDAG &DAG, SDNode *Node,
|
| ScheduleDAG.cpp | 48 const MCInstrDesc *ScheduleDAG::getNodeDesc(const SDNode *Node) const {
288 /// SUnit - Scheduling unit. It's an wrapper around either a single SDNode or
|
| /external/llvm/lib/Target/CellSPU/ |
| SPUISelLowering.cpp | [all...] |
| /external/llvm/utils/TableGen/ |
| DAGISelMatcherEmitter.cpp | 620 OS << "bool CheckNodePredicate(SDNode *Node, unsigned PredNo) const {\n";
639 OS << "bool CheckComplexPattern(SDNode *Root, SDNode *Parent, SDValue N,\n";
641 OS << " SmallVectorImpl<std::pair<SDValue, SDNode*> > &Result) {\n";
684 // FIXME: The node xform could take SDValue's instead of SDNode*'s.
689 Record *SDNode = Entry.first;
697 std::string ClassName = CGP.getSDNodeInfo(SDNode).getSDClassName();
698 if (ClassName == "SDNode")
699 OS << " SDNode *N = V.getNode();\n";
793 OS << "SDNode *SelectCode(SDNode *N) {\n"
[all...] |
| CodeGenDAGPatterns.cpp | 668 ClassName = "SDNode";
674 if (ClassName == "SDNode")
675 Result = " SDNode *N = Node;\n";
[all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreISelLowering.cpp | 195 void XCoreTargetLowering::ReplaceNodeResults(SDNode *N,
645 TryExpandADDWithMul(SDNode *N, SelectionDAG &DAG) const
705 ExpandADDSUB(SDNode *N, SelectionDAG &DAG) const
749 SDNode *Node = Op.getNode();
[all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.cpp | 595 SDNode* N = Op.getNode();
[all...] |
| /external/llvm/lib/Target/Alpha/ |
| AlphaISelLowering.cpp | 537 void AlphaTargetLowering::LowerVAARG(SDNode *N, SDValue &Chain,
777 void AlphaTargetLowering::ReplaceNodeResults(SDNode *N,
[all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcISelLowering.cpp | [all...] |
