| /external/llvm/lib/Target/MBlaze/ |
| MBlazeISelDAGToDAG.cpp | 85 bool SelectAddrRegReg(SDValue N, SDValue &Base, SDValue &Index);
86 bool SelectAddrRegImm(SDValue N, SDValue &Disp, SDValue &Base);
89 inline SDValue getI32Imm(unsigned Imm) {
112 static bool isIntS32Immediate(SDValue Op, int32_t &Imm) {
121 SelectAddrRegReg(SDValue N, SDValue &Base, SDValue &Index)
[all...] |
| /external/llvm/lib/Target/SystemZ/ |
| SystemZISelDAGToDAG.cpp | 34 /// SystemZRRIAddressMode - This corresponds to rriaddr, but uses SDValue's
43 SDValue Reg;
47 SDValue IndexReg;
86 SDValue &Base, SDValue &Disp);
88 SDValue &Base, SDValue &Disp,
89 SDValue &Index);
103 inline SDValue getI8Imm(uint64_t Imm) {
109 inline SDValue getI16Imm(uint64_t Imm)
[all...] |
| SystemZISelLowering.cpp | 163 SDValue SystemZTargetLowering::LowerOperation(SDValue Op,
173 return SDValue();
234 SDValue
235 SystemZTargetLowering::LowerFormalArguments(SDValue Chain,
242 SmallVectorImpl<SDValue> &InVals)
254 SDValue
255 SystemZTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
259 const SmallVectorImpl<SDValue> &OutVals
[all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcISelDAGToDAG.cpp | 47 bool SelectADDRrr(SDValue N, SDValue &R1, SDValue &R2);
48 bool SelectADDRri(SDValue N, SDValue &Base, SDValue &Offset);
52 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
54 std::vector<SDValue> &OutOps);
73 bool SparcDAGToDAGISel::SelectADDRri(SDValue Addr,
74 SDValue &Base, SDValue &Offset)
[all...] |
| SparcISelLowering.cpp | 80 SDValue
81 SparcTargetLowering::LowerReturn(SDValue Chain,
84 const SmallVectorImpl<SDValue> &OutVals,
107 SDValue Flag;
128 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
136 SDValue RetAddrOffsetNode = DAG.getConstant(RetAddrOffset, MVT::i32);
148 SDValue
149 SparcTargetLowering::LowerFormalArguments(SDValue Chain,
154 SmallVectorImpl<SDValue> &InVals)
175 SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32)
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeTypes.cpp | 81 SDValue Res(I, i);
96 SDValue NewVal = ReplacedValues[Res];
97 DenseMap<SDValue, SDValue>::iterator I = ReplacedValues.find(NewVal);
190 DAG.setRoot(SDValue());
336 ReplaceValueWith(SDValue(N, i), SDValue(M, i));
472 SmallVector<SDValue, 8> NewOps;
475 SDValue OrigOp = N->getOperand(i);
476 SDValue Op = OrigOp
[all...] |
| DAGCombiner.cpp | 84 SDValue visit(SDNode *N);
101 SDValue CombineTo(SDNode *N, const SDValue *To, unsigned NumTo,
104 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true) {
108 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1,
110 SDValue To[] = { Res0, Res1 };
121 bool SimplifyDemandedBits(SDValue Op)
[all...] |
| LegalizeFloatTypes.cpp | 48 SDValue R = SDValue();
104 SetSoftenedFloat(SDValue(N, ResNo), R);
107 SDValue DAGTypeLegalizer::SoftenFloatRes_BITCAST(SDNode *N) {
111 SDValue DAGTypeLegalizer::SoftenFloatRes_MERGE_VALUES(SDNode *N,
113 SDValue Op = DisintegrateMERGE_VALUES(N, ResNo);
117 SDValue DAGTypeLegalizer::SoftenFloatRes_BUILD_PAIR(SDNode *N) {
126 SDValue DAGTypeLegalizer::SoftenFloatRes_ConstantFP(ConstantFPSDNode *N) {
132 SDValue DAGTypeLegalizer::SoftenFloatRes_EXTRACT_VECTOR_ELT(SDNode *N) {
133 SDValue NewOp = BitConvertVectorToIntegerVector(N->getOperand(0))
[all...] |
| LegalizeIntegerTypes.cpp | 38 SDValue Res = SDValue();
143 SetPromotedInteger(SDValue(N, ResNo), Res);
146 SDValue DAGTypeLegalizer::PromoteIntRes_MERGE_VALUES(SDNode *N,
148 SDValue Op = DisintegrateMERGE_VALUES(N, ResNo);
152 SDValue DAGTypeLegalizer::PromoteIntRes_AssertSext(SDNode *N) {
154 SDValue Op = SExtPromotedInteger(N->getOperand(0));
159 SDValue DAGTypeLegalizer::PromoteIntRes_AssertZext(SDNode *N) {
161 SDValue Op = ZExtPromotedInteger(N->getOperand(0));
166 SDValue DAGTypeLegalizer::PromoteIntRes_Atomic0(AtomicSDNode *N)
[all...] |
| LegalizeVectorTypes.cpp | 38 SDValue R = SDValue();
122 SetScalarizedVector(SDValue(N, ResNo), R);
125 SDValue DAGTypeLegalizer::ScalarizeVecRes_BinOp(SDNode *N) {
126 SDValue LHS = GetScalarizedVector(N->getOperand(0));
127 SDValue RHS = GetScalarizedVector(N->getOperand(1));
132 SDValue DAGTypeLegalizer::ScalarizeVecRes_MERGE_VALUES(SDNode *N,
134 SDValue Op = DisintegrateMERGE_VALUES(N, ResNo);
138 SDValue DAGTypeLegalizer::ScalarizeVecRes_BITCAST(SDNode *N) {
144 SDValue DAGTypeLegalizer::ScalarizeVecRes_CONVERT_RNDSAT(SDNode *N)
[all...] |
| LegalizeDAG.cpp | 59 SDValue LastCALLSEQ_END;
69 DenseMap<SDValue, SDValue> LegalizedNodes;
71 void AddLegalizedOperand(SDValue From, SDValue To) {
89 SDValue LegalizeOp(SDValue O);
91 SDValue OptimizeFloatStore(StoreSDNode *ST);
97 SDValue PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86ISelDAGToDAG.cpp | 51 /// SDValue's instead of register numbers for the leaves of the matched
60 SDValue Base_Reg;
64 SDValue IndexReg;
66 SDValue Segment;
99 void setBaseReg(SDValue Reg) {
171 virtual bool IsProfitableToFold(SDValue N, SDNode *U, SDNode *Root) const;
197 bool MatchWrapper(SDValue N, X86ISelAddressMode &AM);
198 bool MatchAddress(SDValue N, X86ISelAddressMode &AM);
199 bool MatchAddressRecursively(SDValue N, X86ISelAddressMode &AM,
201 bool MatchAddressBase(SDValue N, X86ISelAddressMode &AM)
[all...] |
| X86SelectionDAGInfo.cpp | 29 SDValue
31 SDValue Chain,
32 SDValue Dst, SDValue Src,
33 SDValue Size, unsigned Align,
40 return SDValue();
49 SDValue InFlag(0, 0);
65 std::pair<SDValue,SDValue> CallResult =
75 return SDValue();
[all...] |
| /external/llvm/lib/Target/PTX/ |
| PTXSelectionDAGInfo.cpp | 28 SDValue
30 SDValue Chain,
31 SDValue Dst, SDValue Src,
32 SDValue Size, unsigned Align,
39 return SDValue();
44 return SDValue();
49 // return SDValue();
58 SDValue TFOps[MAX_LOADS_IN_LDM];
59 SDValue Loads[MAX_LOADS_IN_LDM]
[all...] |
| PTXISelLowering.cpp | 109 SDValue PTXTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
147 SDValue PTXTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
149 SDValue Op0 = Op.getOperand(0);
150 SDValue Op1 = Op.getOperand(1);
151 SDValue Op2 = Op.getOperand(2);
169 SDValue PTXTargetLowering::
170 LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
177 SDValue targetGlobal = DAG.getTargetGlobalAddress(GV, dl, PtrVT)
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelDAGToDAG.cpp | 63 inline SDValue getI32Imm(unsigned Imm) {
69 inline SDValue getI64Imm(uint64_t Imm) {
74 inline SDValue getSmallIPtrImm(unsigned Imm) {
102 SDValue SelectCC(SDValue LHS, SDValue RHS, ISD::CondCode CC, DebugLoc dl);
106 bool SelectAddrImm(SDValue N, SDValue &Disp,
107 SDValue &Base) {
114 bool SelectAddrImmOffs(SDValue N, SDValue &Out) const
[all...] |
| PPCHazardRecognizers.h | 58 SDValue StorePtr1[4], StorePtr2[4];
80 SDValue Ptr1, SDValue Ptr2) const;
|
| PPCISelLowering.cpp | 482 static bool isFloatingPointZero(SDValue Op) {
667 SDValue PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
668 SDValue OpVal(0, 0);
677 SDValue UniquedVals[4];
684 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDValue();
690 return SDValue(); // no match.
723 return SDValue();
732 return SDValue();
735 if (OpVal.getNode() == 0) return SDValue(); // All UNDEF: use implicit def.
749 if (ValSizeInBytes < ByteSize) return SDValue();
[all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreISelLowering.cpp | 165 SDValue XCoreTargetLowering::
166 LowerOperation(SDValue Op, SelectionDAG &DAG) const {
189 return SDValue();
196 SmallVectorImpl<SDValue>&Results,
213 SDValue XCoreTargetLowering::
214 LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const
217 SDValue Cond = DAG.getNode(ISD::SETCC, dl, MVT::i32, Op.getOperand(2),
223 SDValue XCoreTargetLowering::
224 getGlobalAddressWrapper(SDValue GA, const GlobalValue *GV,
245 SDValue XCoreTargetLowering:
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| SelectionDAGISel.h | 26 class SDValue;
83 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
85 std::vector<SDValue> &OutOps) {
91 virtual bool IsProfitableToFold(SDValue N, SDNode *U, SDNode *Root) const;
97 static bool IsLegalToFold(SDValue N, SDNode *U, SDNode *Root,
202 void ReplaceUses(SDValue F, SDValue T) {
209 void ReplaceUses(const SDValue *F, const SDValue *T, unsigned Num) {
224 void SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops)
[all...] |
| /external/llvm/lib/Target/Alpha/ |
| AlphaISelDAGToDAG.cpp | 66 uint64_t get_zapImm(SDValue LHS, uint64_t Constant) const {
139 inline SDValue getI64Imm(int64_t Imm) {
153 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
155 std::vector<SDValue> &OutOps) {
156 SDValue Op0;
231 SDValue Chain = CurDAG->getEntryNode();
232 SDValue N0 = N->getOperand(0);
233 SDValue N1 = N->getOperand(1);
234 SDValue N2 = N->getOperand(2);
236 SDValue(0,0))
[all...] |
| /external/llvm/lib/Target/CellSPU/ |
| SPUISelDAGToDAG.cpp | 114 SDValue getCarryGenerateShufMask(SelectionDAG &DAG, DebugLoc dl) {
115 SmallVector<SDValue, 16 > ShufBytes;
129 SDValue getBorrowGenerateShufMask(SelectionDAG &DAG, DebugLoc dl) {
130 SmallVector<SDValue, 16 > ShufBytes;
170 inline SDValue getI32Imm(uint32_t Imm) {
175 inline SDValue getSmallIPtrImm(unsigned Imm) {
196 HandleSDNode Dummy(SDValue(bvNode, 0));
211 SDValue CPIdx = CurDAG->getConstantPool(CP, SPUtli.getPointerTy());
213 SDValue CGPoolOffset =
220 CurDAG->ReplaceAllUsesWith(SDValue(bvNode, 0), Dummy.getValue())
[all...] |
| SPUISelLowering.cpp | 60 SDValue
61 ExpandLibCall(RTLIB::Libcall LC, SDValue Op, SelectionDAG &DAG,
62 bool isSigned, SDValue &Hi, const SPUTargetLowering &TLI) {
66 SDValue InChain = DAG.getEntryNode();
79 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
85 std::pair<SDValue, SDValue> CallInfo =
557 static SDValue
558 LowerLOAD(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) {
560 SDValue the_chain = LN->getChain()
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMSelectionDAGInfo.cpp | 28 SDValue
30 SDValue Chain,
31 SDValue Dst, SDValue Src,
32 SDValue Size, unsigned Align,
39 return SDValue();
44 return SDValue();
47 return SDValue();
56 SDValue TFOps[MAX_LOADS_IN_LDM];
57 SDValue Loads[MAX_LOADS_IN_LDM]
[all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelDAGToDAG.cpp | 42 SDValue Reg;
106 bool MatchAddress(SDValue N, MSP430ISelAddressMode &AM);
107 bool MatchWrapper(SDValue N, MSP430ISelAddressMode &AM);
108 bool MatchAddressBase(SDValue N, MSP430ISelAddressMode &AM);
111 SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
112 std::vector<SDValue> &OutOps);
120 SDNode *SelectIndexedBinOp(SDNode *Op, SDValue N1, SDValue N2,
123 bool SelectAddr(SDValue Addr, SDValue &Base, SDValue &Disp)
[all...] |
