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  /external/llvm/lib/Target/XCore/
XCoreRegisterInfo.cpp 40 XCoreRegisterInfo::XCoreRegisterInfo(const TargetInstrInfo &tii)
41 : XCoreGenRegisterInfo(XCore::LR), TII(tii) {
148 New=BuildMI(MF, Old->getDebugLoc(), TII.get(Opcode))
153 New=BuildMI(MF, Old->getDebugLoc(), TII.get(Opcode), XCore::SP)
239 BuildMI(MBB, II, dl, TII.get(XCore::LDW_3r), Reg)
244 BuildMI(MBB, II, dl, TII.get(XCore::STW_3r))
250 BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l3r), Reg)
260 BuildMI(MBB, II, dl, TII.get(XCore::LDW_2rus), Reg)
265 BuildMI(MBB, II, dl, TII.get(XCore::STW_2rus)
    [all...]
  /external/llvm/lib/CodeGen/
BranchFolding.cpp 145 if (!TII->isUnpredicatedTerminator(I))
172 const TargetInstrInfo *tii,
175 if (!tii) return false;
179 TII = tii;
190 if (!TII->AnalyzeBranch(*MBB, TBB, FBB, Cond, true))
389 TII->ReplaceTailWithBranchTo(OldInst, NewDest);
402 if (!TII->isLegalToSplitMBBAt(CurMBB, BBI1))
451 const TargetInstrInfo *TII) {
458 !TII->AnalyzeBranch(*CurMBB, TBB, FBB, Cond, true))
    [all...]
ExpandPostRAPseudos.cpp 33 const TargetInstrInfo *TII;
128 MI->setDesc(TII->get(TargetOpcode::KILL));
136 TII->copyPhysReg(*MBB, MI, MI->getDebugLoc(), DstSubReg, InsReg,
163 MI->setDesc(TII->get(TargetOpcode::KILL));
173 TII->copyPhysReg(*MI->getParent(), MI, MI->getDebugLoc(),
197 TII = MF.getTarget().getInstrInfo();
214 if (TII->expandPostRAPseudo(MI)) {
IfConversion.cpp 153 const TargetInstrInfo *TII;
208 return Cycle > 0 && TII->isProfitableToIfCvt(BB, Cycle, Extra,
218 TII->isProfitableToIfCvt(TBB, TCycle, TExtra, FBB, FCycle, FExtra,
262 TII = MF.getTarget().getInstrInfo();
266 if (!TII) return false;
270 bool BFChange = BF.OptimizeFunction(MF, TII,
404 BF.OptimizeFunction(MF, TII,
430 if (!TII->ReverseBranchCondition(BBI.BrCond)) {
431 TII->RemoveBranch(*BBI.BB);
432 TII->InsertBranch(*BBI.BB, BBI.FalseBB, BBI.TrueBB, BBI.BrCond, dl)
    [all...]
  /external/llvm/lib/Target/X86/
X86VZeroUpper.cpp 42 const TargetInstrInfo *TII; // Machine instruction info.
55 TII = MF.getTarget().getInstrInfo();
99 BuildMI(*MBB, I, dl, TII->get(X86::VZEROUPPER));
X86FrameLowering.cpp 144 bool Is64Bit, const TargetInstrInfo &TII,
165 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(Opc))
175 BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
601 const X86InstrInfo &TII = *TM.getInstrInfo();
656 TII.get(getSUBriOpcode(Is64Bit, -TailCallReturnAddrDelta)),
697 BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::PUSH64r : X86::PUSH32r))
704 BuildMI(MBB, MBBI, DL, TII.get(X86::PROLOG_LABEL))
726 TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), FramePtr)
733 BuildMI(MBB, MBBI, DL, TII.get(X86::PROLOG_LABEL))
751 TII.get(Is64Bit ? X86::AND64ri32 : X86::AND32ri), StackPtr
    [all...]
  /external/llvm/lib/Target/Alpha/
AlphaRegisterInfo.h 28 const TargetInstrInfo &TII;
30 AlphaRegisterInfo(const TargetInstrInfo &tii);
  /external/llvm/lib/Target/MBlaze/
MBlazeRegisterInfo.h 40 const TargetInstrInfo &TII;
43 const TargetInstrInfo &tii);
MBlazeFrameLowering.cpp 227 const MBlazeInstrInfo &TII =
257 BuildMI(MENT, MENTI, ENTDL, TII.get(MBlaze::SWI), r)
265 BuildMI(MENT, MENTI, ENTDL, TII.get(MBlaze::SWI), MBlaze::R17)
268 BuildMI(MENT, MENTI, ENTDL, TII.get(MBlaze::SWI), MBlaze::R18)
274 BuildMI(MENT, MENTI, ENTDL, TII.get(MBlaze::MFS), MBlaze::R11)
276 BuildMI(MENT, MENTI, ENTDL, TII.get(MBlaze::SWI), MBlaze::R11)
279 BuildMI(MEXT, MEXTI, EXTDL, TII.get(MBlaze::LWI), MBlaze::R11)
281 BuildMI(MEXT, MEXTI, EXTDL, TII.get(MBlaze::MTS), MBlaze::RMSR)
286 BuildMI(MEXT, MEXTI, EXTDL, TII.get(MBlaze::LWI), MBlaze::R18)
289 BuildMI(MEXT, MEXTI, EXTDL, TII.get(MBlaze::LWI), MBlaze::R17
    [all...]
  /external/llvm/lib/Target/Mips/
MipsExpandPseudo.cpp 30 const TargetInstrInfo *TII;
34 : MachineFunctionPass(ID), TM(tm), TII(tm.getInstrInfo()) { }
90 const MCInstrDesc& Mtc1Tdd = TII->get(Mips::MTC1);
106 const MCInstrDesc& Mfc1Tdd = TII->get(Mips::MFC1);
MipsRegisterInfo.h 30 const TargetInstrInfo &TII;
32 MipsRegisterInfo(const MipsSubtarget &Subtarget, const TargetInstrInfo &tii);
  /external/llvm/lib/Target/PTX/
PTXRegisterInfo.cpp 29 const TargetInstrInfo &tii)
31 : PTXGenRegisterInfo(0), TII(tii) {
60 //MachineInstr* MI2 = BuildMI(MBB, II, dl, TII.get(PTX::LOAD_LOCAL_F32))
  /external/llvm/lib/Target/Sparc/
SparcRegisterInfo.h 30 const TargetInstrInfo &TII;
32 SparcRegisterInfo(SparcSubtarget &st, const TargetInstrInfo &tii);
FPMover.cpp 105 const TargetInstrInfo *TII = TM.getInstrInfo();
107 MI->setDesc(TII->get(SP::FMOVS));
109 MI->setDesc(TII->get(SP::FNEGS));
111 MI->setDesc(TII->get(SP::FABSS));
  /external/llvm/lib/Target/SystemZ/
SystemZRegisterInfo.h 30 const SystemZInstrInfo &TII;
32 SystemZRegisterInfo(SystemZTargetMachine &tm, const SystemZInstrInfo &tii);
SystemZFrameLowering.cpp 68 int64_t NumBytes, const TargetInstrInfo &TII) {
86 BuildMI(MBB, MBBI, DL, TII.get(Opc), SystemZ::R15D)
97 const SystemZInstrInfo &TII =
125 emitSPUpdate(MBB, MBBI, -(int64_t)NumBytes, TII);
130 BuildMI(MBB, MBBI, DL, TII.get(SystemZ::MOV64rr), SystemZ::R11D)
145 const SystemZInstrInfo &TII =
196 emitSPUpdate(MBB, MBBI, NumBytes, TII);
236 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
265 BuildMI(MBB, MI, DL, TII.get((LowReg == HighReg ?
291 TII.storeRegToStackSlot(MBB, MI, Reg, true, CSI[i].getFrameIdx()
    [all...]
  /external/llvm/lib/Target/Blackfin/
BlackfinISelDAGToDAG.cpp 140 const BlackfinInstrInfo &TII = getInstrInfo();
149 const MCInstrDesc &DefMCID = TII.get(NI->getMachineOpcode());
157 TII.getRegClass(DefMCID, UI.getUse().getResNo(), TRI);
159 const MCInstrDesc &UseMCID = TII.get(UI->getMachineOpcode());
163 TII.getRegClass(UseMCID, UseMCID.getNumDefs()+UI.getOperandNo(), TRI);
BlackfinRegisterInfo.h 31 const TargetInstrInfo &TII;
33 BlackfinRegisterInfo(BlackfinSubtarget &st, const TargetInstrInfo &tii);
  /external/llvm/lib/Target/ARM/
ARMFrameLowering.cpp 81 const ARMBaseInstrInfo &TII,
109 DebugLoc dl, const ARMBaseInstrInfo &TII,
113 ARMCC::AL, 0, TII, MIFlags);
116 ARMCC::AL, 0, TII, MIFlags);
126 const ARMBaseInstrInfo &TII =
144 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -VARegSaveSize,
149 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes,
200 BuildMI(MBB, MBBI, dl, TII.get(ADDriOpc), FramePtr)
232 emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes,
262 TII.get(ARM::BICri), ARM::SP
    [all...]
ARMFastISel.cpp 88 const TargetInstrInfo &TII;
100 TII(*TM.getInstrInfo()),
263 if (TII.isPredicable(MI) || isARMNEONPred(MI))
281 const MCInstrDesc &II = TII.get(MachineInstOpcode);
291 const MCInstrDesc &II = TII.get(MachineInstOpcode);
300 TII.get(TargetOpcode::COPY), ResultReg)
311 const MCInstrDesc &II = TII.get(MachineInstOpcode);
322 TII.get(TargetOpcode::COPY), ResultReg)
334 const MCInstrDesc &II = TII.get(MachineInstOpcode);
347 TII.get(TargetOpcode::COPY), ResultReg
    [all...]
Thumb2RegisterInfo.cpp 27 Thumb2RegisterInfo::Thumb2RegisterInfo(const ARMBaseInstrInfo &tii,
29 : ARMBaseRegisterInfo(tii, sti) {
48 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2LDRpci))
  /external/llvm/include/llvm/CodeGen/
MachineSSAUpdater.h 52 const TargetInstrInfo *TII;
  /external/llvm/lib/Target/CellSPU/
SPURegisterInfo.h 31 const TargetInstrInfo &TII;
37 SPURegisterInfo(const SPUSubtarget &subtarget, const TargetInstrInfo &tii);
  /external/llvm/lib/Target/MSP430/
MSP430RegisterInfo.h 30 const TargetInstrInfo &TII;
36 MSP430RegisterInfo(MSP430TargetMachine &tm, const TargetInstrInfo &tii);
  /external/llvm/lib/Target/PowerPC/
PPCRegisterInfo.h 32 const TargetInstrInfo &TII;
34 PPCRegisterInfo(const PPCSubtarget &SubTarget, const TargetInstrInfo &tii);

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