1 //=======- X86FrameLowering.cpp - X86 Frame Information --------*- C++ -*-====// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the X86 implementation of TargetFrameLowering class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "X86FrameLowering.h" 15 #include "X86InstrBuilder.h" 16 #include "X86InstrInfo.h" 17 #include "X86MachineFunctionInfo.h" 18 #include "X86Subtarget.h" 19 #include "X86TargetMachine.h" 20 #include "llvm/Function.h" 21 #include "llvm/CodeGen/MachineFrameInfo.h" 22 #include "llvm/CodeGen/MachineFunction.h" 23 #include "llvm/CodeGen/MachineInstrBuilder.h" 24 #include "llvm/CodeGen/MachineModuleInfo.h" 25 #include "llvm/CodeGen/MachineRegisterInfo.h" 26 #include "llvm/MC/MCAsmInfo.h" 27 #include "llvm/MC/MCSymbol.h" 28 #include "llvm/Target/TargetData.h" 29 #include "llvm/Target/TargetOptions.h" 30 #include "llvm/Support/CommandLine.h" 31 #include "llvm/ADT/SmallSet.h" 32 33 using namespace llvm; 34 35 // FIXME: completely move here. 36 extern cl::opt<bool> ForceStackAlign; 37 38 bool X86FrameLowering::hasReservedCallFrame(const MachineFunction &MF) const { 39 return !MF.getFrameInfo()->hasVarSizedObjects(); 40 } 41 42 /// hasFP - Return true if the specified function should have a dedicated frame 43 /// pointer register. This is true if the function has variable sized allocas 44 /// or if frame pointer elimination is disabled. 45 bool X86FrameLowering::hasFP(const MachineFunction &MF) const { 46 const MachineFrameInfo *MFI = MF.getFrameInfo(); 47 const MachineModuleInfo &MMI = MF.getMMI(); 48 const TargetRegisterInfo *RI = TM.getRegisterInfo(); 49 50 return (DisableFramePointerElim(MF) || 51 RI->needsStackRealignment(MF) || 52 MFI->hasVarSizedObjects() || 53 MFI->isFrameAddressTaken() || 54 MF.getInfo<X86MachineFunctionInfo>()->getForceFramePointer() || 55 MMI.callsUnwindInit()); 56 } 57 58 static unsigned getSUBriOpcode(unsigned is64Bit, int64_t Imm) { 59 if (is64Bit) { 60 if (isInt<8>(Imm)) 61 return X86::SUB64ri8; 62 return X86::SUB64ri32; 63 } else { 64 if (isInt<8>(Imm)) 65 return X86::SUB32ri8; 66 return X86::SUB32ri; 67 } 68 } 69 70 static unsigned getADDriOpcode(unsigned is64Bit, int64_t Imm) { 71 if (is64Bit) { 72 if (isInt<8>(Imm)) 73 return X86::ADD64ri8; 74 return X86::ADD64ri32; 75 } else { 76 if (isInt<8>(Imm)) 77 return X86::ADD32ri8; 78 return X86::ADD32ri; 79 } 80 } 81 82 /// findDeadCallerSavedReg - Return a caller-saved register that isn't live 83 /// when it reaches the "return" instruction. We can then pop a stack object 84 /// to this register without worry about clobbering it. 85 static unsigned findDeadCallerSavedReg(MachineBasicBlock &MBB, 86 MachineBasicBlock::iterator &MBBI, 87 const TargetRegisterInfo &TRI, 88 bool Is64Bit) { 89 const MachineFunction *MF = MBB.getParent(); 90 const Function *F = MF->getFunction(); 91 if (!F || MF->getMMI().callsEHReturn()) 92 return 0; 93 94 static const unsigned CallerSavedRegs32Bit[] = { 95 X86::EAX, X86::EDX, X86::ECX, 0 96 }; 97 98 static const unsigned CallerSavedRegs64Bit[] = { 99 X86::RAX, X86::RDX, X86::RCX, X86::RSI, X86::RDI, 100 X86::R8, X86::R9, X86::R10, X86::R11, 0 101 }; 102 103 unsigned Opc = MBBI->getOpcode(); 104 switch (Opc) { 105 default: return 0; 106 case X86::RET: 107 case X86::RETI: 108 case X86::TCRETURNdi: 109 case X86::TCRETURNri: 110 case X86::TCRETURNmi: 111 case X86::TCRETURNdi64: 112 case X86::TCRETURNri64: 113 case X86::TCRETURNmi64: 114 case X86::EH_RETURN: 115 case X86::EH_RETURN64: { 116 SmallSet<unsigned, 8> Uses; 117 for (unsigned i = 0, e = MBBI->getNumOperands(); i != e; ++i) { 118 MachineOperand &MO = MBBI->getOperand(i); 119 if (!MO.isReg() || MO.isDef()) 120 continue; 121 unsigned Reg = MO.getReg(); 122 if (!Reg) 123 continue; 124 for (const unsigned *AsI = TRI.getOverlaps(Reg); *AsI; ++AsI) 125 Uses.insert(*AsI); 126 } 127 128 const unsigned *CS = Is64Bit ? CallerSavedRegs64Bit : CallerSavedRegs32Bit; 129 for (; *CS; ++CS) 130 if (!Uses.count(*CS)) 131 return *CS; 132 } 133 } 134 135 return 0; 136 } 137 138 139 /// emitSPUpdate - Emit a series of instructions to increment / decrement the 140 /// stack pointer by a constant value. 141 static 142 void emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, 143 unsigned StackPtr, int64_t NumBytes, 144 bool Is64Bit, const TargetInstrInfo &TII, 145 const TargetRegisterInfo &TRI) { 146 bool isSub = NumBytes < 0; 147 uint64_t Offset = isSub ? -NumBytes : NumBytes; 148 unsigned Opc = isSub ? 149 getSUBriOpcode(Is64Bit, Offset) : 150 getADDriOpcode(Is64Bit, Offset); 151 uint64_t Chunk = (1LL << 31) - 1; 152 DebugLoc DL = MBB.findDebugLoc(MBBI); 153 154 while (Offset) { 155 uint64_t ThisVal = (Offset > Chunk) ? Chunk : Offset; 156 if (ThisVal == (Is64Bit ? 8 : 4)) { 157 // Use push / pop instead. 158 unsigned Reg = isSub 159 ? (unsigned)(Is64Bit ? X86::RAX : X86::EAX) 160 : findDeadCallerSavedReg(MBB, MBBI, TRI, Is64Bit); 161 if (Reg) { 162 Opc = isSub 163 ? (Is64Bit ? X86::PUSH64r : X86::PUSH32r) 164 : (Is64Bit ? X86::POP64r : X86::POP32r); 165 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(Opc)) 166 .addReg(Reg, getDefRegState(!isSub) | getUndefRegState(isSub)); 167 if (isSub) 168 MI->setFlag(MachineInstr::FrameSetup); 169 Offset -= ThisVal; 170 continue; 171 } 172 } 173 174 MachineInstr *MI = 175 BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr) 176 .addReg(StackPtr) 177 .addImm(ThisVal); 178 if (isSub) 179 MI->setFlag(MachineInstr::FrameSetup); 180 MI->getOperand(3).setIsDead(); // The EFLAGS implicit def is dead. 181 Offset -= ThisVal; 182 } 183 } 184 185 /// mergeSPUpdatesUp - Merge two stack-manipulating instructions upper iterator. 186 static 187 void mergeSPUpdatesUp(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, 188 unsigned StackPtr, uint64_t *NumBytes = NULL) { 189 if (MBBI == MBB.begin()) return; 190 191 MachineBasicBlock::iterator PI = prior(MBBI); 192 unsigned Opc = PI->getOpcode(); 193 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 || 194 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) && 195 PI->getOperand(0).getReg() == StackPtr) { 196 if (NumBytes) 197 *NumBytes += PI->getOperand(2).getImm(); 198 MBB.erase(PI); 199 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 || 200 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) && 201 PI->getOperand(0).getReg() == StackPtr) { 202 if (NumBytes) 203 *NumBytes -= PI->getOperand(2).getImm(); 204 MBB.erase(PI); 205 } 206 } 207 208 /// mergeSPUpdatesDown - Merge two stack-manipulating instructions lower iterator. 209 static 210 void mergeSPUpdatesDown(MachineBasicBlock &MBB, 211 MachineBasicBlock::iterator &MBBI, 212 unsigned StackPtr, uint64_t *NumBytes = NULL) { 213 // FIXME: THIS ISN'T RUN!!! 214 return; 215 216 if (MBBI == MBB.end()) return; 217 218 MachineBasicBlock::iterator NI = llvm::next(MBBI); 219 if (NI == MBB.end()) return; 220 221 unsigned Opc = NI->getOpcode(); 222 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 || 223 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) && 224 NI->getOperand(0).getReg() == StackPtr) { 225 if (NumBytes) 226 *NumBytes -= NI->getOperand(2).getImm(); 227 MBB.erase(NI); 228 MBBI = NI; 229 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 || 230 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) && 231 NI->getOperand(0).getReg() == StackPtr) { 232 if (NumBytes) 233 *NumBytes += NI->getOperand(2).getImm(); 234 MBB.erase(NI); 235 MBBI = NI; 236 } 237 } 238 239 /// mergeSPUpdates - Checks the instruction before/after the passed 240 /// instruction. If it is an ADD/SUB instruction it is deleted argument and the 241 /// stack adjustment is returned as a positive value for ADD and a negative for 242 /// SUB. 243 static int mergeSPUpdates(MachineBasicBlock &MBB, 244 MachineBasicBlock::iterator &MBBI, 245 unsigned StackPtr, 246 bool doMergeWithPrevious) { 247 if ((doMergeWithPrevious && MBBI == MBB.begin()) || 248 (!doMergeWithPrevious && MBBI == MBB.end())) 249 return 0; 250 251 MachineBasicBlock::iterator PI = doMergeWithPrevious ? prior(MBBI) : MBBI; 252 MachineBasicBlock::iterator NI = doMergeWithPrevious ? 0 : llvm::next(MBBI); 253 unsigned Opc = PI->getOpcode(); 254 int Offset = 0; 255 256 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 || 257 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) && 258 PI->getOperand(0).getReg() == StackPtr){ 259 Offset += PI->getOperand(2).getImm(); 260 MBB.erase(PI); 261 if (!doMergeWithPrevious) MBBI = NI; 262 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 || 263 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) && 264 PI->getOperand(0).getReg() == StackPtr) { 265 Offset -= PI->getOperand(2).getImm(); 266 MBB.erase(PI); 267 if (!doMergeWithPrevious) MBBI = NI; 268 } 269 270 return Offset; 271 } 272 273 static bool isEAXLiveIn(MachineFunction &MF) { 274 for (MachineRegisterInfo::livein_iterator II = MF.getRegInfo().livein_begin(), 275 EE = MF.getRegInfo().livein_end(); II != EE; ++II) { 276 unsigned Reg = II->first; 277 278 if (Reg == X86::EAX || Reg == X86::AX || 279 Reg == X86::AH || Reg == X86::AL) 280 return true; 281 } 282 283 return false; 284 } 285 286 void X86FrameLowering::emitCalleeSavedFrameMoves(MachineFunction &MF, 287 MCSymbol *Label, 288 unsigned FramePtr) const { 289 MachineFrameInfo *MFI = MF.getFrameInfo(); 290 MachineModuleInfo &MMI = MF.getMMI(); 291 292 // Add callee saved registers to move list. 293 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo(); 294 if (CSI.empty()) return; 295 296 std::vector<MachineMove> &Moves = MMI.getFrameMoves(); 297 const TargetData *TD = TM.getTargetData(); 298 bool HasFP = hasFP(MF); 299 300 // Calculate amount of bytes used for return address storing. 301 int stackGrowth = -TD->getPointerSize(); 302 303 // FIXME: This is dirty hack. The code itself is pretty mess right now. 304 // It should be rewritten from scratch and generalized sometimes. 305 306 // Determine maximum offset (minimum due to stack growth). 307 int64_t MaxOffset = 0; 308 for (std::vector<CalleeSavedInfo>::const_iterator 309 I = CSI.begin(), E = CSI.end(); I != E; ++I) 310 MaxOffset = std::min(MaxOffset, 311 MFI->getObjectOffset(I->getFrameIdx())); 312 313 // Calculate offsets. 314 int64_t saveAreaOffset = (HasFP ? 3 : 2) * stackGrowth; 315 for (std::vector<CalleeSavedInfo>::const_iterator 316 I = CSI.begin(), E = CSI.end(); I != E; ++I) { 317 int64_t Offset = MFI->getObjectOffset(I->getFrameIdx()); 318 unsigned Reg = I->getReg(); 319 Offset = MaxOffset - Offset + saveAreaOffset; 320 321 // Don't output a new machine move if we're re-saving the frame 322 // pointer. This happens when the PrologEpilogInserter has inserted an extra 323 // "PUSH" of the frame pointer -- the "emitPrologue" method automatically 324 // generates one when frame pointers are used. If we generate a "machine 325 // move" for this extra "PUSH", the linker will lose track of the fact that 326 // the frame pointer should have the value of the first "PUSH" when it's 327 // trying to unwind. 328 // 329 // FIXME: This looks inelegant. It's possibly correct, but it's covering up 330 // another bug. I.e., one where we generate a prolog like this: 331 // 332 // pushl %ebp 333 // movl %esp, %ebp 334 // pushl %ebp 335 // pushl %esi 336 // ... 337 // 338 // The immediate re-push of EBP is unnecessary. At the least, it's an 339 // optimization bug. EBP can be used as a scratch register in certain 340 // cases, but probably not when we have a frame pointer. 341 if (HasFP && FramePtr == Reg) 342 continue; 343 344 MachineLocation CSDst(MachineLocation::VirtualFP, Offset); 345 MachineLocation CSSrc(Reg); 346 Moves.push_back(MachineMove(Label, CSDst, CSSrc)); 347 } 348 } 349 350 /// getCompactUnwindRegNum - Get the compact unwind number for a given 351 /// register. The number corresponds to the enum lists in 352 /// compact_unwind_encoding.h. 353 static int getCompactUnwindRegNum(const unsigned *CURegs, unsigned Reg) { 354 int Idx = 1; 355 for (; *CURegs; ++CURegs, ++Idx) 356 if (*CURegs == Reg) 357 return Idx; 358 359 return -1; 360 } 361 362 /// encodeCompactUnwindRegistersWithoutFrame - Create the permutation encoding 363 /// used with frameless stacks. It is passed the number of registers to be saved 364 /// and an array of the registers saved. 365 static uint32_t encodeCompactUnwindRegistersWithoutFrame(unsigned SavedRegs[6], 366 unsigned RegCount, 367 bool Is64Bit) { 368 // The saved registers are numbered from 1 to 6. In order to encode the order 369 // in which they were saved, we re-number them according to their place in the 370 // register order. The re-numbering is relative to the last re-numbered 371 // register. E.g., if we have registers {6, 2, 4, 5} saved in that order: 372 // 373 // Orig Re-Num 374 // ---- ------ 375 // 6 6 376 // 2 2 377 // 4 3 378 // 5 3 379 // 380 static const unsigned CU32BitRegs[] = { 381 X86::EBX, X86::ECX, X86::EDX, X86::EDI, X86::ESI, X86::EBP, 0 382 }; 383 static const unsigned CU64BitRegs[] = { 384 X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0 385 }; 386 const unsigned *CURegs = (Is64Bit ? CU64BitRegs : CU32BitRegs); 387 388 uint32_t RenumRegs[6]; 389 for (unsigned i = 6 - RegCount; i < 6; ++i) { 390 int CUReg = getCompactUnwindRegNum(CURegs, SavedRegs[i]); 391 if (CUReg == -1) return ~0U; 392 SavedRegs[i] = CUReg; 393 394 unsigned Countless = 0; 395 for (unsigned j = 6 - RegCount; j < i; ++j) 396 if (SavedRegs[j] < SavedRegs[i]) 397 ++Countless; 398 399 RenumRegs[i] = SavedRegs[i] - Countless - 1; 400 } 401 402 // Take the renumbered values and encode them into a 10-bit number. 403 uint32_t permutationEncoding = 0; 404 switch (RegCount) { 405 case 6: 406 permutationEncoding |= 120 * RenumRegs[0] + 24 * RenumRegs[1] 407 + 6 * RenumRegs[2] + 2 * RenumRegs[3] 408 + RenumRegs[4]; 409 break; 410 case 5: 411 permutationEncoding |= 120 * RenumRegs[1] + 24 * RenumRegs[2] 412 + 6 * RenumRegs[3] + 2 * RenumRegs[4] 413 + RenumRegs[5]; 414 break; 415 case 4: 416 permutationEncoding |= 60 * RenumRegs[2] + 12 * RenumRegs[3] 417 + 3 * RenumRegs[4] + RenumRegs[5]; 418 break; 419 case 3: 420 permutationEncoding |= 20 * RenumRegs[3] + 4 * RenumRegs[4] 421 + RenumRegs[5]; 422 break; 423 case 2: 424 permutationEncoding |= 5 * RenumRegs[4] + RenumRegs[5]; 425 break; 426 case 1: 427 permutationEncoding |= RenumRegs[5]; 428 break; 429 } 430 431 assert((permutationEncoding & 0x3FF) == permutationEncoding && 432 "Invalid compact register encoding!"); 433 return permutationEncoding; 434 } 435 436 /// encodeCompactUnwindRegistersWithFrame - Return the registers encoded for a 437 /// compact encoding with a frame pointer. 438 static uint32_t encodeCompactUnwindRegistersWithFrame(unsigned SavedRegs[6], 439 bool Is64Bit) { 440 static const unsigned CU32BitRegs[] = { 441 X86::EBX, X86::ECX, X86::EDX, X86::EDI, X86::ESI, X86::EBP, 0 442 }; 443 static const unsigned CU64BitRegs[] = { 444 X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0 445 }; 446 const unsigned *CURegs = (Is64Bit ? CU64BitRegs : CU32BitRegs); 447 448 // Encode the registers in the order they were saved, 3-bits per register. The 449 // registers are numbered from 1 to 6. 450 uint32_t RegEnc = 0; 451 for (int I = 5; I >= 0; --I) { 452 unsigned Reg = SavedRegs[I]; 453 if (Reg == 0) break; 454 int CURegNum = getCompactUnwindRegNum(CURegs, Reg); 455 if (CURegNum == -1) 456 return ~0U; 457 RegEnc |= (CURegNum & 0x7) << (5 - I); 458 } 459 460 assert((RegEnc & 0x7FFF) == RegEnc && "Invalid compact register encoding!"); 461 return RegEnc; 462 } 463 464 uint32_t X86FrameLowering::getCompactUnwindEncoding(MachineFunction &MF) const { 465 const X86RegisterInfo *RegInfo = TM.getRegisterInfo(); 466 unsigned FramePtr = RegInfo->getFrameRegister(MF); 467 unsigned StackPtr = RegInfo->getStackRegister(); 468 469 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>(); 470 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta(); 471 472 bool Is64Bit = STI.is64Bit(); 473 bool HasFP = hasFP(MF); 474 475 unsigned SavedRegs[6] = { 0, 0, 0, 0, 0, 0 }; 476 int SavedRegIdx = 6; 477 478 unsigned OffsetSize = (Is64Bit ? 8 : 4); 479 480 unsigned PushInstr = (Is64Bit ? X86::PUSH64r : X86::PUSH32r); 481 unsigned PushInstrSize = 1; 482 unsigned MoveInstr = (Is64Bit ? X86::MOV64rr : X86::MOV32rr); 483 unsigned MoveInstrSize = (Is64Bit ? 3 : 2); 484 unsigned SubtractInstr = getSUBriOpcode(Is64Bit, -TailCallReturnAddrDelta); 485 unsigned SubtractInstrIdx = (Is64Bit ? 3 : 2); 486 487 unsigned StackDivide = (Is64Bit ? 8 : 4); 488 489 unsigned InstrOffset = 0; 490 unsigned CFAOffset = 0; 491 unsigned StackAdjust = 0; 492 493 MachineBasicBlock &MBB = MF.front(); // Prologue is in entry BB. 494 bool ExpectEnd = false; 495 for (MachineBasicBlock::iterator 496 MBBI = MBB.begin(), MBBE = MBB.end(); MBBI != MBBE; ++MBBI) { 497 MachineInstr &MI = *MBBI; 498 unsigned Opc = MI.getOpcode(); 499 if (Opc == X86::PROLOG_LABEL) continue; 500 if (!MI.getFlag(MachineInstr::FrameSetup)) break; 501 502 // We don't exect any more prolog instructions. 503 if (ExpectEnd) return 0; 504 505 if (Opc == PushInstr) { 506 // If there are too many saved registers, we cannot use compact encoding. 507 if (--SavedRegIdx < 0) return 0; 508 509 SavedRegs[SavedRegIdx] = MI.getOperand(0).getReg(); 510 CFAOffset += OffsetSize; 511 InstrOffset += PushInstrSize; 512 } else if (Opc == MoveInstr) { 513 unsigned SrcReg = MI.getOperand(1).getReg(); 514 unsigned DstReg = MI.getOperand(0).getReg(); 515 516 if (DstReg != FramePtr || SrcReg != StackPtr) 517 return 0; 518 519 CFAOffset = 0; 520 memset(SavedRegs, 0, sizeof(SavedRegs)); 521 InstrOffset += MoveInstrSize; 522 } else if (Opc == SubtractInstr) { 523 if (StackAdjust) 524 // We all ready have a stack pointer adjustment. 525 return 0; 526 527 if (!MI.getOperand(0).isReg() || 528 MI.getOperand(0).getReg() != MI.getOperand(1).getReg() || 529 MI.getOperand(0).getReg() != StackPtr || !MI.getOperand(2).isImm()) 530 // We need this to be a stack adjustment pointer. Something like: 531 // 532 // %RSP<def> = SUB64ri8 %RSP, 48 533 return 0; 534 535 StackAdjust = MI.getOperand(2).getImm() / StackDivide; 536 SubtractInstrIdx += InstrOffset; 537 ExpectEnd = true; 538 } 539 } 540 541 // Encode that we are using EBP/RBP as the frame pointer. 542 uint32_t CompactUnwindEncoding = 0; 543 CFAOffset /= StackDivide; 544 if (HasFP) { 545 if ((CFAOffset & 0xFF) != CFAOffset) 546 // Offset was too big for compact encoding. 547 return 0; 548 549 // Get the encoding of the saved registers when we have a frame pointer. 550 uint32_t RegEnc = encodeCompactUnwindRegistersWithFrame(SavedRegs, Is64Bit); 551 if (RegEnc == ~0U) 552 return 0; 553 554 CompactUnwindEncoding |= 0x01000000; 555 CompactUnwindEncoding |= (CFAOffset & 0xFF) << 16; 556 CompactUnwindEncoding |= RegEnc & 0x7FFF; 557 } else { 558 unsigned FullOffset = CFAOffset + StackAdjust; 559 if ((FullOffset & 0xFF) == FullOffset) { 560 // Frameless stack. 561 CompactUnwindEncoding |= 0x02000000; 562 CompactUnwindEncoding |= (FullOffset & 0xFF) << 16; 563 } else { 564 if ((CFAOffset & 0x7) != CFAOffset) 565 // The extra stack adjustments are too big for us to handle. 566 return 0; 567 568 // Frameless stack with an offset too large for us to encode compactly. 569 CompactUnwindEncoding |= 0x03000000; 570 571 // Encode the offset to the nnnnnn value in the 'subl $nnnnnn, ESP' 572 // instruction. 573 CompactUnwindEncoding |= (SubtractInstrIdx & 0xFF) << 16; 574 575 // Encode any extra stack stack changes (done via push instructions). 576 CompactUnwindEncoding |= (CFAOffset & 0x7) << 13; 577 } 578 579 // Get the encoding of the saved registers when we don't have a frame 580 // pointer. 581 uint32_t RegEnc = encodeCompactUnwindRegistersWithoutFrame(SavedRegs, 582 6 - SavedRegIdx, 583 Is64Bit); 584 if (RegEnc == ~0U) return 0; 585 CompactUnwindEncoding |= RegEnc & 0x3FF; 586 } 587 588 return CompactUnwindEncoding; 589 } 590 591 /// emitPrologue - Push callee-saved registers onto the stack, which 592 /// automatically adjust the stack pointer. Adjust the stack pointer to allocate 593 /// space for local variables. Also emit labels used by the exception handler to 594 /// generate the exception handling frames. 595 void X86FrameLowering::emitPrologue(MachineFunction &MF) const { 596 MachineBasicBlock &MBB = MF.front(); // Prologue goes in entry BB. 597 MachineBasicBlock::iterator MBBI = MBB.begin(); 598 MachineFrameInfo *MFI = MF.getFrameInfo(); 599 const Function *Fn = MF.getFunction(); 600 const X86RegisterInfo *RegInfo = TM.getRegisterInfo(); 601 const X86InstrInfo &TII = *TM.getInstrInfo(); 602 MachineModuleInfo &MMI = MF.getMMI(); 603 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>(); 604 bool needsFrameMoves = MMI.hasDebugInfo() || 605 Fn->needsUnwindTableEntry(); 606 uint64_t MaxAlign = MFI->getMaxAlignment(); // Desired stack alignment. 607 uint64_t StackSize = MFI->getStackSize(); // Number of bytes to allocate. 608 bool HasFP = hasFP(MF); 609 bool Is64Bit = STI.is64Bit(); 610 bool IsWin64 = STI.isTargetWin64(); 611 unsigned StackAlign = getStackAlignment(); 612 unsigned SlotSize = RegInfo->getSlotSize(); 613 unsigned FramePtr = RegInfo->getFrameRegister(MF); 614 unsigned StackPtr = RegInfo->getStackRegister(); 615 DebugLoc DL; 616 617 // If we're forcing a stack realignment we can't rely on just the frame 618 // info, we need to know the ABI stack alignment as well in case we 619 // have a call out. Otherwise just make sure we have some alignment - we'll 620 // go with the minimum SlotSize. 621 if (ForceStackAlign) { 622 if (MFI->hasCalls()) 623 MaxAlign = (StackAlign > MaxAlign) ? StackAlign : MaxAlign; 624 else if (MaxAlign < SlotSize) 625 MaxAlign = SlotSize; 626 } 627 628 // Add RETADDR move area to callee saved frame size. 629 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta(); 630 if (TailCallReturnAddrDelta < 0) 631 X86FI->setCalleeSavedFrameSize( 632 X86FI->getCalleeSavedFrameSize() - TailCallReturnAddrDelta); 633 634 // If this is x86-64 and the Red Zone is not disabled, if we are a leaf 635 // function, and use up to 128 bytes of stack space, don't have a frame 636 // pointer, calls, or dynamic alloca then we do not need to adjust the 637 // stack pointer (we fit in the Red Zone). 638 if (Is64Bit && !Fn->hasFnAttr(Attribute::NoRedZone) && 639 !RegInfo->needsStackRealignment(MF) && 640 !MFI->hasVarSizedObjects() && // No dynamic alloca. 641 !MFI->adjustsStack() && // No calls. 642 !IsWin64 && // Win64 has no Red Zone 643 !EnableSegmentedStacks) { // Regular stack 644 uint64_t MinSize = X86FI->getCalleeSavedFrameSize(); 645 if (HasFP) MinSize += SlotSize; 646 StackSize = std::max(MinSize, StackSize > 128 ? StackSize - 128 : 0); 647 MFI->setStackSize(StackSize); 648 } 649 650 // Insert stack pointer adjustment for later moving of return addr. Only 651 // applies to tail call optimized functions where the callee argument stack 652 // size is bigger than the callers. 653 if (TailCallReturnAddrDelta < 0) { 654 MachineInstr *MI = 655 BuildMI(MBB, MBBI, DL, 656 TII.get(getSUBriOpcode(Is64Bit, -TailCallReturnAddrDelta)), 657 StackPtr) 658 .addReg(StackPtr) 659 .addImm(-TailCallReturnAddrDelta) 660 .setMIFlag(MachineInstr::FrameSetup); 661 MI->getOperand(3).setIsDead(); // The EFLAGS implicit def is dead. 662 } 663 664 // Mapping for machine moves: 665 // 666 // DST: VirtualFP AND 667 // SRC: VirtualFP => DW_CFA_def_cfa_offset 668 // ELSE => DW_CFA_def_cfa 669 // 670 // SRC: VirtualFP AND 671 // DST: Register => DW_CFA_def_cfa_register 672 // 673 // ELSE 674 // OFFSET < 0 => DW_CFA_offset_extended_sf 675 // REG < 64 => DW_CFA_offset + Reg 676 // ELSE => DW_CFA_offset_extended 677 678 std::vector<MachineMove> &Moves = MMI.getFrameMoves(); 679 const TargetData *TD = MF.getTarget().getTargetData(); 680 uint64_t NumBytes = 0; 681 int stackGrowth = -TD->getPointerSize(); 682 683 if (HasFP) { 684 // Calculate required stack adjustment. 685 uint64_t FrameSize = StackSize - SlotSize; 686 if (RegInfo->needsStackRealignment(MF)) 687 FrameSize = (FrameSize + MaxAlign - 1) / MaxAlign * MaxAlign; 688 689 NumBytes = FrameSize - X86FI->getCalleeSavedFrameSize(); 690 691 // Get the offset of the stack slot for the EBP register, which is 692 // guaranteed to be the last slot by processFunctionBeforeFrameFinalized. 693 // Update the frame offset adjustment. 694 MFI->setOffsetAdjustment(-NumBytes); 695 696 // Save EBP/RBP into the appropriate stack slot. 697 BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::PUSH64r : X86::PUSH32r)) 698 .addReg(FramePtr, RegState::Kill) 699 .setMIFlag(MachineInstr::FrameSetup); 700 701 if (needsFrameMoves) { 702 // Mark the place where EBP/RBP was saved. 703 MCSymbol *FrameLabel = MMI.getContext().CreateTempSymbol(); 704 BuildMI(MBB, MBBI, DL, TII.get(X86::PROLOG_LABEL)) 705 .addSym(FrameLabel); 706 707 // Define the current CFA rule to use the provided offset. 708 if (StackSize) { 709 MachineLocation SPDst(MachineLocation::VirtualFP); 710 MachineLocation SPSrc(MachineLocation::VirtualFP, 2 * stackGrowth); 711 Moves.push_back(MachineMove(FrameLabel, SPDst, SPSrc)); 712 } else { 713 MachineLocation SPDst(StackPtr); 714 MachineLocation SPSrc(StackPtr, stackGrowth); 715 Moves.push_back(MachineMove(FrameLabel, SPDst, SPSrc)); 716 } 717 718 // Change the rule for the FramePtr to be an "offset" rule. 719 MachineLocation FPDst(MachineLocation::VirtualFP, 2 * stackGrowth); 720 MachineLocation FPSrc(FramePtr); 721 Moves.push_back(MachineMove(FrameLabel, FPDst, FPSrc)); 722 } 723 724 // Update EBP with the new base value. 725 BuildMI(MBB, MBBI, DL, 726 TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), FramePtr) 727 .addReg(StackPtr) 728 .setMIFlag(MachineInstr::FrameSetup); 729 730 if (needsFrameMoves) { 731 // Mark effective beginning of when frame pointer becomes valid. 732 MCSymbol *FrameLabel = MMI.getContext().CreateTempSymbol(); 733 BuildMI(MBB, MBBI, DL, TII.get(X86::PROLOG_LABEL)) 734 .addSym(FrameLabel); 735 736 // Define the current CFA to use the EBP/RBP register. 737 MachineLocation FPDst(FramePtr); 738 MachineLocation FPSrc(MachineLocation::VirtualFP); 739 Moves.push_back(MachineMove(FrameLabel, FPDst, FPSrc)); 740 } 741 742 // Mark the FramePtr as live-in in every block except the entry. 743 for (MachineFunction::iterator I = llvm::next(MF.begin()), E = MF.end(); 744 I != E; ++I) 745 I->addLiveIn(FramePtr); 746 747 // Realign stack 748 if (RegInfo->needsStackRealignment(MF)) { 749 MachineInstr *MI = 750 BuildMI(MBB, MBBI, DL, 751 TII.get(Is64Bit ? X86::AND64ri32 : X86::AND32ri), StackPtr) 752 .addReg(StackPtr) 753 .addImm(-MaxAlign) 754 .setMIFlag(MachineInstr::FrameSetup); 755 756 // The EFLAGS implicit def is dead. 757 MI->getOperand(3).setIsDead(); 758 } 759 } else { 760 NumBytes = StackSize - X86FI->getCalleeSavedFrameSize(); 761 } 762 763 // Skip the callee-saved push instructions. 764 bool PushedRegs = false; 765 int StackOffset = 2 * stackGrowth; 766 767 while (MBBI != MBB.end() && 768 (MBBI->getOpcode() == X86::PUSH32r || 769 MBBI->getOpcode() == X86::PUSH64r)) { 770 PushedRegs = true; 771 MBBI->setFlag(MachineInstr::FrameSetup); 772 ++MBBI; 773 774 if (!HasFP && needsFrameMoves) { 775 // Mark callee-saved push instruction. 776 MCSymbol *Label = MMI.getContext().CreateTempSymbol(); 777 BuildMI(MBB, MBBI, DL, TII.get(X86::PROLOG_LABEL)).addSym(Label); 778 779 // Define the current CFA rule to use the provided offset. 780 unsigned Ptr = StackSize ? MachineLocation::VirtualFP : StackPtr; 781 MachineLocation SPDst(Ptr); 782 MachineLocation SPSrc(Ptr, StackOffset); 783 Moves.push_back(MachineMove(Label, SPDst, SPSrc)); 784 StackOffset += stackGrowth; 785 } 786 } 787 788 DL = MBB.findDebugLoc(MBBI); 789 790 // If there is an SUB32ri of ESP immediately before this instruction, merge 791 // the two. This can be the case when tail call elimination is enabled and 792 // the callee has more arguments then the caller. 793 NumBytes -= mergeSPUpdates(MBB, MBBI, StackPtr, true); 794 795 // If there is an ADD32ri or SUB32ri of ESP immediately after this 796 // instruction, merge the two instructions. 797 mergeSPUpdatesDown(MBB, MBBI, StackPtr, &NumBytes); 798 799 // Adjust stack pointer: ESP -= numbytes. 800 801 // Windows and cygwin/mingw require a prologue helper routine when allocating 802 // more than 4K bytes on the stack. Windows uses __chkstk and cygwin/mingw 803 // uses __alloca. __alloca and the 32-bit version of __chkstk will probe the 804 // stack and adjust the stack pointer in one go. The 64-bit version of 805 // __chkstk is only responsible for probing the stack. The 64-bit prologue is 806 // responsible for adjusting the stack pointer. Touching the stack at 4K 807 // increments is necessary to ensure that the guard pages used by the OS 808 // virtual memory manager are allocated in correct sequence. 809 if (NumBytes >= 4096 && STI.isTargetCOFF() && !STI.isTargetEnvMacho()) { 810 const char *StackProbeSymbol; 811 bool isSPUpdateNeeded = false; 812 813 if (Is64Bit) { 814 if (STI.isTargetCygMing()) 815 StackProbeSymbol = "___chkstk"; 816 else { 817 StackProbeSymbol = "__chkstk"; 818 isSPUpdateNeeded = true; 819 } 820 } else if (STI.isTargetCygMing()) 821 StackProbeSymbol = "_alloca"; 822 else 823 StackProbeSymbol = "_chkstk"; 824 825 // Check whether EAX is livein for this function. 826 bool isEAXAlive = isEAXLiveIn(MF); 827 828 if (isEAXAlive) { 829 // Sanity check that EAX is not livein for this function. 830 // It should not be, so throw an assert. 831 assert(!Is64Bit && "EAX is livein in x64 case!"); 832 833 // Save EAX 834 BuildMI(MBB, MBBI, DL, TII.get(X86::PUSH32r)) 835 .addReg(X86::EAX, RegState::Kill) 836 .setMIFlag(MachineInstr::FrameSetup); 837 } 838 839 if (Is64Bit) { 840 // Handle the 64-bit Windows ABI case where we need to call __chkstk. 841 // Function prologue is responsible for adjusting the stack pointer. 842 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64ri), X86::RAX) 843 .addImm(NumBytes) 844 .setMIFlag(MachineInstr::FrameSetup); 845 } else { 846 // Allocate NumBytes-4 bytes on stack in case of isEAXAlive. 847 // We'll also use 4 already allocated bytes for EAX. 848 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32ri), X86::EAX) 849 .addImm(isEAXAlive ? NumBytes - 4 : NumBytes) 850 .setMIFlag(MachineInstr::FrameSetup); 851 } 852 853 BuildMI(MBB, MBBI, DL, 854 TII.get(Is64Bit ? X86::W64ALLOCA : X86::CALLpcrel32)) 855 .addExternalSymbol(StackProbeSymbol) 856 .addReg(StackPtr, RegState::Define | RegState::Implicit) 857 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit) 858 .setMIFlag(MachineInstr::FrameSetup); 859 860 // MSVC x64's __chkstk needs to adjust %rsp. 861 // FIXME: %rax preserves the offset and should be available. 862 if (isSPUpdateNeeded) 863 emitSPUpdate(MBB, MBBI, StackPtr, -(int64_t)NumBytes, Is64Bit, 864 TII, *RegInfo); 865 866 if (isEAXAlive) { 867 // Restore EAX 868 MachineInstr *MI = addRegOffset(BuildMI(MF, DL, TII.get(X86::MOV32rm), 869 X86::EAX), 870 StackPtr, false, NumBytes - 4); 871 MI->setFlag(MachineInstr::FrameSetup); 872 MBB.insert(MBBI, MI); 873 } 874 } else if (NumBytes) 875 emitSPUpdate(MBB, MBBI, StackPtr, -(int64_t)NumBytes, Is64Bit, 876 TII, *RegInfo); 877 878 if (( (!HasFP && NumBytes) || PushedRegs) && needsFrameMoves) { 879 // Mark end of stack pointer adjustment. 880 MCSymbol *Label = MMI.getContext().CreateTempSymbol(); 881 BuildMI(MBB, MBBI, DL, TII.get(X86::PROLOG_LABEL)) 882 .addSym(Label); 883 884 if (!HasFP && NumBytes) { 885 // Define the current CFA rule to use the provided offset. 886 if (StackSize) { 887 MachineLocation SPDst(MachineLocation::VirtualFP); 888 MachineLocation SPSrc(MachineLocation::VirtualFP, 889 -StackSize + stackGrowth); 890 Moves.push_back(MachineMove(Label, SPDst, SPSrc)); 891 } else { 892 MachineLocation SPDst(StackPtr); 893 MachineLocation SPSrc(StackPtr, stackGrowth); 894 Moves.push_back(MachineMove(Label, SPDst, SPSrc)); 895 } 896 } 897 898 // Emit DWARF info specifying the offsets of the callee-saved registers. 899 if (PushedRegs) 900 emitCalleeSavedFrameMoves(MF, Label, HasFP ? FramePtr : StackPtr); 901 } 902 903 // Darwin 10.7 and greater has support for compact unwind encoding. 904 if (STI.getTargetTriple().isMacOSX() && 905 !STI.getTargetTriple().isMacOSXVersionLT(10, 7)) 906 MMI.setCompactUnwindEncoding(getCompactUnwindEncoding(MF)); 907 } 908 909 void X86FrameLowering::emitEpilogue(MachineFunction &MF, 910 MachineBasicBlock &MBB) const { 911 const MachineFrameInfo *MFI = MF.getFrameInfo(); 912 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>(); 913 const X86RegisterInfo *RegInfo = TM.getRegisterInfo(); 914 const X86InstrInfo &TII = *TM.getInstrInfo(); 915 MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr(); 916 assert(MBBI != MBB.end() && "Returning block has no instructions"); 917 unsigned RetOpcode = MBBI->getOpcode(); 918 DebugLoc DL = MBBI->getDebugLoc(); 919 bool Is64Bit = STI.is64Bit(); 920 unsigned StackAlign = getStackAlignment(); 921 unsigned SlotSize = RegInfo->getSlotSize(); 922 unsigned FramePtr = RegInfo->getFrameRegister(MF); 923 unsigned StackPtr = RegInfo->getStackRegister(); 924 925 switch (RetOpcode) { 926 default: 927 llvm_unreachable("Can only insert epilog into returning blocks"); 928 case X86::RET: 929 case X86::RETI: 930 case X86::TCRETURNdi: 931 case X86::TCRETURNri: 932 case X86::TCRETURNmi: 933 case X86::TCRETURNdi64: 934 case X86::TCRETURNri64: 935 case X86::TCRETURNmi64: 936 case X86::EH_RETURN: 937 case X86::EH_RETURN64: 938 break; // These are ok 939 } 940 941 // Get the number of bytes to allocate from the FrameInfo. 942 uint64_t StackSize = MFI->getStackSize(); 943 uint64_t MaxAlign = MFI->getMaxAlignment(); 944 unsigned CSSize = X86FI->getCalleeSavedFrameSize(); 945 uint64_t NumBytes = 0; 946 947 // If we're forcing a stack realignment we can't rely on just the frame 948 // info, we need to know the ABI stack alignment as well in case we 949 // have a call out. Otherwise just make sure we have some alignment - we'll 950 // go with the minimum. 951 if (ForceStackAlign) { 952 if (MFI->hasCalls()) 953 MaxAlign = (StackAlign > MaxAlign) ? StackAlign : MaxAlign; 954 else 955 MaxAlign = MaxAlign ? MaxAlign : 4; 956 } 957 958 if (hasFP(MF)) { 959 // Calculate required stack adjustment. 960 uint64_t FrameSize = StackSize - SlotSize; 961 if (RegInfo->needsStackRealignment(MF)) 962 FrameSize = (FrameSize + MaxAlign - 1)/MaxAlign*MaxAlign; 963 964 NumBytes = FrameSize - CSSize; 965 966 // Pop EBP. 967 BuildMI(MBB, MBBI, DL, 968 TII.get(Is64Bit ? X86::POP64r : X86::POP32r), FramePtr); 969 } else { 970 NumBytes = StackSize - CSSize; 971 } 972 973 // Skip the callee-saved pop instructions. 974 MachineBasicBlock::iterator LastCSPop = MBBI; 975 while (MBBI != MBB.begin()) { 976 MachineBasicBlock::iterator PI = prior(MBBI); 977 unsigned Opc = PI->getOpcode(); 978 979 if (Opc != X86::POP32r && Opc != X86::POP64r && Opc != X86::DBG_VALUE && 980 !PI->getDesc().isTerminator()) 981 break; 982 983 --MBBI; 984 } 985 986 DL = MBBI->getDebugLoc(); 987 988 // If there is an ADD32ri or SUB32ri of ESP immediately before this 989 // instruction, merge the two instructions. 990 if (NumBytes || MFI->hasVarSizedObjects()) 991 mergeSPUpdatesUp(MBB, MBBI, StackPtr, &NumBytes); 992 993 // If dynamic alloca is used, then reset esp to point to the last callee-saved 994 // slot before popping them off! Same applies for the case, when stack was 995 // realigned. 996 if (RegInfo->needsStackRealignment(MF)) { 997 // We cannot use LEA here, because stack pointer was realigned. We need to 998 // deallocate local frame back. 999 if (CSSize) { 1000 emitSPUpdate(MBB, MBBI, StackPtr, NumBytes, Is64Bit, TII, *RegInfo); 1001 MBBI = prior(LastCSPop); 1002 } 1003 1004 BuildMI(MBB, MBBI, DL, 1005 TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), 1006 StackPtr).addReg(FramePtr); 1007 } else if (MFI->hasVarSizedObjects()) { 1008 if (CSSize) { 1009 unsigned Opc = Is64Bit ? X86::LEA64r : X86::LEA32r; 1010 MachineInstr *MI = 1011 addRegOffset(BuildMI(MF, DL, TII.get(Opc), StackPtr), 1012 FramePtr, false, -CSSize); 1013 MBB.insert(MBBI, MI); 1014 } else { 1015 BuildMI(MBB, MBBI, DL, 1016 TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), StackPtr) 1017 .addReg(FramePtr); 1018 } 1019 } else if (NumBytes) { 1020 // Adjust stack pointer back: ESP += numbytes. 1021 emitSPUpdate(MBB, MBBI, StackPtr, NumBytes, Is64Bit, TII, *RegInfo); 1022 } 1023 1024 // We're returning from function via eh_return. 1025 if (RetOpcode == X86::EH_RETURN || RetOpcode == X86::EH_RETURN64) { 1026 MBBI = MBB.getLastNonDebugInstr(); 1027 MachineOperand &DestAddr = MBBI->getOperand(0); 1028 assert(DestAddr.isReg() && "Offset should be in register!"); 1029 BuildMI(MBB, MBBI, DL, 1030 TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), 1031 StackPtr).addReg(DestAddr.getReg()); 1032 } else if (RetOpcode == X86::TCRETURNri || RetOpcode == X86::TCRETURNdi || 1033 RetOpcode == X86::TCRETURNmi || 1034 RetOpcode == X86::TCRETURNri64 || RetOpcode == X86::TCRETURNdi64 || 1035 RetOpcode == X86::TCRETURNmi64) { 1036 bool isMem = RetOpcode == X86::TCRETURNmi || RetOpcode == X86::TCRETURNmi64; 1037 // Tail call return: adjust the stack pointer and jump to callee. 1038 MBBI = MBB.getLastNonDebugInstr(); 1039 MachineOperand &JumpTarget = MBBI->getOperand(0); 1040 MachineOperand &StackAdjust = MBBI->getOperand(isMem ? 5 : 1); 1041 assert(StackAdjust.isImm() && "Expecting immediate value."); 1042 1043 // Adjust stack pointer. 1044 int StackAdj = StackAdjust.getImm(); 1045 int MaxTCDelta = X86FI->getTCReturnAddrDelta(); 1046 int Offset = 0; 1047 assert(MaxTCDelta <= 0 && "MaxTCDelta should never be positive"); 1048 1049 // Incoporate the retaddr area. 1050 Offset = StackAdj-MaxTCDelta; 1051 assert(Offset >= 0 && "Offset should never be negative"); 1052 1053 if (Offset) { 1054 // Check for possible merge with preceding ADD instruction. 1055 Offset += mergeSPUpdates(MBB, MBBI, StackPtr, true); 1056 emitSPUpdate(MBB, MBBI, StackPtr, Offset, Is64Bit, TII, *RegInfo); 1057 } 1058 1059 // Jump to label or value in register. 1060 if (RetOpcode == X86::TCRETURNdi || RetOpcode == X86::TCRETURNdi64) { 1061 MachineInstrBuilder MIB = 1062 BuildMI(MBB, MBBI, DL, TII.get((RetOpcode == X86::TCRETURNdi) 1063 ? X86::TAILJMPd : X86::TAILJMPd64)); 1064 if (JumpTarget.isGlobal()) 1065 MIB.addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(), 1066 JumpTarget.getTargetFlags()); 1067 else { 1068 assert(JumpTarget.isSymbol()); 1069 MIB.addExternalSymbol(JumpTarget.getSymbolName(), 1070 JumpTarget.getTargetFlags()); 1071 } 1072 } else if (RetOpcode == X86::TCRETURNmi || RetOpcode == X86::TCRETURNmi64) { 1073 MachineInstrBuilder MIB = 1074 BuildMI(MBB, MBBI, DL, TII.get((RetOpcode == X86::TCRETURNmi) 1075 ? X86::TAILJMPm : X86::TAILJMPm64)); 1076 for (unsigned i = 0; i != 5; ++i) 1077 MIB.addOperand(MBBI->getOperand(i)); 1078 } else if (RetOpcode == X86::TCRETURNri64) { 1079 BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPr64)). 1080 addReg(JumpTarget.getReg(), RegState::Kill); 1081 } else { 1082 BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPr)). 1083 addReg(JumpTarget.getReg(), RegState::Kill); 1084 } 1085 1086 MachineInstr *NewMI = prior(MBBI); 1087 for (unsigned i = 2, e = MBBI->getNumOperands(); i != e; ++i) 1088 NewMI->addOperand(MBBI->getOperand(i)); 1089 1090 // Delete the pseudo instruction TCRETURN. 1091 MBB.erase(MBBI); 1092 } else if ((RetOpcode == X86::RET || RetOpcode == X86::RETI) && 1093 (X86FI->getTCReturnAddrDelta() < 0)) { 1094 // Add the return addr area delta back since we are not tail calling. 1095 int delta = -1*X86FI->getTCReturnAddrDelta(); 1096 MBBI = MBB.getLastNonDebugInstr(); 1097 1098 // Check for possible merge with preceding ADD instruction. 1099 delta += mergeSPUpdates(MBB, MBBI, StackPtr, true); 1100 emitSPUpdate(MBB, MBBI, StackPtr, delta, Is64Bit, TII, *RegInfo); 1101 } 1102 } 1103 1104 int X86FrameLowering::getFrameIndexOffset(const MachineFunction &MF, int FI) const { 1105 const X86RegisterInfo *RI = 1106 static_cast<const X86RegisterInfo*>(MF.getTarget().getRegisterInfo()); 1107 const MachineFrameInfo *MFI = MF.getFrameInfo(); 1108 int Offset = MFI->getObjectOffset(FI) - getOffsetOfLocalArea(); 1109 uint64_t StackSize = MFI->getStackSize(); 1110 1111 if (RI->needsStackRealignment(MF)) { 1112 if (FI < 0) { 1113 // Skip the saved EBP. 1114 Offset += RI->getSlotSize(); 1115 } else { 1116 assert((-(Offset + StackSize)) % MFI->getObjectAlignment(FI) == 0); 1117 return Offset + StackSize; 1118 } 1119 // FIXME: Support tail calls 1120 } else { 1121 if (!hasFP(MF)) 1122 return Offset + StackSize; 1123 1124 // Skip the saved EBP. 1125 Offset += RI->getSlotSize(); 1126 1127 // Skip the RETADDR move area 1128 const X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>(); 1129 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta(); 1130 if (TailCallReturnAddrDelta < 0) 1131 Offset -= TailCallReturnAddrDelta; 1132 } 1133 1134 return Offset; 1135 } 1136 1137 bool X86FrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB, 1138 MachineBasicBlock::iterator MI, 1139 const std::vector<CalleeSavedInfo> &CSI, 1140 const TargetRegisterInfo *TRI) const { 1141 if (CSI.empty()) 1142 return false; 1143 1144 DebugLoc DL = MBB.findDebugLoc(MI); 1145 1146 MachineFunction &MF = *MBB.getParent(); 1147 1148 unsigned SlotSize = STI.is64Bit() ? 8 : 4; 1149 unsigned FPReg = TRI->getFrameRegister(MF); 1150 unsigned CalleeFrameSize = 0; 1151 1152 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); 1153 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>(); 1154 1155 // Push GPRs. It increases frame size. 1156 unsigned Opc = STI.is64Bit() ? X86::PUSH64r : X86::PUSH32r; 1157 for (unsigned i = CSI.size(); i != 0; --i) { 1158 unsigned Reg = CSI[i-1].getReg(); 1159 if (!X86::GR64RegClass.contains(Reg) && 1160 !X86::GR32RegClass.contains(Reg)) 1161 continue; 1162 // Add the callee-saved register as live-in. It's killed at the spill. 1163 MBB.addLiveIn(Reg); 1164 if (Reg == FPReg) 1165 // X86RegisterInfo::emitPrologue will handle spilling of frame register. 1166 continue; 1167 CalleeFrameSize += SlotSize; 1168 BuildMI(MBB, MI, DL, TII.get(Opc)).addReg(Reg, RegState::Kill) 1169 .setMIFlag(MachineInstr::FrameSetup); 1170 } 1171 1172 X86FI->setCalleeSavedFrameSize(CalleeFrameSize); 1173 1174 // Make XMM regs spilled. X86 does not have ability of push/pop XMM. 1175 // It can be done by spilling XMMs to stack frame. 1176 // Note that only Win64 ABI might spill XMMs. 1177 for (unsigned i = CSI.size(); i != 0; --i) { 1178 unsigned Reg = CSI[i-1].getReg(); 1179 if (X86::GR64RegClass.contains(Reg) || 1180 X86::GR32RegClass.contains(Reg)) 1181 continue; 1182 // Add the callee-saved register as live-in. It's killed at the spill. 1183 MBB.addLiveIn(Reg); 1184 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); 1185 TII.storeRegToStackSlot(MBB, MI, Reg, true, CSI[i-1].getFrameIdx(), 1186 RC, TRI); 1187 } 1188 1189 return true; 1190 } 1191 1192 bool X86FrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB, 1193 MachineBasicBlock::iterator MI, 1194 const std::vector<CalleeSavedInfo> &CSI, 1195 const TargetRegisterInfo *TRI) const { 1196 if (CSI.empty()) 1197 return false; 1198 1199 DebugLoc DL = MBB.findDebugLoc(MI); 1200 1201 MachineFunction &MF = *MBB.getParent(); 1202 const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); 1203 1204 // Reload XMMs from stack frame. 1205 for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 1206 unsigned Reg = CSI[i].getReg(); 1207 if (X86::GR64RegClass.contains(Reg) || 1208 X86::GR32RegClass.contains(Reg)) 1209 continue; 1210 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); 1211 TII.loadRegFromStackSlot(MBB, MI, Reg, CSI[i].getFrameIdx(), 1212 RC, TRI); 1213 } 1214 1215 // POP GPRs. 1216 unsigned FPReg = TRI->getFrameRegister(MF); 1217 unsigned Opc = STI.is64Bit() ? X86::POP64r : X86::POP32r; 1218 for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 1219 unsigned Reg = CSI[i].getReg(); 1220 if (!X86::GR64RegClass.contains(Reg) && 1221 !X86::GR32RegClass.contains(Reg)) 1222 continue; 1223 if (Reg == FPReg) 1224 // X86RegisterInfo::emitEpilogue will handle restoring of frame register. 1225 continue; 1226 BuildMI(MBB, MI, DL, TII.get(Opc), Reg); 1227 } 1228 return true; 1229 } 1230 1231 void 1232 X86FrameLowering::processFunctionBeforeCalleeSavedScan(MachineFunction &MF, 1233 RegScavenger *RS) const { 1234 MachineFrameInfo *MFI = MF.getFrameInfo(); 1235 const X86RegisterInfo *RegInfo = TM.getRegisterInfo(); 1236 unsigned SlotSize = RegInfo->getSlotSize(); 1237 1238 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>(); 1239 int32_t TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta(); 1240 1241 if (TailCallReturnAddrDelta < 0) { 1242 // create RETURNADDR area 1243 // arg 1244 // arg 1245 // RETADDR 1246 // { ... 1247 // RETADDR area 1248 // ... 1249 // } 1250 // [EBP] 1251 MFI->CreateFixedObject(-TailCallReturnAddrDelta, 1252 (-1U*SlotSize)+TailCallReturnAddrDelta, true); 1253 } 1254 1255 if (hasFP(MF)) { 1256 assert((TailCallReturnAddrDelta <= 0) && 1257 "The Delta should always be zero or negative"); 1258 const TargetFrameLowering &TFI = *MF.getTarget().getFrameLowering(); 1259 1260 // Create a frame entry for the EBP register that must be saved. 1261 int FrameIdx = MFI->CreateFixedObject(SlotSize, 1262 -(int)SlotSize + 1263 TFI.getOffsetOfLocalArea() + 1264 TailCallReturnAddrDelta, 1265 true); 1266 assert(FrameIdx == MFI->getObjectIndexBegin() && 1267 "Slot for EBP register must be last in order to be found!"); 1268 (void)FrameIdx; 1269 } 1270 } 1271 1272 static bool 1273 HasNestArgument(const MachineFunction *MF) { 1274 const Function *F = MF->getFunction(); 1275 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end(); 1276 I != E; I++) { 1277 if (I->hasNestAttr()) 1278 return true; 1279 } 1280 return false; 1281 } 1282 1283 static unsigned 1284 GetScratchRegister(bool Is64Bit, const MachineFunction &MF) { 1285 if (Is64Bit) { 1286 return X86::R11; 1287 } else { 1288 CallingConv::ID CallingConvention = MF.getFunction()->getCallingConv(); 1289 bool IsNested = HasNestArgument(&MF); 1290 1291 if (CallingConvention == CallingConv::X86_FastCall) { 1292 if (IsNested) { 1293 report_fatal_error("Segmented stacks does not support fastcall with " 1294 "nested function."); 1295 return -1; 1296 } else { 1297 return X86::EAX; 1298 } 1299 } else { 1300 if (IsNested) 1301 return X86::EDX; 1302 else 1303 return X86::ECX; 1304 } 1305 } 1306 } 1307 1308 void 1309 X86FrameLowering::adjustForSegmentedStacks(MachineFunction &MF) const { 1310 MachineBasicBlock &prologueMBB = MF.front(); 1311 MachineFrameInfo *MFI = MF.getFrameInfo(); 1312 const X86InstrInfo &TII = *TM.getInstrInfo(); 1313 uint64_t StackSize; 1314 bool Is64Bit = STI.is64Bit(); 1315 unsigned TlsReg, TlsOffset; 1316 DebugLoc DL; 1317 const X86Subtarget *ST = &MF.getTarget().getSubtarget<X86Subtarget>(); 1318 1319 unsigned ScratchReg = GetScratchRegister(Is64Bit, MF); 1320 assert(!MF.getRegInfo().isLiveIn(ScratchReg) && 1321 "Scratch register is live-in"); 1322 1323 if (MF.getFunction()->isVarArg()) 1324 report_fatal_error("Segmented stacks do not support vararg functions."); 1325 if (!ST->isTargetLinux()) 1326 report_fatal_error("Segmented stacks supported only on linux."); 1327 1328 MachineBasicBlock *allocMBB = MF.CreateMachineBasicBlock(); 1329 MachineBasicBlock *checkMBB = MF.CreateMachineBasicBlock(); 1330 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>(); 1331 bool IsNested = false; 1332 1333 // We need to know if the function has a nest argument only in 64 bit mode. 1334 if (Is64Bit) 1335 IsNested = HasNestArgument(&MF); 1336 1337 // The MOV R10, RAX needs to be in a different block, since the RET we emit in 1338 // allocMBB needs to be last (terminating) instruction. 1339 MachineBasicBlock *restoreR10MBB = NULL; 1340 if (IsNested) 1341 restoreR10MBB = MF.CreateMachineBasicBlock(); 1342 1343 for (MachineBasicBlock::livein_iterator i = prologueMBB.livein_begin(), 1344 e = prologueMBB.livein_end(); i != e; i++) { 1345 allocMBB->addLiveIn(*i); 1346 checkMBB->addLiveIn(*i); 1347 1348 if (IsNested) 1349 restoreR10MBB->addLiveIn(*i); 1350 } 1351 1352 if (IsNested) { 1353 allocMBB->addLiveIn(X86::R10); 1354 restoreR10MBB->addLiveIn(X86::RAX); 1355 } 1356 1357 if (IsNested) 1358 MF.push_front(restoreR10MBB); 1359 MF.push_front(allocMBB); 1360 MF.push_front(checkMBB); 1361 1362 // Eventually StackSize will be calculated by a link-time pass; which will 1363 // also decide whether checking code needs to be injected into this particular 1364 // prologue. 1365 StackSize = MFI->getStackSize(); 1366 1367 // Read the limit off the current stacklet off the stack_guard location. 1368 if (Is64Bit) { 1369 TlsReg = X86::FS; 1370 TlsOffset = 0x70; 1371 1372 BuildMI(checkMBB, DL, TII.get(X86::LEA64r), ScratchReg).addReg(X86::RSP) 1373 .addImm(0).addReg(0).addImm(-StackSize).addReg(0); 1374 BuildMI(checkMBB, DL, TII.get(X86::CMP64rm)).addReg(ScratchReg) 1375 .addReg(0).addImm(0).addReg(0).addImm(TlsOffset).addReg(TlsReg); 1376 } else { 1377 TlsReg = X86::GS; 1378 TlsOffset = 0x30; 1379 1380 BuildMI(checkMBB, DL, TII.get(X86::LEA32r), ScratchReg).addReg(X86::ESP) 1381 .addImm(0).addReg(0).addImm(-StackSize).addReg(0); 1382 BuildMI(checkMBB, DL, TII.get(X86::CMP32rm)).addReg(ScratchReg) 1383 .addReg(0).addImm(0).addReg(0).addImm(TlsOffset).addReg(TlsReg); 1384 } 1385 1386 // This jump is taken if SP >= (Stacklet Limit + Stack Space required). 1387 // It jumps to normal execution of the function body. 1388 BuildMI(checkMBB, DL, TII.get(X86::JG_4)).addMBB(&prologueMBB); 1389 1390 // On 32 bit we first push the arguments size and then the frame size. On 64 1391 // bit, we pass the stack frame size in r10 and the argument size in r11. 1392 if (Is64Bit) { 1393 // Functions with nested arguments use R10, so it needs to be saved across 1394 // the call to _morestack 1395 1396 if (IsNested) 1397 BuildMI(allocMBB, DL, TII.get(X86::MOV64rr), X86::RAX).addReg(X86::R10); 1398 1399 BuildMI(allocMBB, DL, TII.get(X86::MOV64ri), X86::R10) 1400 .addImm(StackSize); 1401 BuildMI(allocMBB, DL, TII.get(X86::MOV64ri), X86::R11) 1402 .addImm(X86FI->getArgumentStackSize()); 1403 MF.getRegInfo().setPhysRegUsed(X86::R10); 1404 MF.getRegInfo().setPhysRegUsed(X86::R11); 1405 } else { 1406 // Since we'll call __morestack, stack alignment needs to be preserved. 1407 BuildMI(allocMBB, DL, TII.get(X86::SUB32ri), X86::ESP).addReg(X86::ESP) 1408 .addImm(8); 1409 BuildMI(allocMBB, DL, TII.get(X86::PUSHi32)) 1410 .addImm(X86FI->getArgumentStackSize()); 1411 BuildMI(allocMBB, DL, TII.get(X86::PUSHi32)) 1412 .addImm(StackSize); 1413 } 1414 1415 // __morestack is in libgcc 1416 if (Is64Bit) 1417 BuildMI(allocMBB, DL, TII.get(X86::CALL64pcrel32)) 1418 .addExternalSymbol("__morestack"); 1419 else 1420 BuildMI(allocMBB, DL, TII.get(X86::CALLpcrel32)) 1421 .addExternalSymbol("__morestack"); 1422 1423 // __morestack only seems to remove 8 bytes off the stack. Add back the 1424 // additional 8 bytes we added before pushing the arguments. 1425 if (!Is64Bit) 1426 BuildMI(allocMBB, DL, TII.get(X86::ADD32ri), X86::ESP).addReg(X86::ESP) 1427 .addImm(8); 1428 BuildMI(allocMBB, DL, TII.get(X86::RET)); 1429 1430 if (IsNested) 1431 BuildMI(restoreR10MBB, DL, TII.get(X86::MOV64rr), X86::R10) 1432 .addReg(X86::RAX); 1433 1434 if (IsNested) { 1435 allocMBB->addSuccessor(restoreR10MBB); 1436 restoreR10MBB->addSuccessor(&prologueMBB); 1437 } else { 1438 allocMBB->addSuccessor(&prologueMBB); 1439 } 1440 1441 checkMBB->addSuccessor(allocMBB); 1442 checkMBB->addSuccessor(&prologueMBB); 1443 1444 #ifdef XDEBUG 1445 MF.verify(); 1446 #endif 1447 } 1448