1 %default { "naninst":"mvn r1, #0" } 2 %verify "executed" 3 %verify "basic lt, gt, eq */ 4 %verify "left arg NaN" 5 %verify "right arg NaN" 6 /* 7 * Compare two floating-point values. Puts 0, 1, or -1 into the 8 * destination register based on the results of the comparison. 9 * 10 * Provide a "naninst" instruction that puts 1 or -1 into r1 depending 11 * on what value we'd like to return when one of the operands is NaN. 12 * 13 * See OP_CMPL_FLOAT for an explanation. 14 * 15 * For: cmpl-double, cmpg-double 16 */ 17 /* op vAA, vBB, vCC */ 18 FETCH(r0, 1) @ r0<- CCBB 19 and r9, r0, #255 @ r9<- BB 20 mov r10, r0, lsr #8 @ r10<- CC 21 add r9, rFP, r9, lsl #2 @ r9<- &fp[BB] 22 add r10, rFP, r10, lsl #2 @ r10<- &fp[CC] 23 ldmia r9, {r0-r1} @ r0/r1<- vBB/vBB+1 24 ldmia r10, {r2-r3} @ r2/r3<- vCC/vCC+1 25 bl __aeabi_cdcmple @ cmp <=: C clear if <, Z set if eq 26 bhi .L${opcode}_gt_or_nan @ C set and Z clear, disambiguate 27 mvncc r1, #0 @ (less than) r1<- -1 28 moveq r1, #0 @ (equal) r1<- 0, trumps less than 29 .L${opcode}_finish: 30 mov r3, rINST, lsr #8 @ r3<- AA 31 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST 32 SET_VREG(r1, r3) @ vAA<- r1 33 GET_INST_OPCODE(ip) @ extract opcode from rINST 34 GOTO_OPCODE(ip) @ jump to next instruction 35 %break 36 37 @ Test for NaN with a second comparison. EABI forbids testing bit 38 @ patterns, and we can't represent 0x7fc00000 in immediate form, so 39 @ make the library call. 40 .L${opcode}_gt_or_nan: 41 ldmia r10, {r0-r1} @ reverse order 42 ldmia r9, {r2-r3} 43 bl __aeabi_cdcmple @ r0<- Z set if eq, C clear if < 44 @bleq common_abort 45 movcc r1, #1 @ (greater than) r1<- 1 46 bcc .L${opcode}_finish 47 $naninst @ r1<- 1 or -1 for NaN 48 b .L${opcode}_finish 49
