1 /* 2 * 3 * Copyright 2011 Samsung Electronics S.LSI Co. LTD 4 * 5 * Licensed under the Apache License, Version 2.0 (the "License"); 6 * you may not use this file except in compliance with the License. 7 * You may obtain a copy of the License at 8 * 9 * http://www.apache.org/licenses/LICENSE-2.0 10 * 11 * Unless required by applicable law or agreed to in writing, software 12 * distributed under the License is distributed on an "AS IS" BASIS, 13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14 * See the License for the specific language governing permissions and 15 * limitations under the License. 16 */ 17 18 /* 19 * @file csc_interleave_memcpy.s 20 * @brief SEC_OMX specific define 21 * @author ShinWon Lee (shinwon.lee (at) samsung.com) 22 * @version 1.0 23 * @history 24 * 2011.7.01 : Create 25 */ 26 .arch armv7-a 27 .text 28 .global csc_interleave_memcpy 29 .type csc_interleave_memcpy, %function 30 csc_interleave_memcpy: 31 .fnstart 32 33 @r0 dest 34 @r1 src1 35 @r2 src2 36 @r3 src_size 37 @r4 i 38 @r5 temp1 39 @r6 temp2 40 @r7 temp3 41 @r8 temp2 42 @r9 temp3 43 44 stmfd sp!, {r4-r12,r14} @ backup registers 45 46 mov r4, #0 47 cmp r3, #128 48 blt LINEAR_SIZE_64 49 50 bic r5, r3, #0x2F 51 LINEAR_SIZE_128_LOOP: 52 pld [r1, #64] 53 vld1.8 {q0}, [r1]! 54 vld1.8 {q2}, [r1]! 55 vld1.8 {q4}, [r1]! 56 vld1.8 {q6}, [r1]! 57 pld [r2] 58 vld1.8 {q8}, [r1]! 59 vld1.8 {q10}, [r1]! 60 vld1.8 {q12}, [r1]! 61 vld1.8 {q14}, [r1]! 62 pld [r2, #64] 63 vld1.8 {q1}, [r2]! 64 vld1.8 {q3}, [r2]! 65 vld1.8 {q5}, [r2]! 66 vld1.8 {q7}, [r2]! 67 vld1.8 {q9}, [r2]! 68 vld1.8 {q11}, [r2]! 69 vld1.8 {q13}, [r2]! 70 vld1.8 {q15}, [r2]! 71 72 vst2.8 {q0, q1}, [r0]! 73 vst2.8 {q2, q3}, [r0]! 74 vst2.8 {q4, q5}, [r0]! 75 vst2.8 {q6, q7}, [r0]! 76 vst2.8 {q8, q9}, [r0]! 77 vst2.8 {q10, q11}, [r0]! 78 pld [r1] 79 vst2.8 {q12, q13}, [r0]! 80 vst2.8 {q14, q15}, [r0]! 81 82 add r4, #128 83 cmp r4, r5 84 blt LINEAR_SIZE_128_LOOP 85 86 LINEAR_SIZE_64: 87 sub r5, r3, r4 88 cmp r5, #64 89 blt LINEAR_SIZE_2 90 LINEAR_SIZE_64_LOOP: 91 pld [r2] 92 vld1.8 {q0}, [r1]! 93 vld1.8 {q2}, [r1]! 94 vld1.8 {q4}, [r1]! 95 vld1.8 {q6}, [r1]! 96 vld1.8 {q1}, [r2]! 97 vld1.8 {q3}, [r2]! 98 vld1.8 {q5}, [r2]! 99 vld1.8 {q7}, [r2]! 100 101 vst2.8 {q0, q1}, [r0]! 102 vst2.8 {q2, q3}, [r0]! 103 pld [r1] 104 vst2.8 {q4, q5}, [r0]! 105 vst2.8 {q6, q7}, [r0]! 106 107 add r4, #64 108 cmp r4, r3 109 blt LINEAR_SIZE_64_LOOP 110 111 LINEAR_SIZE_2: 112 sub r5, r3, r4 113 cmp r5, #2 114 blt RESTORE_REG 115 LINEAR_SIZE_2_LOOP: 116 ldrb r6, [r1], #1 117 ldrb r7, [r2], #1 118 ldrb r8, [r1], #1 119 ldrb r9, [r2], #1 120 121 strb r6, [r0], #1 122 strb r7, [r0], #1 123 strb r8, [r0], #1 124 strb r9, [r0], #1 125 126 add r4, #2 127 cmp r4, r3 128 blt LINEAR_SIZE_2_LOOP 129 130 RESTORE_REG: 131 ldmfd sp!, {r4-r12,r15} @ restore registers 132 .fnend 133 134
