1 #ifndef _LINUX_DSSCOMP_H 2 #define _LINUX_DSSCOMP_H 3 4 #ifdef __KERNEL__ 5 #include <video/omapdss.h> 6 #else 7 8 /* exporting enumerations from arch/arm/plat-omap/include/plat/display.h */ 9 enum omap_plane { 10 OMAP_DSS_GFX = 0, 11 OMAP_DSS_VIDEO1 = 1, 12 OMAP_DSS_VIDEO2 = 2, 13 OMAP_DSS_VIDEO3 = 3, 14 OMAP_DSS_WB = 4, 15 }; 16 17 enum omap_channel { 18 OMAP_DSS_CHANNEL_LCD = 0, 19 OMAP_DSS_CHANNEL_DIGIT = 1, 20 OMAP_DSS_CHANNEL_LCD2 = 2, 21 }; 22 23 enum omap_color_mode { 24 OMAP_DSS_COLOR_CLUT1 = 1 << 0, /* BITMAP 1 */ 25 OMAP_DSS_COLOR_CLUT2 = 1 << 1, /* BITMAP 2 */ 26 OMAP_DSS_COLOR_CLUT4 = 1 << 2, /* BITMAP 4 */ 27 OMAP_DSS_COLOR_CLUT8 = 1 << 3, /* BITMAP 8 */ 28 29 /* also referred to as RGB 12-BPP, 16-bit container */ 30 OMAP_DSS_COLOR_RGB12U = 1 << 4, /* xRGB12-4444 */ 31 OMAP_DSS_COLOR_ARGB16 = 1 << 5, /* ARGB16-4444 */ 32 OMAP_DSS_COLOR_RGB16 = 1 << 6, /* RGB16-565 */ 33 34 /* also referred to as RGB 24-BPP, 32-bit container */ 35 OMAP_DSS_COLOR_RGB24U = 1 << 7, /* xRGB24-8888 */ 36 OMAP_DSS_COLOR_RGB24P = 1 << 8, /* RGB24-888 */ 37 OMAP_DSS_COLOR_YUV2 = 1 << 9, /* YUV2 4:2:2 co-sited */ 38 OMAP_DSS_COLOR_UYVY = 1 << 10, /* UYVY 4:2:2 co-sited */ 39 OMAP_DSS_COLOR_ARGB32 = 1 << 11, /* ARGB32-8888 */ 40 OMAP_DSS_COLOR_RGBA32 = 1 << 12, /* RGBA32-8888 */ 41 42 /* also referred to as RGBx 32 in TRM */ 43 OMAP_DSS_COLOR_RGBX24 = 1 << 13, /* RGBx32-8888 */ 44 OMAP_DSS_COLOR_RGBX32 = 1 << 13, /* RGBx32-8888 */ 45 OMAP_DSS_COLOR_NV12 = 1 << 14, /* NV12 format: YUV 4:2:0 */ 46 47 /* also referred to as RGBA12-4444 in TRM */ 48 OMAP_DSS_COLOR_RGBA16 = 1 << 15, /* RGBA16-4444 */ 49 50 OMAP_DSS_COLOR_RGBX12 = 1 << 16, /* RGBx16-4444 */ 51 OMAP_DSS_COLOR_RGBX16 = 1 << 16, /* RGBx16-4444 */ 52 OMAP_DSS_COLOR_ARGB16_1555 = 1 << 17, /* ARGB16-1555 */ 53 54 /* also referred to as xRGB16-555 in TRM */ 55 OMAP_DSS_COLOR_XRGB15 = 1 << 18, /* xRGB16-1555 */ 56 OMAP_DSS_COLOR_XRGB16_1555 = 1 << 18, /* xRGB16-1555 */ 57 }; 58 59 enum omap_dss_trans_key_type { 60 OMAP_DSS_COLOR_KEY_GFX_DST = 0, 61 OMAP_DSS_COLOR_KEY_VID_SRC = 1, 62 }; 63 64 enum omap_dss_display_state { 65 OMAP_DSS_DISPLAY_DISABLED = 0, 66 OMAP_DSS_DISPLAY_ACTIVE, 67 OMAP_DSS_DISPLAY_SUSPENDED, 68 OMAP_DSS_DISPLAY_TRANSITION, 69 }; 70 71 struct omap_video_timings { 72 /* Unit: pixels */ 73 __u16 x_res; 74 /* Unit: pixels */ 75 __u16 y_res; 76 /* Unit: KHz */ 77 __u32 pixel_clock; 78 /* Unit: pixel clocks */ 79 __u16 hsw; /* Horizontal synchronization pulse width */ 80 /* Unit: pixel clocks */ 81 __u16 hfp; /* Horizontal front porch */ 82 /* Unit: pixel clocks */ 83 __u16 hbp; /* Horizontal back porch */ 84 /* Unit: line clocks */ 85 __u16 vsw; /* Vertical synchronization pulse width */ 86 /* Unit: line clocks */ 87 __u16 vfp; /* Vertical front porch */ 88 /* Unit: line clocks */ 89 __u16 vbp; /* Vertical back porch */ 90 }; 91 92 /* YUV to RGB color conversion info */ 93 struct omap_dss_cconv_coefs { 94 __s16 ry, rcr, rcb; 95 __s16 gy, gcr, gcb; 96 __s16 by, bcr, bcb; 97 98 /* Y is 16..235, UV is 16..240 if not fullrange. Otherwise 0..255 */ 99 __u16 full_range; 100 } __attribute__ ((aligned(4))); 101 102 struct omap_dss_cpr_coefs { 103 __s16 rr, rg, rb; 104 __s16 gr, gg, gb; 105 __s16 br, bg, bb; 106 }; 107 108 #endif 109 110 /* copy of fb_videomode */ 111 struct dsscomp_videomode { 112 const char *name; /* optional */ 113 __u32 refresh; /* optional */ 114 __u32 xres; 115 __u32 yres; 116 __u32 pixclock; 117 __u32 left_margin; 118 __u32 right_margin; 119 __u32 upper_margin; 120 __u32 lower_margin; 121 __u32 hsync_len; 122 __u32 vsync_len; 123 __u32 sync; 124 __u32 vmode; 125 __u32 flag; 126 }; 127 128 /* 129 * Stereoscopic Panel types 130 * row, column, overunder, sidebyside options 131 * are with respect to native scan order 132 */ 133 enum s3d_disp_type { 134 S3D_DISP_NONE = 0, 135 S3D_DISP_FRAME_SEQ, 136 S3D_DISP_ROW_IL, 137 S3D_DISP_COL_IL, 138 S3D_DISP_PIX_IL, 139 S3D_DISP_CHECKB, 140 S3D_DISP_OVERUNDER, 141 S3D_DISP_SIDEBYSIDE, 142 }; 143 144 /* Subsampling direction is based on native panel scan order.*/ 145 enum s3d_disp_sub_sampling { 146 S3D_DISP_SUB_SAMPLE_NONE = 0, 147 S3D_DISP_SUB_SAMPLE_V, 148 S3D_DISP_SUB_SAMPLE_H, 149 }; 150 151 /* 152 * Indicates if display expects left view first followed by right or viceversa 153 * For row interlaved displays, defines first row view 154 * For column interleaved displays, defines first column view 155 * For checkerboard, defines first pixel view 156 * For overunder, defines top view 157 * For sidebyside, defines west view 158 */ 159 enum s3d_disp_order { 160 S3D_DISP_ORDER_L = 0, 161 S3D_DISP_ORDER_R = 1, 162 }; 163 164 /* 165 * Indicates current view 166 * Used mainly for displays that need to trigger a sync signal 167 */ 168 enum s3d_disp_view { 169 S3D_DISP_VIEW_L = 0, 170 S3D_DISP_VIEW_R, 171 }; 172 173 struct s3d_disp_info { 174 enum s3d_disp_type type; 175 enum s3d_disp_sub_sampling sub_samp; 176 enum s3d_disp_order order; 177 /* 178 * Gap between left and right views 179 * For over/under units are lines 180 * For sidebyside units are pixels 181 * For other types ignored 182 */ 183 unsigned int gap; 184 }; 185 186 enum omap_dss_ilace_mode { 187 OMAP_DSS_ILACE = (1 << 0), /* interlaced vs. progressive */ 188 OMAP_DSS_ILACE_SEQ = (1 << 1), /* sequential vs interleaved */ 189 OMAP_DSS_ILACE_SWAP = (1 << 2), /* swap fields, e.g. TB=>BT */ 190 191 OMAP_DSS_ILACE_NONE = 0, 192 OMAP_DSS_ILACE_IL_TB = OMAP_DSS_ILACE, 193 OMAP_DSS_ILACE_IL_BT = OMAP_DSS_ILACE | OMAP_DSS_ILACE_SWAP, 194 OMAP_DSS_ILACE_SEQ_TB = OMAP_DSS_ILACE_IL_TB | OMAP_DSS_ILACE_SEQ, 195 OMAP_DSS_ILACE_SEQ_BT = OMAP_DSS_ILACE_IL_BT | OMAP_DSS_ILACE_SEQ, 196 }; 197 198 /* YUV VC1 range mapping info */ 199 struct dss2_vc1_range_map_info { 200 __u8 enable; /* bool */ 201 202 __u8 range_y; /* 0..7 */ 203 __u8 range_uv; /* 0..7 */ 204 } __attribute__ ((aligned(4))); 205 206 /* standard rectangle */ 207 struct dss2_rect_t { 208 __s32 x; /* left */ 209 __s32 y; /* top */ 210 __u32 w; /* width */ 211 __u32 h; /* height */ 212 } __attribute__ ((aligned(4))); 213 214 /* decimation constraints */ 215 struct dss2_decim { 216 __u8 min_x; 217 __u8 max_x; /* 0 is same as 255 */ 218 __u8 min_y; 219 __u8 max_y; /* 0 is same as 255 */ 220 } __attribute__ ((aligned(4))); 221 222 /* 223 * A somewhat more user friendly interface to the DSS2. This is a 224 * direct interface to the DSS2 overlay and overlay_manager modules. 225 * User-space APIs are provided for HW-specific control of DSS in 226 * contrast with V4L2/FB that are more generic, but in this process 227 * omit HW-specific features. 228 * 229 * For now managers are specified by display index as opposed to manager 230 * type, so that display0 is always the default display (e.g. HDMI on 231 * panda, and LCD blaze.) For now you would need to query the displays 232 * or use sysfs to find a specific display. 233 * 234 * Userspace operations are as follows: 235 * 236 * 1) check if DSS supports an overlay configuration, use DSSCIOC_CHECK_OVL 237 * ioctl with the manager, overlay, and setup-mode information filled out. 238 * All fields should be filled out as it may influence whether DSS can 239 * display/render the overlay. 240 * 241 * If proper address information is not available, it may be possible to 242 * use a type-of-address enumeration instead for luma/rgb and chroma (if 243 * applicable) frames. 244 * 245 * Do this for each overlay before attempting to configure DSS. 246 * 247 * 2) configure DSS pipelines for display/manager using DSSCOMP_SETUP_MANAGER 248 * ioctl. You can delay applying the settings until an dss2_manager_apply() 249 * is called for the internal composition object, if the APPLY bit of setup mode 250 * is not set. However the CAPTURE/DISPLAY bits of the setup mode settings will 251 * determine if at this time a capture will take place (in case of capture 252 * only mode). You may also set up additional pipelines with 253 * dss2_overlay_setup() before this. 254 * 255 * 3) On OMAP4/5 you can use the DSS WB pipeline to copy (and convert) a buffer 256 * using DSS. Use the DSSCIOC_WB_COPY ioctl for this. This is a blocking 257 * call, and it may possibly fail if an ongoing WB capture mode has been 258 * scheduled (which is outside of the current scope of the DSS2 interface.) 259 * 260 * There is also a one-shot configuration API (DSSCIOC_SETUP_DISPC). This 261 * allows you to set-up all overlays on all managers in one call. This call 262 * performs additional functionality: 263 * 264 * - it maps userspace 1D buffers into TILER 1D for the duration of the display 265 * - it disables all overlays that were specified before, but are no longer 266 * specified 267 * 268 */ 269 270 /* 271 * DSS2 overlay information. This structure contains all information 272 * needed to set up the overlay for a particular buffer to be displayed 273 * at a particular orientation. 274 * 275 * The following information is deemed to be set globally, so it is not 276 * included: 277 * - whether to enable zorder (always enabled) 278 * - whether to replicate/truncate color fields (it is decided per the 279 * whole manager/overlay settings, and is enabled unless overlay is 280 * directed to WB.) 281 * 282 * There is also no support for CLUT formats 283 * 284 * Requirements: 285 * 286 * 1) 0 <= crop.x <= crop.x + crop.w <= width 287 * 2) 0 <= crop.y <= crop.y + crop.h <= height 288 * 3) win.x <= win.x + win.w and win.w >= 0 289 * 4) win.y <= win.y + win.h and win.h >= 0 290 * 291 * 5) color_mode is supported by overlay 292 * 6) requested scaling is supported by overlay and functional clocks 293 * 294 * Notes: 295 * 296 * 1) Any portions of X:[pos_x, pos_x + out_width] and 297 * Y:[pos_y, pos_y + out_height] outside of the screen 298 * X:[0, screen.width], Y:[0, screen.height] will be cropped 299 * automatically without changing the scaling ratio. 300 * 301 * 2) Crop region will be adjusted to the pixel granularity: 302 * (2-by-1) for YUV422, (2-by-2) for YUV420. This will 303 * not modify the output region. Crop region is for the 304 * original (unrotated) buffer, so it does not change with 305 * rotation. 306 * 307 * 3) Rotation will not modify the output region, specifically 308 * its height and width. Also the coordinate system of the 309 * display is always (0,0) = top left. 310 * 311 * 4) cconv and vc1 only needs to be filled for YUV color modes. 312 * 313 * 5) vc1.range_y and vc1.range_uv only needs to be filled if 314 * vc1.enable is true. 315 */ 316 struct dss2_ovl_cfg { 317 __u16 width; /* buffer width */ 318 __u16 height; /* buffer height */ 319 __u32 stride; /* buffer stride */ 320 321 enum omap_color_mode color_mode; 322 __u8 pre_mult_alpha; /* bool */ 323 __u8 global_alpha; /* 0..255 */ 324 __u8 rotation; /* 0..3 (*90 degrees clockwise) */ 325 __u8 mirror; /* left-to-right: mirroring is applied after rotation */ 326 327 enum omap_dss_ilace_mode ilace; /* interlace mode */ 328 329 struct dss2_rect_t win; /* output window - on display */ 330 struct dss2_rect_t crop; /* crop window - in source buffer */ 331 332 struct dss2_decim decim; /* predecimation limits */ 333 334 struct omap_dss_cconv_coefs cconv; 335 struct dss2_vc1_range_map_info vc1; 336 337 __u8 ix; /* ovl index same as sysfs/overlay# */ 338 __u8 zorder; /* 0..3 */ 339 __u8 enabled; /* bool */ 340 __u8 zonly; /* only set zorder and enabled bit */ 341 __u8 mgr_ix; /* mgr index */ 342 } __attribute__ ((aligned(4))); 343 344 enum omapdss_buffer_type { 345 OMAP_DSS_BUFTYPE_SDMA, 346 OMAP_DSS_BUFTYPE_TILER_8BIT, 347 OMAP_DSS_BUFTYPE_TILER_16BIT, 348 OMAP_DSS_BUFTYPE_TILER_32BIT, 349 OMAP_DSS_BUFTYPE_TILER_PAGE, 350 }; 351 352 enum omapdss_buffer_addressing_type { 353 OMAP_DSS_BUFADDR_DIRECT, /* using direct addresses */ 354 OMAP_DSS_BUFADDR_BYTYPE, /* using buffer types */ 355 OMAP_DSS_BUFADDR_ION, /* using ion handle(s) */ 356 OMAP_DSS_BUFADDR_GRALLOC, /* using gralloc handle */ 357 OMAP_DSS_BUFADDR_OVL_IX, /* using a prior overlay */ 358 OMAP_DSS_BUFADDR_LAYER_IX, /* using a Post2 layer */ 359 OMAP_DSS_BUFADDR_FB, /* using framebuffer memory */ 360 }; 361 362 struct dss2_ovl_info { 363 struct dss2_ovl_cfg cfg; 364 365 enum omapdss_buffer_addressing_type addressing; 366 367 union { 368 /* user-space interfaces */ 369 struct { 370 void *address; /* main buffer address */ 371 void *uv_address; /* uv buffer */ 372 }; 373 374 /* 375 * For DSSCIOC_CHECK_OVL we allow specifying just the 376 * type of each buffer. This is used if we need to 377 * check whether DSS will be able to display a buffer 378 * if using a particular memory type before spending 379 * time to map/copy the buffer into that type of 380 * memory. 381 */ 382 struct { 383 enum omapdss_buffer_type ba_type; 384 enum omapdss_buffer_type uv_type; 385 }; 386 387 /* kernel-space interfaces */ 388 389 /* 390 * for fbmem, highest 4-bits of address is fb index, 391 * rest of the bits are the offset 392 */ 393 struct { 394 __u32 ba; /* base address or index */ 395 __u32 uv; /* uv address */ 396 }; 397 }; 398 }; 399 400 /* 401 * DSS2 manager information. 402 * 403 * The following information is deemed to be set globally, so it is not 404 * included: 405 * gamma correction 406 * whether to enable zorder (always enabled) 407 * whether to replicate/truncate color fields (it is decided per the 408 * whole manager/overlay settings, and is enabled unless overlay is 409 * directed to WB.) 410 * Notes: 411 * 412 * 1) trans_key_type and trans_enabled only need to be filled if 413 * trans_enabled is true, and alpha_blending is false. 414 */ 415 struct dss2_mgr_info { 416 __u32 ix; /* display index same as sysfs/display# */ 417 418 __u32 default_color; 419 420 enum omap_dss_trans_key_type trans_key_type; 421 __u32 trans_key; 422 struct omap_dss_cpr_coefs cpr_coefs; 423 424 __u8 trans_enabled; /* bool */ 425 426 __u8 interlaced; /* bool */ 427 __u8 alpha_blending; /* bool - overrides trans_enabled */ 428 __u8 cpr_enabled; /* bool */ 429 __u8 swap_rb; /* bool - swap red and blue */ 430 } __attribute__ ((aligned(4))); 431 432 /* 433 * ioctl: DSSCIOC_SETUP_MGR, struct dsscomp_setup_mgr_data 434 * 435 * 1. sets manager of each ovl in composition to the display 436 * 2. calls set_dss_ovl_info() for each ovl to set up the 437 * overlay staging structures (this is a wrapper around ovl->set_info()) 438 * 3. calls set_dss_mgr_info() for mgr to set up the manager 439 * staging structures (this is a wrapper around mgr->set_info()) 440 * 4. if update is true: 441 * calls manager->apply() 442 * calls driver->update() in a non-blocking fashion 443 * this will program the DSS synchronously 444 * 445 * Notes: 446 * 447 * 1) x, y, w, h only needs to be set if update is true. 448 * 449 * All non-specified pipelines that currently are on the same display 450 * will remain the same as on the previous frame. You may want to 451 * disable unused pipelines to avoid surprises. 452 * 453 * If get_sync_obj is false, it returns 0 on success, <0 error value 454 * on failure. 455 * 456 * If get_sync_obj is true, it returns fd on success, or a negative value 457 * on failure. You can use the fd to wait on (using DSSCIOC_WAIT ioctl()). 458 * 459 * Note: frames do not get eclipsed when the display turns off. Queue a 460 * blank frame to eclipse old frames. Blank frames get eclipsed when 461 * programmed into DSS. 462 * 463 * (A blank frame is queued to the display automatically in Android before 464 * the display is turned off.) 465 * 466 * All overlays to be used on the frame must be listed. There is no way 467 * to add another overlay to a defined frame. 468 */ 469 enum dsscomp_setup_mode { 470 DSSCOMP_SETUP_MODE_APPLY = (1 << 0), /* applies changes to cache */ 471 DSSCOMP_SETUP_MODE_DISPLAY = (1 << 1), /* calls display update */ 472 DSSCOMP_SETUP_MODE_CAPTURE = (1 << 2), /* capture to WB */ 473 474 /* just apply changes for next vsync/update */ 475 DSSCOMP_SETUP_APPLY = DSSCOMP_SETUP_MODE_APPLY, 476 /* trigger an update (wait for vsync) */ 477 DSSCOMP_SETUP_DISPLAY = 478 DSSCOMP_SETUP_MODE_APPLY | DSSCOMP_SETUP_MODE_DISPLAY, 479 /* capture to WB - WB must be configured */ 480 DSSCOMP_SETUP_CAPTURE = 481 DSSCOMP_SETUP_MODE_APPLY | DSSCOMP_SETUP_MODE_CAPTURE, 482 /* display and capture to WB - WB must be configured */ 483 DSSCOMP_SETUP_DISPLAY_CAPTURE = 484 DSSCOMP_SETUP_DISPLAY | DSSCOMP_SETUP_CAPTURE, 485 }; 486 487 struct dsscomp_setup_mgr_data { 488 __u32 sync_id; /* synchronization ID - for debugging */ 489 490 struct dss2_rect_t win; /* update region, set w/h to 0 for fullscreen */ 491 enum dsscomp_setup_mode mode; 492 __u16 num_ovls; /* # of overlays used in the composition */ 493 __u16 get_sync_obj; /* ioctl should return a sync object */ 494 495 struct dss2_mgr_info mgr; 496 struct dss2_ovl_info ovls[0]; /* up to 5 overlays to set up */ 497 }; 498 499 /* 500 * ioctl: DSSCIOC_CHECK_OVL, struct dsscomp_check_ovl_data 501 * 502 * DISPLAY and/or CAPTURE bits must be filled for the mode field 503 * correctly to be able to decide correctly if DSS can properly 504 * render the overlay. 505 * 506 * ovl.ix is ignored. 507 * 508 * Returns a positive bitmask regarding which overlay of DSS can 509 * render the overlay as it is configured for the display/display's 510 * manager. NOTE: that overlays that are assigned to other displays 511 * may be returned. If there is an invalid configuration (negative 512 * sizes, etc.), a negative error value is returned. 513 * 514 * ovl->decim's min values will be modified to the smallest decimation that 515 * DSS can use to support the overlay configuration. 516 * 517 * Assumptions: 518 * - zorder will be distinct from other pipelines on that manager 519 * - overlay will be enabled and routed to the display specified 520 */ 521 struct dsscomp_check_ovl_data { 522 enum dsscomp_setup_mode mode; 523 struct dss2_mgr_info mgr; 524 struct dss2_ovl_info ovl; 525 }; 526 527 /* 528 * This structure is used to set up the entire DISPC (all managers), 529 * and is analogous to dsscomp_setup_mgr_data. 530 * 531 * Additional features: 532 * - all overlays that were specified in a prior use of this 533 * structure, and are no longer specified, will be disabled. 534 * - 1D buffers under 4M will be mapped into TILER1D. 535 * 536 * Limitations: 537 * - only DISPLAY mode is supported (DISPLAY and APPLY bits will 538 * automatically be set) 539 * - getting a sync object is not supported. 540 */ 541 struct dsscomp_setup_dispc_data { 542 __u32 sync_id; /* synchronization ID - for debugging */ 543 544 enum dsscomp_setup_mode mode; 545 __u16 num_ovls; /* # of overlays used in the composition */ 546 __u16 num_mgrs; /* # of managers used in the composition */ 547 __u16 get_sync_obj; /* ioctl should return a sync object */ 548 549 struct dss2_mgr_info mgrs[3]; 550 struct dss2_ovl_info ovls[5]; /* up to 5 overlays to set up */ 551 }; 552 553 /* 554 * ioctl: DSSCIOC_WB_COPY, struct dsscomp_wb_copy_data 555 *, 556 * Requirements: 557 * wb.ix must be OMAP_DSS_WB. 558 * 559 * Returns 0 on success (copy is completed), non-0 on failure. 560 */ 561 struct dsscomp_wb_copy_data { 562 struct dss2_ovl_info ovl, wb; 563 }; 564 565 /* 566 * ioctl: DSSCIOC_QUERY_DISPLAY, struct dsscomp_display_info 567 * 568 * Gets informations about the display. Fill in ix and modedb_len before 569 * calling ioctl, and rest of the fields are filled in by ioctl. Up to 570 * modedb_len timings are retrieved in the order of display preference. 571 * 572 * Returns: 0 on success, non-0 error value on failure. 573 */ 574 struct dsscomp_display_info { 575 __u32 ix; /* display index (sysfs/display#) */ 576 __u32 overlays_available; /* bitmask of available overlays */ 577 __u32 overlays_owned; /* bitmask of owned overlays */ 578 enum omap_channel channel; 579 enum omap_dss_display_state state; 580 __u8 enabled; /* bool: resume-state if suspended */ 581 struct omap_video_timings timings; 582 struct s3d_disp_info s3d_info; /* any S3D specific information */ 583 struct dss2_mgr_info mgr; /* manager information */ 584 __u16 width_in_mm; /* screen dimensions */ 585 __u16 height_in_mm; 586 587 __u32 modedb_len; /* number of video timings */ 588 struct dsscomp_videomode modedb[]; /* display supported timings */ 589 }; 590 591 /* 592 * ioctl: DSSCIOC_SETUP_DISPLAY, struct dsscomp_setup_display_data 593 * 594 * Gets informations about the display. Fill in ix before calling 595 * ioctl, and rest of the fields are filled in by ioctl. 596 * 597 * Returns: 0 on success, non-0 error value on failure. 598 */ 599 struct dsscomp_setup_display_data { 600 __u32 ix; /* display index (sysfs/display#) */ 601 struct dsscomp_videomode mode; /* video timings */ 602 }; 603 604 /* 605 * ioctl: DSSCIOC_WAIT, struct dsscomp_wait_data 606 * 607 * Use this ioctl to wait for one of the following events: 608 * 609 * A) the moment a composition is programmed into DSS 610 * B) the moment a composition is first displayed (or captured) 611 * C) the moment when a composition is no longer queued or displayed on a 612 * display (it is released). (A composition is assumed to be superceded 613 * when another composition has been programmed into DSS, even if that 614 * subsequent composition does not update/specify all overlays used by 615 * the prior composition; moreover, even if it uses the same buffers.) 616 * 617 * Set timeout to desired timeout value in microseconds. 618 * 619 * This ioctl must be used on the sync object returned by the 620 * DSSCIOC_SETUP_MGR or DSSCIOC_SETUP_DISPC ioctls. 621 * 622 * Returns: >=0 on success, <0 error value on failure (e.g. -ETIME). 623 */ 624 enum dsscomp_wait_phase { 625 DSSCOMP_WAIT_PROGRAMMED = 1, 626 DSSCOMP_WAIT_DISPLAYED, 627 DSSCOMP_WAIT_RELEASED, 628 }; 629 630 struct dsscomp_wait_data { 631 __u32 timeout_us; /* timeout in microseconds */ 632 enum dsscomp_wait_phase phase; /* phase to wait for */ 633 }; 634 635 /* IOCTLS */ 636 #define DSSCIOC_SETUP_MGR _IOW('O', 128, struct dsscomp_setup_mgr_data) 637 #define DSSCIOC_CHECK_OVL _IOWR('O', 129, struct dsscomp_check_ovl_data) 638 #define DSSCIOC_WB_COPY _IOW('O', 130, struct dsscomp_wb_copy_data) 639 #define DSSCIOC_QUERY_DISPLAY _IOWR('O', 131, struct dsscomp_display_info) 640 #define DSSCIOC_WAIT _IOW('O', 132, struct dsscomp_wait_data) 641 642 #define DSSCIOC_SETUP_DISPC _IOW('O', 133, struct dsscomp_setup_dispc_data) 643 #define DSSCIOC_SETUP_DISPLAY _IOW('O', 134, struct dsscomp_setup_display_data) 644 #endif 645
