Home | History | Annotate | Download | only in CodeGen
      1 //===-- llvm/CodeGen/SchedulerRegistry.h ------------------------*- C++ -*-===//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //===----------------------------------------------------------------------===//
      9 //
     10 // This file contains the implementation for instruction scheduler function
     11 // pass registry (RegisterScheduler).
     12 //
     13 //===----------------------------------------------------------------------===//
     14 
     15 #ifndef LLVM_CODEGENSCHEDULERREGISTRY_H
     16 #define LLVM_CODEGENSCHEDULERREGISTRY_H
     17 
     18 #include "llvm/CodeGen/MachinePassRegistry.h"
     19 #include "llvm/Target/TargetMachine.h"
     20 
     21 namespace llvm {
     22 
     23 //===----------------------------------------------------------------------===//
     24 ///
     25 /// RegisterScheduler class - Track the registration of instruction schedulers.
     26 ///
     27 //===----------------------------------------------------------------------===//
     28 
     29 class SelectionDAGISel;
     30 class ScheduleDAGSDNodes;
     31 class SelectionDAG;
     32 class MachineBasicBlock;
     33 
     34 class RegisterScheduler : public MachinePassRegistryNode {
     35 public:
     36   typedef ScheduleDAGSDNodes *(*FunctionPassCtor)(SelectionDAGISel*,
     37                                                   CodeGenOpt::Level);
     38 
     39   static MachinePassRegistry Registry;
     40 
     41   RegisterScheduler(const char *N, const char *D, FunctionPassCtor C)
     42   : MachinePassRegistryNode(N, D, (MachinePassCtor)C)
     43   { Registry.Add(this); }
     44   ~RegisterScheduler() { Registry.Remove(this); }
     45 
     46 
     47   // Accessors.
     48   //
     49   RegisterScheduler *getNext() const {
     50     return (RegisterScheduler *)MachinePassRegistryNode::getNext();
     51   }
     52   static RegisterScheduler *getList() {
     53     return (RegisterScheduler *)Registry.getList();
     54   }
     55   static FunctionPassCtor getDefault() {
     56     return (FunctionPassCtor)Registry.getDefault();
     57   }
     58   static void setDefault(FunctionPassCtor C) {
     59     Registry.setDefault((MachinePassCtor)C);
     60   }
     61   static void setListener(MachinePassRegistryListener *L) {
     62     Registry.setListener(L);
     63   }
     64 };
     65 
     66 /// createBURRListDAGScheduler - This creates a bottom up register usage
     67 /// reduction list scheduler.
     68 ScheduleDAGSDNodes *createBURRListDAGScheduler(SelectionDAGISel *IS,
     69                                                CodeGenOpt::Level OptLevel);
     70 
     71 /// createTDRRListDAGScheduler - This creates a top down register usage
     72 /// reduction list scheduler.
     73 ScheduleDAGSDNodes *createTDRRListDAGScheduler(SelectionDAGISel *IS,
     74                                                CodeGenOpt::Level OptLevel);
     75 
     76 /// createBURRListDAGScheduler - This creates a bottom up list scheduler that
     77 /// schedules nodes in source code order when possible.
     78 ScheduleDAGSDNodes *createSourceListDAGScheduler(SelectionDAGISel *IS,
     79                                                  CodeGenOpt::Level OptLevel);
     80 
     81 /// createHybridListDAGScheduler - This creates a bottom up register pressure
     82 /// aware list scheduler that make use of latency information to avoid stalls
     83 /// for long latency instructions in low register pressure mode. In high
     84 /// register pressure mode it schedules to reduce register pressure.
     85 ScheduleDAGSDNodes *createHybridListDAGScheduler(SelectionDAGISel *IS,
     86                                                  CodeGenOpt::Level);
     87 
     88 /// createILPListDAGScheduler - This creates a bottom up register pressure
     89 /// aware list scheduler that tries to increase instruction level parallelism
     90 /// in low register pressure mode. In high register pressure mode it schedules
     91 /// to reduce register pressure.
     92 ScheduleDAGSDNodes *createILPListDAGScheduler(SelectionDAGISel *IS,
     93                                               CodeGenOpt::Level);
     94 /// createTDListDAGScheduler - This creates a top-down list scheduler with
     95 /// a hazard recognizer.
     96 ScheduleDAGSDNodes *createTDListDAGScheduler(SelectionDAGISel *IS,
     97                                              CodeGenOpt::Level OptLevel);
     98 
     99 /// createFastDAGScheduler - This creates a "fast" scheduler.
    100 ///
    101 ScheduleDAGSDNodes *createFastDAGScheduler(SelectionDAGISel *IS,
    102                                            CodeGenOpt::Level OptLevel);
    103 
    104 /// createDefaultScheduler - This creates an instruction scheduler appropriate
    105 /// for the target.
    106 ScheduleDAGSDNodes *createDefaultScheduler(SelectionDAGISel *IS,
    107                                            CodeGenOpt::Level OptLevel);
    108 
    109 } // end namespace llvm
    110 
    111 #endif
    112