1 //===-- MCSubtargetInfo.cpp - Subtarget Information -----------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #include "llvm/MC/MCSubtargetInfo.h" 11 #include "llvm/MC/MCInstrItineraries.h" 12 #include "llvm/MC/SubtargetFeature.h" 13 #include "llvm/ADT/StringRef.h" 14 #include "llvm/ADT/Triple.h" 15 #include "llvm/Support/raw_ostream.h" 16 #include <algorithm> 17 18 using namespace llvm; 19 20 void 21 MCSubtargetInfo::InitMCSubtargetInfo(StringRef TT, StringRef CPU, StringRef FS, 22 const SubtargetFeatureKV *PF, 23 const SubtargetFeatureKV *PD, 24 const SubtargetInfoKV *PI, 25 const InstrStage *IS, 26 const unsigned *OC, 27 const unsigned *FP, 28 unsigned NF, unsigned NP) { 29 TargetTriple = TT; 30 ProcFeatures = PF; 31 ProcDesc = PD; 32 ProcItins = PI; 33 Stages = IS; 34 OperandCycles = OC; 35 ForwardingPathes = FP; 36 NumFeatures = NF; 37 NumProcs = NP; 38 39 SubtargetFeatures Features(FS); 40 FeatureBits = Features.getFeatureBits(CPU, ProcDesc, NumProcs, 41 ProcFeatures, NumFeatures); 42 } 43 44 45 /// ReInitMCSubtargetInfo - Change CPU (and optionally supplemented with 46 /// feature string) and recompute feature bits. 47 uint64_t MCSubtargetInfo::ReInitMCSubtargetInfo(StringRef CPU, StringRef FS) { 48 SubtargetFeatures Features(FS); 49 FeatureBits = Features.getFeatureBits(CPU, ProcDesc, NumProcs, 50 ProcFeatures, NumFeatures); 51 return FeatureBits; 52 } 53 54 /// ToggleFeature - Toggle a feature and returns the re-computed feature 55 /// bits. This version does not change the implied bits. 56 uint64_t MCSubtargetInfo::ToggleFeature(uint64_t FB) { 57 FeatureBits ^= FB; 58 return FeatureBits; 59 } 60 61 /// ToggleFeature - Toggle a feature and returns the re-computed feature 62 /// bits. This version will also change all implied bits. 63 uint64_t MCSubtargetInfo::ToggleFeature(StringRef FS) { 64 SubtargetFeatures Features; 65 FeatureBits = Features.ToggleFeature(FeatureBits, FS, 66 ProcFeatures, NumFeatures); 67 return FeatureBits; 68 } 69 70 71 InstrItineraryData 72 MCSubtargetInfo::getInstrItineraryForCPU(StringRef CPU) const { 73 assert(ProcItins && "Instruction itineraries information not available!"); 74 75 #ifndef NDEBUG 76 for (size_t i = 1; i < NumProcs; i++) { 77 assert(strcmp(ProcItins[i - 1].Key, ProcItins[i].Key) < 0 && 78 "Itineraries table is not sorted"); 79 } 80 #endif 81 82 // Find entry 83 SubtargetInfoKV KV; 84 KV.Key = CPU.data(); 85 const SubtargetInfoKV *Found = 86 std::lower_bound(ProcItins, ProcItins+NumProcs, KV); 87 if (Found == ProcItins+NumProcs || StringRef(Found->Key) != CPU) { 88 errs() << "'" << CPU 89 << "' is not a recognized processor for this target" 90 << " (ignoring processor)\n"; 91 return InstrItineraryData(); 92 } 93 94 return InstrItineraryData(Stages, OperandCycles, ForwardingPathes, 95 (InstrItinerary *)Found->Value); 96 } 97
