1 //===- MipsInstrFPU.td - Mips FPU Instruction Information --*- tablegen -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file describes the Mips FPU instruction set. 11 // 12 //===----------------------------------------------------------------------===// 13 14 //===----------------------------------------------------------------------===// 15 // Floating Point Instructions 16 // ------------------------ 17 // * 64bit fp: 18 // - 32 64-bit registers (default mode) 19 // - 16 even 32-bit registers (32-bit compatible mode) for 20 // single and double access. 21 // * 32bit fp: 22 // - 16 even 32-bit registers - single and double (aliased) 23 // - 32 32-bit registers (within single-only mode) 24 //===----------------------------------------------------------------------===// 25 26 // Floating Point Compare and Branch 27 def SDT_MipsFPBrcond : SDTypeProfile<0, 2, [SDTCisInt<0>, 28 SDTCisVT<1, OtherVT>]>; 29 def SDT_MipsFPCmp : SDTypeProfile<0, 3, [SDTCisSameAs<0, 1>, SDTCisFP<1>, 30 SDTCisVT<2, i32>]>; 31 def SDT_MipsCMovFP : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>, 32 SDTCisSameAs<1, 2>]>; 33 def SDT_MipsBuildPairF64 : SDTypeProfile<1, 2, [SDTCisVT<0, f64>, 34 SDTCisVT<1, i32>, 35 SDTCisSameAs<1, 2>]>; 36 def SDT_MipsExtractElementF64 : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, 37 SDTCisVT<1, f64>, 38 SDTCisVT<2, i32>]>; 39 40 def MipsFPCmp : SDNode<"MipsISD::FPCmp", SDT_MipsFPCmp, [SDNPOutGlue]>; 41 def MipsCMovFP_T : SDNode<"MipsISD::CMovFP_T", SDT_MipsCMovFP, [SDNPInGlue]>; 42 def MipsCMovFP_F : SDNode<"MipsISD::CMovFP_F", SDT_MipsCMovFP, [SDNPInGlue]>; 43 def MipsFPBrcond : SDNode<"MipsISD::FPBrcond", SDT_MipsFPBrcond, 44 [SDNPHasChain, SDNPOptInGlue]>; 45 def MipsBuildPairF64 : SDNode<"MipsISD::BuildPairF64", SDT_MipsBuildPairF64>; 46 def MipsExtractElementF64 : SDNode<"MipsISD::ExtractElementF64", 47 SDT_MipsExtractElementF64>; 48 49 // Operand for printing out a condition code. 50 let PrintMethod = "printFCCOperand" in 51 def condcode : Operand<i32>; 52 53 //===----------------------------------------------------------------------===// 54 // Feature predicates. 55 //===----------------------------------------------------------------------===// 56 57 def IsFP64bit : Predicate<"Subtarget.isFP64bit()">; 58 def NotFP64bit : Predicate<"!Subtarget.isFP64bit()">; 59 def IsSingleFloat : Predicate<"Subtarget.isSingleFloat()">; 60 def IsNotSingleFloat : Predicate<"!Subtarget.isSingleFloat()">; 61 62 //===----------------------------------------------------------------------===// 63 // Instruction Class Templates 64 // 65 // A set of multiclasses is used to address the register usage. 66 // 67 // S32 - single precision in 16 32bit even fp registers 68 // single precision in 32 32bit fp registers in SingleOnly mode 69 // S64 - single precision in 32 64bit fp registers (In64BitMode) 70 // D32 - double precision in 16 32bit even fp registers 71 // D64 - double precision in 32 64bit fp registers (In64BitMode) 72 // 73 // Only S32 and D32 are supported right now. 74 //===----------------------------------------------------------------------===// 75 76 // FP load. 77 class FPLoad<bits<6> op, string opstr, PatFrag FOp, RegisterClass RC, 78 Operand MemOpnd>: 79 FMem<op, (outs RC:$ft), (ins MemOpnd:$addr), 80 !strconcat(opstr, "\t$ft, $addr"), [(set RC:$ft, (FOp addr:$addr))], 81 IILoad>; 82 83 // FP store. 84 class FPStore<bits<6> op, string opstr, PatFrag FOp, RegisterClass RC, 85 Operand MemOpnd>: 86 FMem<op, (outs), (ins RC:$ft, MemOpnd:$addr), 87 !strconcat(opstr, "\t$ft, $addr"), [(store RC:$ft, addr:$addr)], 88 IIStore>; 89 90 // Instructions that convert an FP value to 32-bit fixed point. 91 multiclass FFR1_W_M<bits<6> funct, string opstr> { 92 def _S : FFR1<funct, 16, opstr, "w.s", FGR32, FGR32>; 93 def _D32 : FFR1<funct, 17, opstr, "w.d", FGR32, AFGR64>, 94 Requires<[NotFP64bit]>; 95 def _D64 : FFR1<funct, 17, opstr, "w.d", FGR32, FGR64>, 96 Requires<[IsFP64bit]>; 97 } 98 99 // Instructions that convert an FP value to 64-bit fixed point. 100 let Predicates = [IsFP64bit] in 101 multiclass FFR1_L_M<bits<6> funct, string opstr> { 102 def _S : FFR1<funct, 16, opstr, "l.s", FGR64, FGR32>; 103 def _D64 : FFR1<funct, 17, opstr, "l.d", FGR64, FGR64>; 104 } 105 106 // FP-to-FP conversion instructions. 107 multiclass FFR1P_M<bits<6> funct, string opstr, SDNode OpNode> { 108 def _S : FFR1P<funct, 16, opstr, "s", FGR32, FGR32, OpNode>; 109 def _D32 : FFR1P<funct, 17, opstr, "d", AFGR64, AFGR64, OpNode>, 110 Requires<[NotFP64bit]>; 111 def _D64 : FFR1P<funct, 17, opstr, "d", FGR64, FGR64, OpNode>, 112 Requires<[IsFP64bit]>; 113 } 114 115 multiclass FFR2P_M<bits<6> funct, string opstr, SDNode OpNode, bit isComm = 0> { 116 let isCommutable = isComm in { 117 def _S : FFR2P<funct, 16, opstr, "s", FGR32, OpNode>; 118 def _D32 : FFR2P<funct, 17, opstr, "d", AFGR64, OpNode>, 119 Requires<[NotFP64bit]>; 120 def _D64 : FFR2P<funct, 17, opstr, "d", FGR64, OpNode>, 121 Requires<[IsFP64bit]>; 122 } 123 } 124 125 //===----------------------------------------------------------------------===// 126 // Floating Point Instructions 127 //===----------------------------------------------------------------------===// 128 defm ROUND_W : FFR1_W_M<0xc, "round">; 129 defm ROUND_L : FFR1_L_M<0x8, "round">; 130 defm TRUNC_W : FFR1_W_M<0xd, "trunc">; 131 defm TRUNC_L : FFR1_L_M<0x9, "trunc">; 132 defm CEIL_W : FFR1_W_M<0xe, "ceil">; 133 defm CEIL_L : FFR1_L_M<0xa, "ceil">; 134 defm FLOOR_W : FFR1_W_M<0xf, "floor">; 135 defm FLOOR_L : FFR1_L_M<0xb, "floor">; 136 defm CVT_W : FFR1_W_M<0x24, "cvt">; 137 defm CVT_L : FFR1_L_M<0x25, "cvt">; 138 139 def CVT_S_W : FFR1<0x20, 20, "cvt", "s.w", FGR32, FGR32>; 140 141 let Predicates = [NotFP64bit] in { 142 def CVT_S_D32 : FFR1<0x20, 17, "cvt", "s.d", FGR32, AFGR64>; 143 def CVT_D32_W : FFR1<0x21, 20, "cvt", "d.w", AFGR64, FGR32>; 144 def CVT_D32_S : FFR1<0x21, 16, "cvt", "d.s", AFGR64, FGR32>; 145 } 146 147 let Predicates = [IsFP64bit] in { 148 def CVT_S_D64 : FFR1<0x20, 17, "cvt", "s.d", FGR32, FGR64>; 149 def CVT_S_L : FFR1<0x20, 21, "cvt", "s.l", FGR32, FGR64>; 150 def CVT_D64_W : FFR1<0x21, 20, "cvt", "d.w", FGR64, FGR32>; 151 def CVT_D64_S : FFR1<0x21, 16, "cvt", "d.s", FGR64, FGR32>; 152 def CVT_D64_L : FFR1<0x21, 21, "cvt", "d.l", FGR64, FGR64>; 153 } 154 155 defm FABS : FFR1P_M<0x5, "abs", fabs>; 156 defm FNEG : FFR1P_M<0x7, "neg", fneg>; 157 defm FSQRT : FFR1P_M<0x4, "sqrt", fsqrt>; 158 159 // The odd-numbered registers are only referenced when doing loads, 160 // stores, and moves between floating-point and integer registers. 161 // When defining instructions, we reference all 32-bit registers, 162 // regardless of register aliasing. 163 164 class FFRGPR<bits<5> _fmt, dag outs, dag ins, string asmstr, list<dag> pattern>: 165 FFR<0x11, 0x0, _fmt, outs, ins, asmstr, pattern> { 166 bits<5> rt; 167 let ft = rt; 168 let fd = 0; 169 } 170 171 /// Move Control Registers From/To CPU Registers 172 def CFC1 : FFRGPR<0x2, (outs CPURegs:$rt), (ins CCR:$fs), 173 "cfc1\t$rt, $fs", []>; 174 175 def CTC1 : FFRGPR<0x6, (outs CCR:$fs), (ins CPURegs:$rt), 176 "ctc1\t$rt, $fs", []>; 177 178 def MFC1 : FFRGPR<0x00, (outs CPURegs:$rt), (ins FGR32:$fs), 179 "mfc1\t$rt, $fs", 180 [(set CPURegs:$rt, (bitconvert FGR32:$fs))]>; 181 182 def MTC1 : FFRGPR<0x04, (outs FGR32:$fs), (ins CPURegs:$rt), 183 "mtc1\t$rt, $fs", 184 [(set FGR32:$fs, (bitconvert CPURegs:$rt))]>; 185 186 def FMOV_S : FFR1<0x6, 16, "mov", "s", FGR32, FGR32>; 187 def FMOV_D32 : FFR1<0x6, 17, "mov", "d", AFGR64, AFGR64>, 188 Requires<[NotFP64bit]>; 189 def FMOV_D64 : FFR1<0x6, 17, "mov", "d", FGR64, FGR64>, 190 Requires<[IsFP64bit]>; 191 192 /// Floating Point Memory Instructions 193 let Predicates = [IsN64] in { 194 def LWC1_P8 : FPLoad<0x31, "lwc1", load, FGR32, mem64>; 195 def SWC1_P8 : FPStore<0x39, "swc1", store, FGR32, mem64>; 196 def LDC164_P8 : FPLoad<0x35, "ldc1", load, FGR64, mem64>; 197 def SDC164_P8 : FPStore<0x3d, "sdc1", store, FGR64, mem64>; 198 } 199 200 let Predicates = [NotN64] in { 201 def LWC1 : FPLoad<0x31, "lwc1", load, FGR32, mem>; 202 def SWC1 : FPStore<0x39, "swc1", store, FGR32, mem>; 203 let Predicates = [HasMips64] in { 204 def LDC164 : FPLoad<0x35, "ldc1", load, FGR64, mem>; 205 def SDC164 : FPStore<0x3d, "sdc1", store, FGR64, mem>; 206 } 207 let Predicates = [NotMips64] in { 208 def LDC1 : FPLoad<0x35, "ldc1", load, AFGR64, mem>; 209 def SDC1 : FPStore<0x3d, "sdc1", store, AFGR64, mem>; 210 } 211 } 212 213 /// Floating-point Aritmetic 214 defm FADD : FFR2P_M<0x00, "add", fadd, 1>; 215 defm FDIV : FFR2P_M<0x03, "div", fdiv>; 216 defm FMUL : FFR2P_M<0x02, "mul", fmul, 1>; 217 defm FSUB : FFR2P_M<0x01, "sub", fsub>; 218 219 //===----------------------------------------------------------------------===// 220 // Floating Point Branch Codes 221 //===----------------------------------------------------------------------===// 222 // Mips branch codes. These correspond to condcode in MipsInstrInfo.h. 223 // They must be kept in synch. 224 def MIPS_BRANCH_F : PatLeaf<(i32 0)>; 225 def MIPS_BRANCH_T : PatLeaf<(i32 1)>; 226 227 /// Floating Point Branch of False/True (Likely) 228 let isBranch=1, isTerminator=1, hasDelaySlot=1, base=0x8, Uses=[FCR31] in 229 class FBRANCH<bits<1> nd, bits<1> tf, PatLeaf op, string asmstr> : 230 FFI<0x11, (outs), (ins brtarget:$dst), !strconcat(asmstr, "\t$dst"), 231 [(MipsFPBrcond op, bb:$dst)]> { 232 let Inst{20-18} = 0; 233 let Inst{17} = nd; 234 let Inst{16} = tf; 235 } 236 237 def BC1F : FBRANCH<0, 0, MIPS_BRANCH_F, "bc1f">; 238 def BC1T : FBRANCH<0, 1, MIPS_BRANCH_T, "bc1t">; 239 240 //===----------------------------------------------------------------------===// 241 // Floating Point Flag Conditions 242 //===----------------------------------------------------------------------===// 243 // Mips condition codes. They must correspond to condcode in MipsInstrInfo.h. 244 // They must be kept in synch. 245 def MIPS_FCOND_F : PatLeaf<(i32 0)>; 246 def MIPS_FCOND_UN : PatLeaf<(i32 1)>; 247 def MIPS_FCOND_OEQ : PatLeaf<(i32 2)>; 248 def MIPS_FCOND_UEQ : PatLeaf<(i32 3)>; 249 def MIPS_FCOND_OLT : PatLeaf<(i32 4)>; 250 def MIPS_FCOND_ULT : PatLeaf<(i32 5)>; 251 def MIPS_FCOND_OLE : PatLeaf<(i32 6)>; 252 def MIPS_FCOND_ULE : PatLeaf<(i32 7)>; 253 def MIPS_FCOND_SF : PatLeaf<(i32 8)>; 254 def MIPS_FCOND_NGLE : PatLeaf<(i32 9)>; 255 def MIPS_FCOND_SEQ : PatLeaf<(i32 10)>; 256 def MIPS_FCOND_NGL : PatLeaf<(i32 11)>; 257 def MIPS_FCOND_LT : PatLeaf<(i32 12)>; 258 def MIPS_FCOND_NGE : PatLeaf<(i32 13)>; 259 def MIPS_FCOND_LE : PatLeaf<(i32 14)>; 260 def MIPS_FCOND_NGT : PatLeaf<(i32 15)>; 261 262 /// Floating Point Compare 263 let Defs=[FCR31] in { 264 def FCMP_S32 : FCC<0x10, (outs), (ins FGR32:$fs, FGR32:$ft, condcode:$cc), 265 "c.$cc.s\t$fs, $ft", 266 [(MipsFPCmp FGR32:$fs, FGR32:$ft, imm:$cc)]>; 267 268 def FCMP_D32 : FCC<0x11, (outs), (ins AFGR64:$fs, AFGR64:$ft, condcode:$cc), 269 "c.$cc.d\t$fs, $ft", 270 [(MipsFPCmp AFGR64:$fs, AFGR64:$ft, imm:$cc)]>, 271 Requires<[NotFP64bit]>; 272 } 273 274 //===----------------------------------------------------------------------===// 275 // Floating Point Pseudo-Instructions 276 //===----------------------------------------------------------------------===// 277 def MOVCCRToCCR : MipsPseudo<(outs CCR:$dst), (ins CCR:$src), 278 "# MOVCCRToCCR", []>; 279 280 // This pseudo instr gets expanded into 2 mtc1 instrs after register 281 // allocation. 282 def BuildPairF64 : 283 MipsPseudo<(outs AFGR64:$dst), 284 (ins CPURegs:$lo, CPURegs:$hi), "", 285 [(set AFGR64:$dst, (MipsBuildPairF64 CPURegs:$lo, CPURegs:$hi))]>; 286 287 // This pseudo instr gets expanded into 2 mfc1 instrs after register 288 // allocation. 289 // if n is 0, lower part of src is extracted. 290 // if n is 1, higher part of src is extracted. 291 def ExtractElementF64 : 292 MipsPseudo<(outs CPURegs:$dst), 293 (ins AFGR64:$src, i32imm:$n), "", 294 [(set CPURegs:$dst, 295 (MipsExtractElementF64 AFGR64:$src, imm:$n))]>; 296 297 //===----------------------------------------------------------------------===// 298 // Floating Point Patterns 299 //===----------------------------------------------------------------------===// 300 def fpimm0 : PatLeaf<(fpimm), [{ 301 return N->isExactlyValue(+0.0); 302 }]>; 303 304 def fpimm0neg : PatLeaf<(fpimm), [{ 305 return N->isExactlyValue(-0.0); 306 }]>; 307 308 def : Pat<(f32 fpimm0), (MTC1 ZERO)>; 309 def : Pat<(f32 fpimm0neg), (FNEG_S (MTC1 ZERO))>; 310 311 def : Pat<(f32 (sint_to_fp CPURegs:$src)), (CVT_S_W (MTC1 CPURegs:$src))>; 312 def : Pat<(f64 (sint_to_fp CPURegs:$src)), (CVT_D32_W (MTC1 CPURegs:$src))>; 313 314 def : Pat<(i32 (fp_to_sint FGR32:$src)), (MFC1 (TRUNC_W_S FGR32:$src))>; 315 def : Pat<(i32 (fp_to_sint AFGR64:$src)), (MFC1 (TRUNC_W_D32 AFGR64:$src))>; 316 317 let Predicates = [NotFP64bit] in { 318 def : Pat<(f32 (fround AFGR64:$src)), (CVT_S_D32 AFGR64:$src)>; 319 def : Pat<(f64 (fextend FGR32:$src)), (CVT_D32_S FGR32:$src)>; 320 } 321 322
