1 //===-- PTXTargetMachine.cpp - Define TargetMachine for PTX ---------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // Top-level implementation for the PTX target. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "PTX.h" 15 #include "PTXTargetMachine.h" 16 #include "llvm/PassManager.h" 17 #include "llvm/Analysis/Passes.h" 18 #include "llvm/Analysis/Verifier.h" 19 #include "llvm/Assembly/PrintModulePass.h" 20 #include "llvm/ADT/OwningPtr.h" 21 #include "llvm/CodeGen/AsmPrinter.h" 22 #include "llvm/CodeGen/MachineFunctionAnalysis.h" 23 #include "llvm/CodeGen/MachineModuleInfo.h" 24 #include "llvm/CodeGen/Passes.h" 25 #include "llvm/MC/MCAsmInfo.h" 26 #include "llvm/MC/MCInstrInfo.h" 27 #include "llvm/MC/MCStreamer.h" 28 #include "llvm/MC/MCSubtargetInfo.h" 29 #include "llvm/Support/TargetRegistry.h" 30 #include "llvm/Support/raw_ostream.h" 31 #include "llvm/Target/TargetData.h" 32 #include "llvm/Target/TargetInstrInfo.h" 33 #include "llvm/Target/TargetLowering.h" 34 #include "llvm/Target/TargetLoweringObjectFile.h" 35 #include "llvm/Target/TargetMachine.h" 36 #include "llvm/Target/TargetOptions.h" 37 #include "llvm/Target/TargetRegisterInfo.h" 38 #include "llvm/Target/TargetSubtargetInfo.h" 39 #include "llvm/Transforms/Scalar.h" 40 #include "llvm/Support/Debug.h" 41 #include "llvm/Support/TargetRegistry.h" 42 43 44 using namespace llvm; 45 46 namespace llvm { 47 MCStreamer *createPTXAsmStreamer(MCContext &Ctx, formatted_raw_ostream &OS, 48 bool isVerboseAsm, bool useLoc, 49 bool useCFI, bool useDwarfDirectory, 50 MCInstPrinter *InstPrint, 51 MCCodeEmitter *CE, 52 MCAsmBackend *MAB, 53 bool ShowInst); 54 } 55 56 extern "C" void LLVMInitializePTXTarget() { 57 58 RegisterTargetMachine<PTX32TargetMachine> X(ThePTX32Target); 59 RegisterTargetMachine<PTX64TargetMachine> Y(ThePTX64Target); 60 61 TargetRegistry::RegisterAsmStreamer(ThePTX32Target, createPTXAsmStreamer); 62 TargetRegistry::RegisterAsmStreamer(ThePTX64Target, createPTXAsmStreamer); 63 } 64 65 namespace { 66 const char* DataLayout32 = 67 "e-p:32:32-i64:32:32-f64:32:32-v128:32:128-v64:32:64-n32:64"; 68 const char* DataLayout64 = 69 "e-p:64:64-i64:32:32-f64:32:32-v128:32:128-v64:32:64-n32:64"; 70 71 // Copied from LLVMTargetMachine.cpp 72 void printNoVerify(PassManagerBase &PM, const char *Banner) { 73 if (PrintMachineCode) 74 PM.add(createMachineFunctionPrinterPass(dbgs(), Banner)); 75 } 76 77 void printAndVerify(PassManagerBase &PM, 78 const char *Banner) { 79 if (PrintMachineCode) 80 PM.add(createMachineFunctionPrinterPass(dbgs(), Banner)); 81 82 //if (VerifyMachineCode) 83 // PM.add(createMachineVerifierPass(Banner)); 84 } 85 } 86 87 // DataLayout and FrameLowering are filled with dummy data 88 PTXTargetMachine::PTXTargetMachine(const Target &T, 89 StringRef TT, StringRef CPU, StringRef FS, 90 Reloc::Model RM, CodeModel::Model CM, 91 bool is64Bit) 92 : LLVMTargetMachine(T, TT, CPU, FS, RM, CM), 93 DataLayout(is64Bit ? DataLayout64 : DataLayout32), 94 Subtarget(TT, CPU, FS, is64Bit), 95 FrameLowering(Subtarget), 96 InstrInfo(*this), 97 TSInfo(*this), 98 TLInfo(*this) { 99 } 100 101 PTX32TargetMachine::PTX32TargetMachine(const Target &T, StringRef TT, 102 StringRef CPU, StringRef FS, 103 Reloc::Model RM, CodeModel::Model CM) 104 : PTXTargetMachine(T, TT, CPU, FS, RM, CM, false) { 105 } 106 107 PTX64TargetMachine::PTX64TargetMachine(const Target &T, StringRef TT, 108 StringRef CPU, StringRef FS, 109 Reloc::Model RM, CodeModel::Model CM) 110 : PTXTargetMachine(T, TT, CPU, FS, RM, CM, true) { 111 } 112 113 bool PTXTargetMachine::addInstSelector(PassManagerBase &PM, 114 CodeGenOpt::Level OptLevel) { 115 PM.add(createPTXISelDag(*this, OptLevel)); 116 return false; 117 } 118 119 bool PTXTargetMachine::addPostRegAlloc(PassManagerBase &PM, 120 CodeGenOpt::Level OptLevel) { 121 // PTXMFInfoExtract must after register allocation! 122 //PM.add(createPTXMFInfoExtract(*this, OptLevel)); 123 return false; 124 } 125 126 bool PTXTargetMachine::addPassesToEmitFile(PassManagerBase &PM, 127 formatted_raw_ostream &Out, 128 CodeGenFileType FileType, 129 CodeGenOpt::Level OptLevel, 130 bool DisableVerify) { 131 // This is mostly based on LLVMTargetMachine::addPassesToEmitFile 132 133 // Add common CodeGen passes. 134 MCContext *Context = 0; 135 if (addCommonCodeGenPasses(PM, OptLevel, DisableVerify, Context)) 136 return true; 137 assert(Context != 0 && "Failed to get MCContext"); 138 139 if (hasMCSaveTempLabels()) 140 Context->setAllowTemporaryLabels(false); 141 142 const MCAsmInfo &MAI = *getMCAsmInfo(); 143 const MCSubtargetInfo &STI = getSubtarget<MCSubtargetInfo>(); 144 OwningPtr<MCStreamer> AsmStreamer; 145 146 switch (FileType) { 147 default: return true; 148 case CGFT_AssemblyFile: { 149 MCInstPrinter *InstPrinter = 150 getTarget().createMCInstPrinter(MAI.getAssemblerDialect(), MAI, STI); 151 152 // Create a code emitter if asked to show the encoding. 153 MCCodeEmitter *MCE = 0; 154 MCAsmBackend *MAB = 0; 155 156 MCStreamer *S = getTarget().createAsmStreamer(*Context, Out, 157 true, /* verbose asm */ 158 hasMCUseLoc(), 159 hasMCUseCFI(), 160 hasMCUseDwarfDirectory(), 161 InstPrinter, 162 MCE, MAB, 163 false /* show MC encoding */); 164 AsmStreamer.reset(S); 165 break; 166 } 167 case CGFT_ObjectFile: { 168 llvm_unreachable("Object file emission is not supported with PTX"); 169 } 170 case CGFT_Null: 171 // The Null output is intended for use for performance analysis and testing, 172 // not real users. 173 AsmStreamer.reset(createNullStreamer(*Context)); 174 break; 175 } 176 177 // MC Logging 178 //AsmStreamer.reset(createLoggingStreamer(AsmStreamer.take(), errs())); 179 180 // Create the AsmPrinter, which takes ownership of AsmStreamer if successful. 181 FunctionPass *Printer = getTarget().createAsmPrinter(*this, *AsmStreamer); 182 if (Printer == 0) 183 return true; 184 185 // If successful, createAsmPrinter took ownership of AsmStreamer. 186 AsmStreamer.take(); 187 188 PM.add(Printer); 189 190 PM.add(createGCInfoDeleter()); 191 return false; 192 } 193 194 bool PTXTargetMachine::addCommonCodeGenPasses(PassManagerBase &PM, 195 CodeGenOpt::Level OptLevel, 196 bool DisableVerify, 197 MCContext *&OutContext) { 198 // Add standard LLVM codegen passes. 199 // This is derived from LLVMTargetMachine::addCommonCodeGenPasses, with some 200 // modifications for the PTX target. 201 202 // Standard LLVM-Level Passes. 203 204 // Basic AliasAnalysis support. 205 // Add TypeBasedAliasAnalysis before BasicAliasAnalysis so that 206 // BasicAliasAnalysis wins if they disagree. This is intended to help 207 // support "obvious" type-punning idioms. 208 PM.add(createTypeBasedAliasAnalysisPass()); 209 PM.add(createBasicAliasAnalysisPass()); 210 211 // Before running any passes, run the verifier to determine if the input 212 // coming from the front-end and/or optimizer is valid. 213 if (!DisableVerify) 214 PM.add(createVerifierPass()); 215 216 // Run loop strength reduction before anything else. 217 if (OptLevel != CodeGenOpt::None) { 218 PM.add(createLoopStrengthReducePass(getTargetLowering())); 219 //PM.add(createPrintFunctionPass("\n\n*** Code after LSR ***\n", &dbgs())); 220 } 221 222 PM.add(createGCLoweringPass()); 223 224 // Make sure that no unreachable blocks are instruction selected. 225 PM.add(createUnreachableBlockEliminationPass()); 226 227 PM.add(createLowerInvokePass(getTargetLowering())); 228 // The lower invoke pass may create unreachable code. Remove it. 229 PM.add(createUnreachableBlockEliminationPass()); 230 231 if (OptLevel != CodeGenOpt::None) 232 PM.add(createCodeGenPreparePass(getTargetLowering())); 233 234 PM.add(createStackProtectorPass(getTargetLowering())); 235 236 addPreISel(PM, OptLevel); 237 238 //PM.add(createPrintFunctionPass("\n\n" 239 // "*** Final LLVM Code input to ISel ***\n", 240 // &dbgs())); 241 242 // All passes which modify the LLVM IR are now complete; run the verifier 243 // to ensure that the IR is valid. 244 if (!DisableVerify) 245 PM.add(createVerifierPass()); 246 247 // Standard Lower-Level Passes. 248 249 // Install a MachineModuleInfo class, which is an immutable pass that holds 250 // all the per-module stuff we're generating, including MCContext. 251 MachineModuleInfo *MMI = new MachineModuleInfo(*getMCAsmInfo(), 252 *getRegisterInfo(), 253 &getTargetLowering()->getObjFileLowering()); 254 PM.add(MMI); 255 OutContext = &MMI->getContext(); // Return the MCContext specifically by-ref. 256 257 // Set up a MachineFunction for the rest of CodeGen to work on. 258 PM.add(new MachineFunctionAnalysis(*this, OptLevel)); 259 260 // Ask the target for an isel. 261 if (addInstSelector(PM, OptLevel)) 262 return true; 263 264 // Print the instruction selected machine code... 265 printAndVerify(PM, "After Instruction Selection"); 266 267 // Expand pseudo-instructions emitted by ISel. 268 PM.add(createExpandISelPseudosPass()); 269 270 // Pre-ra tail duplication. 271 if (OptLevel != CodeGenOpt::None) { 272 PM.add(createTailDuplicatePass(true)); 273 printAndVerify(PM, "After Pre-RegAlloc TailDuplicate"); 274 } 275 276 // Optimize PHIs before DCE: removing dead PHI cycles may make more 277 // instructions dead. 278 if (OptLevel != CodeGenOpt::None) 279 PM.add(createOptimizePHIsPass()); 280 281 // If the target requests it, assign local variables to stack slots relative 282 // to one another and simplify frame index references where possible. 283 PM.add(createLocalStackSlotAllocationPass()); 284 285 if (OptLevel != CodeGenOpt::None) { 286 // With optimization, dead code should already be eliminated. However 287 // there is one known exception: lowered code for arguments that are only 288 // used by tail calls, where the tail calls reuse the incoming stack 289 // arguments directly (see t11 in test/CodeGen/X86/sibcall.ll). 290 PM.add(createDeadMachineInstructionElimPass()); 291 printAndVerify(PM, "After codegen DCE pass"); 292 293 PM.add(createMachineLICMPass()); 294 PM.add(createMachineCSEPass()); 295 PM.add(createMachineSinkingPass()); 296 printAndVerify(PM, "After Machine LICM, CSE and Sinking passes"); 297 298 PM.add(createPeepholeOptimizerPass()); 299 printAndVerify(PM, "After codegen peephole optimization pass"); 300 } 301 302 // Run pre-ra passes. 303 if (addPreRegAlloc(PM, OptLevel)) 304 printAndVerify(PM, "After PreRegAlloc passes"); 305 306 // Perform register allocation. 307 PM.add(createPTXRegisterAllocator()); 308 printAndVerify(PM, "After Register Allocation"); 309 310 // Perform stack slot coloring and post-ra machine LICM. 311 if (OptLevel != CodeGenOpt::None) { 312 // FIXME: Re-enable coloring with register when it's capable of adding 313 // kill markers. 314 PM.add(createStackSlotColoringPass(false)); 315 316 // FIXME: Post-RA LICM has asserts that fire on virtual registers. 317 // Run post-ra machine LICM to hoist reloads / remats. 318 //if (!DisablePostRAMachineLICM) 319 // PM.add(createMachineLICMPass(false)); 320 321 printAndVerify(PM, "After StackSlotColoring and postra Machine LICM"); 322 } 323 324 // Run post-ra passes. 325 if (addPostRegAlloc(PM, OptLevel)) 326 printAndVerify(PM, "After PostRegAlloc passes"); 327 328 PM.add(createExpandPostRAPseudosPass()); 329 printAndVerify(PM, "After ExpandPostRAPseudos"); 330 331 // Insert prolog/epilog code. Eliminate abstract frame index references... 332 PM.add(createPrologEpilogCodeInserter()); 333 printAndVerify(PM, "After PrologEpilogCodeInserter"); 334 335 // Run pre-sched2 passes. 336 if (addPreSched2(PM, OptLevel)) 337 printAndVerify(PM, "After PreSched2 passes"); 338 339 // Second pass scheduler. 340 if (OptLevel != CodeGenOpt::None) { 341 PM.add(createPostRAScheduler(OptLevel)); 342 printAndVerify(PM, "After PostRAScheduler"); 343 } 344 345 // Branch folding must be run after regalloc and prolog/epilog insertion. 346 if (OptLevel != CodeGenOpt::None) { 347 PM.add(createBranchFoldingPass(getEnableTailMergeDefault())); 348 printNoVerify(PM, "After BranchFolding"); 349 } 350 351 // Tail duplication. 352 if (OptLevel != CodeGenOpt::None) { 353 PM.add(createTailDuplicatePass(false)); 354 printNoVerify(PM, "After TailDuplicate"); 355 } 356 357 PM.add(createGCMachineCodeAnalysisPass()); 358 359 //if (PrintGCInfo) 360 // PM.add(createGCInfoPrinter(dbgs())); 361 362 if (OptLevel != CodeGenOpt::None) { 363 PM.add(createCodePlacementOptPass()); 364 printNoVerify(PM, "After CodePlacementOpt"); 365 } 366 367 if (addPreEmitPass(PM, OptLevel)) 368 printNoVerify(PM, "After PreEmit passes"); 369 370 PM.add(createPTXMFInfoExtract(*this, OptLevel)); 371 PM.add(createPTXFPRoundingModePass(*this, OptLevel)); 372 373 return false; 374 } 375