1 //===- SparcInstrInfo.td - Target Description for Sparc Target ------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file describes the Sparc instructions in TableGen format. 11 // 12 //===----------------------------------------------------------------------===// 13 14 //===----------------------------------------------------------------------===// 15 // Instruction format superclass 16 //===----------------------------------------------------------------------===// 17 18 include "SparcInstrFormats.td" 19 20 //===----------------------------------------------------------------------===// 21 // Feature predicates. 22 //===----------------------------------------------------------------------===// 23 24 // HasV9 - This predicate is true when the target processor supports V9 25 // instructions. Note that the machine may be running in 32-bit mode. 26 def HasV9 : Predicate<"Subtarget.isV9()">; 27 28 // HasNoV9 - This predicate is true when the target doesn't have V9 29 // instructions. Use of this is just a hack for the isel not having proper 30 // costs for V8 instructions that are more expensive than their V9 ones. 31 def HasNoV9 : Predicate<"!Subtarget.isV9()">; 32 33 // HasVIS - This is true when the target processor has VIS extensions. 34 def HasVIS : Predicate<"Subtarget.isVIS()">; 35 36 // UseDeprecatedInsts - This predicate is true when the target processor is a 37 // V8, or when it is V9 but the V8 deprecated instructions are efficient enough 38 // to use when appropriate. In either of these cases, the instruction selector 39 // will pick deprecated instructions. 40 def UseDeprecatedInsts : Predicate<"Subtarget.useDeprecatedV8Instructions()">; 41 42 //===----------------------------------------------------------------------===// 43 // Instruction Pattern Stuff 44 //===----------------------------------------------------------------------===// 45 46 def simm11 : PatLeaf<(imm), [{ return isInt<11>(N->getSExtValue()); }]>; 47 48 def simm13 : PatLeaf<(imm), [{ return isInt<13>(N->getSExtValue()); }]>; 49 50 def LO10 : SDNodeXForm<imm, [{ 51 return CurDAG->getTargetConstant((unsigned)N->getZExtValue() & 1023, 52 MVT::i32); 53 }]>; 54 55 def HI22 : SDNodeXForm<imm, [{ 56 // Transformation function: shift the immediate value down into the low bits. 57 return CurDAG->getTargetConstant((unsigned)N->getZExtValue() >> 10, MVT::i32); 58 }]>; 59 60 def SETHIimm : PatLeaf<(imm), [{ 61 return (((unsigned)N->getZExtValue() >> 10) << 10) == 62 (unsigned)N->getZExtValue(); 63 }], HI22>; 64 65 // Addressing modes. 66 def ADDRrr : ComplexPattern<i32, 2, "SelectADDRrr", [], []>; 67 def ADDRri : ComplexPattern<i32, 2, "SelectADDRri", [frameindex], []>; 68 69 // Address operands 70 def MEMrr : Operand<i32> { 71 let PrintMethod = "printMemOperand"; 72 let MIOperandInfo = (ops IntRegs, IntRegs); 73 } 74 def MEMri : Operand<i32> { 75 let PrintMethod = "printMemOperand"; 76 let MIOperandInfo = (ops IntRegs, i32imm); 77 } 78 79 // Branch targets have OtherVT type. 80 def brtarget : Operand<OtherVT>; 81 def calltarget : Operand<i32>; 82 83 // Operand for printing out a condition code. 84 let PrintMethod = "printCCOperand" in 85 def CCOp : Operand<i32>; 86 87 def SDTSPcmpfcc : 88 SDTypeProfile<0, 2, [SDTCisFP<0>, SDTCisSameAs<0, 1>]>; 89 def SDTSPbrcc : 90 SDTypeProfile<0, 2, [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>; 91 def SDTSPselectcc : 92 SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32>]>; 93 def SDTSPFTOI : 94 SDTypeProfile<1, 1, [SDTCisVT<0, f32>, SDTCisFP<1>]>; 95 def SDTSPITOF : 96 SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVT<1, f32>]>; 97 98 def SPcmpicc : SDNode<"SPISD::CMPICC", SDTIntBinOp, [SDNPOutGlue]>; 99 def SPcmpfcc : SDNode<"SPISD::CMPFCC", SDTSPcmpfcc, [SDNPOutGlue]>; 100 def SPbricc : SDNode<"SPISD::BRICC", SDTSPbrcc, [SDNPHasChain, SDNPInGlue]>; 101 def SPbrfcc : SDNode<"SPISD::BRFCC", SDTSPbrcc, [SDNPHasChain, SDNPInGlue]>; 102 103 def SPhi : SDNode<"SPISD::Hi", SDTIntUnaryOp>; 104 def SPlo : SDNode<"SPISD::Lo", SDTIntUnaryOp>; 105 106 def SPftoi : SDNode<"SPISD::FTOI", SDTSPFTOI>; 107 def SPitof : SDNode<"SPISD::ITOF", SDTSPITOF>; 108 109 def SPselecticc : SDNode<"SPISD::SELECT_ICC", SDTSPselectcc, [SDNPInGlue]>; 110 def SPselectfcc : SDNode<"SPISD::SELECT_FCC", SDTSPselectcc, [SDNPInGlue]>; 111 112 // These are target-independent nodes, but have target-specific formats. 113 def SDT_SPCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>; 114 def SDT_SPCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>, 115 SDTCisVT<1, i32> ]>; 116 117 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_SPCallSeqStart, 118 [SDNPHasChain, SDNPOutGlue]>; 119 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_SPCallSeqEnd, 120 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 121 122 def SDT_SPCall : SDTypeProfile<0, -1, [SDTCisVT<0, i32>]>; 123 def call : SDNode<"SPISD::CALL", SDT_SPCall, 124 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 125 SDNPVariadic]>; 126 127 def SDT_SPRet : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>; 128 def retflag : SDNode<"SPISD::RET_FLAG", SDT_SPRet, 129 [SDNPHasChain, SDNPOptInGlue]>; 130 131 def flushw : SDNode<"SPISD::FLUSHW", SDTNone, 132 [SDNPHasChain]>; 133 134 def getPCX : Operand<i32> { 135 let PrintMethod = "printGetPCX"; 136 } 137 138 //===----------------------------------------------------------------------===// 139 // SPARC Flag Conditions 140 //===----------------------------------------------------------------------===// 141 142 // Note that these values must be kept in sync with the CCOp::CondCode enum 143 // values. 144 class ICC_VAL<int N> : PatLeaf<(i32 N)>; 145 def ICC_NE : ICC_VAL< 9>; // Not Equal 146 def ICC_E : ICC_VAL< 1>; // Equal 147 def ICC_G : ICC_VAL<10>; // Greater 148 def ICC_LE : ICC_VAL< 2>; // Less or Equal 149 def ICC_GE : ICC_VAL<11>; // Greater or Equal 150 def ICC_L : ICC_VAL< 3>; // Less 151 def ICC_GU : ICC_VAL<12>; // Greater Unsigned 152 def ICC_LEU : ICC_VAL< 4>; // Less or Equal Unsigned 153 def ICC_CC : ICC_VAL<13>; // Carry Clear/Great or Equal Unsigned 154 def ICC_CS : ICC_VAL< 5>; // Carry Set/Less Unsigned 155 def ICC_POS : ICC_VAL<14>; // Positive 156 def ICC_NEG : ICC_VAL< 6>; // Negative 157 def ICC_VC : ICC_VAL<15>; // Overflow Clear 158 def ICC_VS : ICC_VAL< 7>; // Overflow Set 159 160 class FCC_VAL<int N> : PatLeaf<(i32 N)>; 161 def FCC_U : FCC_VAL<23>; // Unordered 162 def FCC_G : FCC_VAL<22>; // Greater 163 def FCC_UG : FCC_VAL<21>; // Unordered or Greater 164 def FCC_L : FCC_VAL<20>; // Less 165 def FCC_UL : FCC_VAL<19>; // Unordered or Less 166 def FCC_LG : FCC_VAL<18>; // Less or Greater 167 def FCC_NE : FCC_VAL<17>; // Not Equal 168 def FCC_E : FCC_VAL<25>; // Equal 169 def FCC_UE : FCC_VAL<24>; // Unordered or Equal 170 def FCC_GE : FCC_VAL<25>; // Greater or Equal 171 def FCC_UGE : FCC_VAL<26>; // Unordered or Greater or Equal 172 def FCC_LE : FCC_VAL<27>; // Less or Equal 173 def FCC_ULE : FCC_VAL<28>; // Unordered or Less or Equal 174 def FCC_O : FCC_VAL<29>; // Ordered 175 176 //===----------------------------------------------------------------------===// 177 // Instruction Class Templates 178 //===----------------------------------------------------------------------===// 179 180 /// F3_12 multiclass - Define a normal F3_1/F3_2 pattern in one shot. 181 multiclass F3_12<string OpcStr, bits<6> Op3Val, SDNode OpNode> { 182 def rr : F3_1<2, Op3Val, 183 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c), 184 !strconcat(OpcStr, " $b, $c, $dst"), 185 [(set IntRegs:$dst, (OpNode IntRegs:$b, IntRegs:$c))]>; 186 def ri : F3_2<2, Op3Val, 187 (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c), 188 !strconcat(OpcStr, " $b, $c, $dst"), 189 [(set IntRegs:$dst, (OpNode IntRegs:$b, simm13:$c))]>; 190 } 191 192 /// F3_12np multiclass - Define a normal F3_1/F3_2 pattern in one shot, with no 193 /// pattern. 194 multiclass F3_12np<string OpcStr, bits<6> Op3Val> { 195 def rr : F3_1<2, Op3Val, 196 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c), 197 !strconcat(OpcStr, " $b, $c, $dst"), []>; 198 def ri : F3_2<2, Op3Val, 199 (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c), 200 !strconcat(OpcStr, " $b, $c, $dst"), []>; 201 } 202 203 //===----------------------------------------------------------------------===// 204 // Instructions 205 //===----------------------------------------------------------------------===// 206 207 // Pseudo instructions. 208 class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern> 209 : InstSP<outs, ins, asmstr, pattern>; 210 211 // GETPCX for PIC 212 let Defs = [O7] in { 213 def GETPCX : Pseudo<(outs getPCX:$getpcseq), (ins), "$getpcseq", [] >; 214 } 215 216 let Defs = [O6], Uses = [O6] in { 217 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt), 218 "!ADJCALLSTACKDOWN $amt", 219 [(callseq_start timm:$amt)]>; 220 def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2), 221 "!ADJCALLSTACKUP $amt1", 222 [(callseq_end timm:$amt1, timm:$amt2)]>; 223 } 224 225 let hasSideEffects = 1, mayStore = 1 in { 226 let rd = 0, rs1 = 0, rs2 = 0 in 227 def FLUSHW : F3_1<0b10, 0b101011, (outs), (ins), 228 "flushw", 229 [(flushw)]>, Requires<[HasV9]>; 230 let rd = 0, rs1 = 1, simm13 = 3 in 231 def TA3 : F3_2<0b10, 0b111010, (outs), (ins), 232 "ta 3", 233 [(flushw)]>; 234 } 235 236 def UNIMP : F2_1<0b000, (outs), (ins i32imm:$val), 237 "unimp $val", []>; 238 239 // FpMOVD/FpNEGD/FpABSD - These are lowered to single-precision ops by the 240 // fpmover pass. 241 let Predicates = [HasNoV9] in { // Only emit these in V8 mode. 242 def FpMOVD : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$src), 243 "!FpMOVD $src, $dst", []>; 244 def FpNEGD : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$src), 245 "!FpNEGD $src, $dst", 246 [(set DFPRegs:$dst, (fneg DFPRegs:$src))]>; 247 def FpABSD : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$src), 248 "!FpABSD $src, $dst", 249 [(set DFPRegs:$dst, (fabs DFPRegs:$src))]>; 250 } 251 252 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after 253 // instruction selection into a branch sequence. This has to handle all 254 // permutations of selection between i32/f32/f64 on ICC and FCC. 255 // Expanded after instruction selection. 256 let Uses = [ICC], usesCustomInserter = 1 in { 257 def SELECT_CC_Int_ICC 258 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, i32imm:$Cond), 259 "; SELECT_CC_Int_ICC PSEUDO!", 260 [(set IntRegs:$dst, (SPselecticc IntRegs:$T, IntRegs:$F, 261 imm:$Cond))]>; 262 def SELECT_CC_FP_ICC 263 : Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, i32imm:$Cond), 264 "; SELECT_CC_FP_ICC PSEUDO!", 265 [(set FPRegs:$dst, (SPselecticc FPRegs:$T, FPRegs:$F, 266 imm:$Cond))]>; 267 268 def SELECT_CC_DFP_ICC 269 : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$T, DFPRegs:$F, i32imm:$Cond), 270 "; SELECT_CC_DFP_ICC PSEUDO!", 271 [(set DFPRegs:$dst, (SPselecticc DFPRegs:$T, DFPRegs:$F, 272 imm:$Cond))]>; 273 } 274 275 let usesCustomInserter = 1, Uses = [FCC] in { 276 277 def SELECT_CC_Int_FCC 278 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, i32imm:$Cond), 279 "; SELECT_CC_Int_FCC PSEUDO!", 280 [(set IntRegs:$dst, (SPselectfcc IntRegs:$T, IntRegs:$F, 281 imm:$Cond))]>; 282 283 def SELECT_CC_FP_FCC 284 : Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, i32imm:$Cond), 285 "; SELECT_CC_FP_FCC PSEUDO!", 286 [(set FPRegs:$dst, (SPselectfcc FPRegs:$T, FPRegs:$F, 287 imm:$Cond))]>; 288 def SELECT_CC_DFP_FCC 289 : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$T, DFPRegs:$F, i32imm:$Cond), 290 "; SELECT_CC_DFP_FCC PSEUDO!", 291 [(set DFPRegs:$dst, (SPselectfcc DFPRegs:$T, DFPRegs:$F, 292 imm:$Cond))]>; 293 } 294 295 296 // Section A.3 - Synthetic Instructions, p. 85 297 // special cases of JMPL: 298 let isReturn = 1, isTerminator = 1, hasDelaySlot = 1, isBarrier = 1 in { 299 let rd = O7.Num, rs1 = G0.Num in 300 def RETL: F3_2<2, 0b111000, (outs), (ins i32imm:$val), 301 "jmp %o7+$val", [(retflag simm13:$val)]>; 302 303 let rd = I7.Num, rs1 = G0.Num in 304 def RET: F3_2<2, 0b111000, (outs), (ins i32imm:$val), 305 "jmp %i7+$val", []>; 306 } 307 308 // Section B.1 - Load Integer Instructions, p. 90 309 def LDSBrr : F3_1<3, 0b001001, 310 (outs IntRegs:$dst), (ins MEMrr:$addr), 311 "ldsb [$addr], $dst", 312 [(set IntRegs:$dst, (sextloadi8 ADDRrr:$addr))]>; 313 def LDSBri : F3_2<3, 0b001001, 314 (outs IntRegs:$dst), (ins MEMri:$addr), 315 "ldsb [$addr], $dst", 316 [(set IntRegs:$dst, (sextloadi8 ADDRri:$addr))]>; 317 def LDSHrr : F3_1<3, 0b001010, 318 (outs IntRegs:$dst), (ins MEMrr:$addr), 319 "ldsh [$addr], $dst", 320 [(set IntRegs:$dst, (sextloadi16 ADDRrr:$addr))]>; 321 def LDSHri : F3_2<3, 0b001010, 322 (outs IntRegs:$dst), (ins MEMri:$addr), 323 "ldsh [$addr], $dst", 324 [(set IntRegs:$dst, (sextloadi16 ADDRri:$addr))]>; 325 def LDUBrr : F3_1<3, 0b000001, 326 (outs IntRegs:$dst), (ins MEMrr:$addr), 327 "ldub [$addr], $dst", 328 [(set IntRegs:$dst, (zextloadi8 ADDRrr:$addr))]>; 329 def LDUBri : F3_2<3, 0b000001, 330 (outs IntRegs:$dst), (ins MEMri:$addr), 331 "ldub [$addr], $dst", 332 [(set IntRegs:$dst, (zextloadi8 ADDRri:$addr))]>; 333 def LDUHrr : F3_1<3, 0b000010, 334 (outs IntRegs:$dst), (ins MEMrr:$addr), 335 "lduh [$addr], $dst", 336 [(set IntRegs:$dst, (zextloadi16 ADDRrr:$addr))]>; 337 def LDUHri : F3_2<3, 0b000010, 338 (outs IntRegs:$dst), (ins MEMri:$addr), 339 "lduh [$addr], $dst", 340 [(set IntRegs:$dst, (zextloadi16 ADDRri:$addr))]>; 341 def LDrr : F3_1<3, 0b000000, 342 (outs IntRegs:$dst), (ins MEMrr:$addr), 343 "ld [$addr], $dst", 344 [(set IntRegs:$dst, (load ADDRrr:$addr))]>; 345 def LDri : F3_2<3, 0b000000, 346 (outs IntRegs:$dst), (ins MEMri:$addr), 347 "ld [$addr], $dst", 348 [(set IntRegs:$dst, (load ADDRri:$addr))]>; 349 350 // Section B.2 - Load Floating-point Instructions, p. 92 351 def LDFrr : F3_1<3, 0b100000, 352 (outs FPRegs:$dst), (ins MEMrr:$addr), 353 "ld [$addr], $dst", 354 [(set FPRegs:$dst, (load ADDRrr:$addr))]>; 355 def LDFri : F3_2<3, 0b100000, 356 (outs FPRegs:$dst), (ins MEMri:$addr), 357 "ld [$addr], $dst", 358 [(set FPRegs:$dst, (load ADDRri:$addr))]>; 359 def LDDFrr : F3_1<3, 0b100011, 360 (outs DFPRegs:$dst), (ins MEMrr:$addr), 361 "ldd [$addr], $dst", 362 [(set DFPRegs:$dst, (load ADDRrr:$addr))]>; 363 def LDDFri : F3_2<3, 0b100011, 364 (outs DFPRegs:$dst), (ins MEMri:$addr), 365 "ldd [$addr], $dst", 366 [(set DFPRegs:$dst, (load ADDRri:$addr))]>; 367 368 // Section B.4 - Store Integer Instructions, p. 95 369 def STBrr : F3_1<3, 0b000101, 370 (outs), (ins MEMrr:$addr, IntRegs:$src), 371 "stb $src, [$addr]", 372 [(truncstorei8 IntRegs:$src, ADDRrr:$addr)]>; 373 def STBri : F3_2<3, 0b000101, 374 (outs), (ins MEMri:$addr, IntRegs:$src), 375 "stb $src, [$addr]", 376 [(truncstorei8 IntRegs:$src, ADDRri:$addr)]>; 377 def STHrr : F3_1<3, 0b000110, 378 (outs), (ins MEMrr:$addr, IntRegs:$src), 379 "sth $src, [$addr]", 380 [(truncstorei16 IntRegs:$src, ADDRrr:$addr)]>; 381 def STHri : F3_2<3, 0b000110, 382 (outs), (ins MEMri:$addr, IntRegs:$src), 383 "sth $src, [$addr]", 384 [(truncstorei16 IntRegs:$src, ADDRri:$addr)]>; 385 def STrr : F3_1<3, 0b000100, 386 (outs), (ins MEMrr:$addr, IntRegs:$src), 387 "st $src, [$addr]", 388 [(store IntRegs:$src, ADDRrr:$addr)]>; 389 def STri : F3_2<3, 0b000100, 390 (outs), (ins MEMri:$addr, IntRegs:$src), 391 "st $src, [$addr]", 392 [(store IntRegs:$src, ADDRri:$addr)]>; 393 394 // Section B.5 - Store Floating-point Instructions, p. 97 395 def STFrr : F3_1<3, 0b100100, 396 (outs), (ins MEMrr:$addr, FPRegs:$src), 397 "st $src, [$addr]", 398 [(store FPRegs:$src, ADDRrr:$addr)]>; 399 def STFri : F3_2<3, 0b100100, 400 (outs), (ins MEMri:$addr, FPRegs:$src), 401 "st $src, [$addr]", 402 [(store FPRegs:$src, ADDRri:$addr)]>; 403 def STDFrr : F3_1<3, 0b100111, 404 (outs), (ins MEMrr:$addr, DFPRegs:$src), 405 "std $src, [$addr]", 406 [(store DFPRegs:$src, ADDRrr:$addr)]>; 407 def STDFri : F3_2<3, 0b100111, 408 (outs), (ins MEMri:$addr, DFPRegs:$src), 409 "std $src, [$addr]", 410 [(store DFPRegs:$src, ADDRri:$addr)]>; 411 412 // Section B.9 - SETHI Instruction, p. 104 413 def SETHIi: F2_1<0b100, 414 (outs IntRegs:$dst), (ins i32imm:$src), 415 "sethi $src, $dst", 416 [(set IntRegs:$dst, SETHIimm:$src)]>; 417 418 // Section B.10 - NOP Instruction, p. 105 419 // (It's a special case of SETHI) 420 let rd = 0, imm22 = 0 in 421 def NOP : F2_1<0b100, (outs), (ins), "nop", []>; 422 423 // Section B.11 - Logical Instructions, p. 106 424 defm AND : F3_12<"and", 0b000001, and>; 425 426 def ANDNrr : F3_1<2, 0b000101, 427 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c), 428 "andn $b, $c, $dst", 429 [(set IntRegs:$dst, (and IntRegs:$b, (not IntRegs:$c)))]>; 430 def ANDNri : F3_2<2, 0b000101, 431 (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c), 432 "andn $b, $c, $dst", []>; 433 434 defm OR : F3_12<"or", 0b000010, or>; 435 436 def ORNrr : F3_1<2, 0b000110, 437 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c), 438 "orn $b, $c, $dst", 439 [(set IntRegs:$dst, (or IntRegs:$b, (not IntRegs:$c)))]>; 440 def ORNri : F3_2<2, 0b000110, 441 (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c), 442 "orn $b, $c, $dst", []>; 443 defm XOR : F3_12<"xor", 0b000011, xor>; 444 445 def XNORrr : F3_1<2, 0b000111, 446 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c), 447 "xnor $b, $c, $dst", 448 [(set IntRegs:$dst, (not (xor IntRegs:$b, IntRegs:$c)))]>; 449 def XNORri : F3_2<2, 0b000111, 450 (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c), 451 "xnor $b, $c, $dst", []>; 452 453 // Section B.12 - Shift Instructions, p. 107 454 defm SLL : F3_12<"sll", 0b100101, shl>; 455 defm SRL : F3_12<"srl", 0b100110, srl>; 456 defm SRA : F3_12<"sra", 0b100111, sra>; 457 458 // Section B.13 - Add Instructions, p. 108 459 defm ADD : F3_12<"add", 0b000000, add>; 460 461 // "LEA" forms of add (patterns to make tblgen happy) 462 def LEA_ADDri : F3_2<2, 0b000000, 463 (outs IntRegs:$dst), (ins MEMri:$addr), 464 "add ${addr:arith}, $dst", 465 [(set IntRegs:$dst, ADDRri:$addr)]>; 466 467 let Defs = [ICC] in 468 defm ADDCC : F3_12<"addcc", 0b010000, addc>; 469 470 let Uses = [ICC] in 471 defm ADDX : F3_12<"addx", 0b001000, adde>; 472 473 // Section B.15 - Subtract Instructions, p. 110 474 defm SUB : F3_12 <"sub" , 0b000100, sub>; 475 let Uses = [ICC] in 476 defm SUBX : F3_12 <"subx" , 0b001100, sube>; 477 478 let Defs = [ICC] in 479 defm SUBCC : F3_12 <"subcc", 0b010100, SPcmpicc>; 480 481 let Uses = [ICC], Defs = [ICC] in 482 def SUBXCCrr: F3_1<2, 0b011100, 483 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c), 484 "subxcc $b, $c, $dst", []>; 485 486 487 // Section B.18 - Multiply Instructions, p. 113 488 let Defs = [Y] in { 489 defm UMUL : F3_12np<"umul", 0b001010>; 490 defm SMUL : F3_12 <"smul", 0b001011, mul>; 491 } 492 493 // Section B.19 - Divide Instructions, p. 115 494 let Defs = [Y] in { 495 defm UDIV : F3_12np<"udiv", 0b001110>; 496 defm SDIV : F3_12np<"sdiv", 0b001111>; 497 } 498 499 // Section B.20 - SAVE and RESTORE, p. 117 500 defm SAVE : F3_12np<"save" , 0b111100>; 501 defm RESTORE : F3_12np<"restore", 0b111101>; 502 503 // Section B.21 - Branch on Integer Condition Codes Instructions, p. 119 504 505 // conditional branch class: 506 class BranchSP<bits<4> cc, dag ins, string asmstr, list<dag> pattern> 507 : F2_2<cc, 0b010, (outs), ins, asmstr, pattern> { 508 let isBranch = 1; 509 let isTerminator = 1; 510 let hasDelaySlot = 1; 511 } 512 513 let isBarrier = 1 in 514 def BA : BranchSP<0b1000, (ins brtarget:$dst), 515 "ba $dst", 516 [(br bb:$dst)]>; 517 518 // FIXME: the encoding for the JIT should look at the condition field. 519 let Uses = [ICC] in 520 def BCOND : BranchSP<0, (ins brtarget:$dst, CCOp:$cc), 521 "b$cc $dst", 522 [(SPbricc bb:$dst, imm:$cc)]>; 523 524 525 // Section B.22 - Branch on Floating-point Condition Codes Instructions, p. 121 526 527 // floating-point conditional branch class: 528 class FPBranchSP<bits<4> cc, dag ins, string asmstr, list<dag> pattern> 529 : F2_2<cc, 0b110, (outs), ins, asmstr, pattern> { 530 let isBranch = 1; 531 let isTerminator = 1; 532 let hasDelaySlot = 1; 533 } 534 535 // FIXME: the encoding for the JIT should look at the condition field. 536 let Uses = [FCC] in 537 def FBCOND : FPBranchSP<0, (ins brtarget:$dst, CCOp:$cc), 538 "fb$cc $dst", 539 [(SPbrfcc bb:$dst, imm:$cc)]>; 540 541 542 // Section B.24 - Call and Link Instruction, p. 125 543 // This is the only Format 1 instruction 544 let Uses = [O6], 545 hasDelaySlot = 1, isCall = 1, 546 Defs = [O0, O1, O2, O3, O4, O5, O7, G1, G2, G3, G4, G5, G6, G7, 547 D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15, 548 ICC, FCC, Y] in { 549 def CALL : InstSP<(outs), (ins calltarget:$dst, variable_ops), 550 "call $dst", []> { 551 bits<30> disp; 552 let op = 1; 553 let Inst{29-0} = disp; 554 } 555 556 // indirect calls 557 def JMPLrr : F3_1<2, 0b111000, 558 (outs), (ins MEMrr:$ptr, variable_ops), 559 "call $ptr", 560 [(call ADDRrr:$ptr)]>; 561 def JMPLri : F3_2<2, 0b111000, 562 (outs), (ins MEMri:$ptr, variable_ops), 563 "call $ptr", 564 [(call ADDRri:$ptr)]>; 565 } 566 567 // Section B.28 - Read State Register Instructions 568 let Uses = [Y] in 569 def RDY : F3_1<2, 0b101000, 570 (outs IntRegs:$dst), (ins), 571 "rd %y, $dst", []>; 572 573 // Section B.29 - Write State Register Instructions 574 let Defs = [Y] in { 575 def WRYrr : F3_1<2, 0b110000, 576 (outs), (ins IntRegs:$b, IntRegs:$c), 577 "wr $b, $c, %y", []>; 578 def WRYri : F3_2<2, 0b110000, 579 (outs), (ins IntRegs:$b, i32imm:$c), 580 "wr $b, $c, %y", []>; 581 } 582 // Convert Integer to Floating-point Instructions, p. 141 583 def FITOS : F3_3<2, 0b110100, 0b011000100, 584 (outs FPRegs:$dst), (ins FPRegs:$src), 585 "fitos $src, $dst", 586 [(set FPRegs:$dst, (SPitof FPRegs:$src))]>; 587 def FITOD : F3_3<2, 0b110100, 0b011001000, 588 (outs DFPRegs:$dst), (ins FPRegs:$src), 589 "fitod $src, $dst", 590 [(set DFPRegs:$dst, (SPitof FPRegs:$src))]>; 591 592 // Convert Floating-point to Integer Instructions, p. 142 593 def FSTOI : F3_3<2, 0b110100, 0b011010001, 594 (outs FPRegs:$dst), (ins FPRegs:$src), 595 "fstoi $src, $dst", 596 [(set FPRegs:$dst, (SPftoi FPRegs:$src))]>; 597 def FDTOI : F3_3<2, 0b110100, 0b011010010, 598 (outs FPRegs:$dst), (ins DFPRegs:$src), 599 "fdtoi $src, $dst", 600 [(set FPRegs:$dst, (SPftoi DFPRegs:$src))]>; 601 602 // Convert between Floating-point Formats Instructions, p. 143 603 def FSTOD : F3_3<2, 0b110100, 0b011001001, 604 (outs DFPRegs:$dst), (ins FPRegs:$src), 605 "fstod $src, $dst", 606 [(set DFPRegs:$dst, (fextend FPRegs:$src))]>; 607 def FDTOS : F3_3<2, 0b110100, 0b011000110, 608 (outs FPRegs:$dst), (ins DFPRegs:$src), 609 "fdtos $src, $dst", 610 [(set FPRegs:$dst, (fround DFPRegs:$src))]>; 611 612 // Floating-point Move Instructions, p. 144 613 def FMOVS : F3_3<2, 0b110100, 0b000000001, 614 (outs FPRegs:$dst), (ins FPRegs:$src), 615 "fmovs $src, $dst", []>; 616 def FNEGS : F3_3<2, 0b110100, 0b000000101, 617 (outs FPRegs:$dst), (ins FPRegs:$src), 618 "fnegs $src, $dst", 619 [(set FPRegs:$dst, (fneg FPRegs:$src))]>; 620 def FABSS : F3_3<2, 0b110100, 0b000001001, 621 (outs FPRegs:$dst), (ins FPRegs:$src), 622 "fabss $src, $dst", 623 [(set FPRegs:$dst, (fabs FPRegs:$src))]>; 624 625 626 // Floating-point Square Root Instructions, p.145 627 def FSQRTS : F3_3<2, 0b110100, 0b000101001, 628 (outs FPRegs:$dst), (ins FPRegs:$src), 629 "fsqrts $src, $dst", 630 [(set FPRegs:$dst, (fsqrt FPRegs:$src))]>; 631 def FSQRTD : F3_3<2, 0b110100, 0b000101010, 632 (outs DFPRegs:$dst), (ins DFPRegs:$src), 633 "fsqrtd $src, $dst", 634 [(set DFPRegs:$dst, (fsqrt DFPRegs:$src))]>; 635 636 637 638 // Floating-point Add and Subtract Instructions, p. 146 639 def FADDS : F3_3<2, 0b110100, 0b001000001, 640 (outs FPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2), 641 "fadds $src1, $src2, $dst", 642 [(set FPRegs:$dst, (fadd FPRegs:$src1, FPRegs:$src2))]>; 643 def FADDD : F3_3<2, 0b110100, 0b001000010, 644 (outs DFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2), 645 "faddd $src1, $src2, $dst", 646 [(set DFPRegs:$dst, (fadd DFPRegs:$src1, DFPRegs:$src2))]>; 647 def FSUBS : F3_3<2, 0b110100, 0b001000101, 648 (outs FPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2), 649 "fsubs $src1, $src2, $dst", 650 [(set FPRegs:$dst, (fsub FPRegs:$src1, FPRegs:$src2))]>; 651 def FSUBD : F3_3<2, 0b110100, 0b001000110, 652 (outs DFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2), 653 "fsubd $src1, $src2, $dst", 654 [(set DFPRegs:$dst, (fsub DFPRegs:$src1, DFPRegs:$src2))]>; 655 656 // Floating-point Multiply and Divide Instructions, p. 147 657 def FMULS : F3_3<2, 0b110100, 0b001001001, 658 (outs FPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2), 659 "fmuls $src1, $src2, $dst", 660 [(set FPRegs:$dst, (fmul FPRegs:$src1, FPRegs:$src2))]>; 661 def FMULD : F3_3<2, 0b110100, 0b001001010, 662 (outs DFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2), 663 "fmuld $src1, $src2, $dst", 664 [(set DFPRegs:$dst, (fmul DFPRegs:$src1, DFPRegs:$src2))]>; 665 def FSMULD : F3_3<2, 0b110100, 0b001101001, 666 (outs DFPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2), 667 "fsmuld $src1, $src2, $dst", 668 [(set DFPRegs:$dst, (fmul (fextend FPRegs:$src1), 669 (fextend FPRegs:$src2)))]>; 670 def FDIVS : F3_3<2, 0b110100, 0b001001101, 671 (outs FPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2), 672 "fdivs $src1, $src2, $dst", 673 [(set FPRegs:$dst, (fdiv FPRegs:$src1, FPRegs:$src2))]>; 674 def FDIVD : F3_3<2, 0b110100, 0b001001110, 675 (outs DFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2), 676 "fdivd $src1, $src2, $dst", 677 [(set DFPRegs:$dst, (fdiv DFPRegs:$src1, DFPRegs:$src2))]>; 678 679 // Floating-point Compare Instructions, p. 148 680 // Note: the 2nd template arg is different for these guys. 681 // Note 2: the result of a FCMP is not available until the 2nd cycle 682 // after the instr is retired, but there is no interlock. This behavior 683 // is modelled with a forced noop after the instruction. 684 let Defs = [FCC] in { 685 def FCMPS : F3_3<2, 0b110101, 0b001010001, 686 (outs), (ins FPRegs:$src1, FPRegs:$src2), 687 "fcmps $src1, $src2\n\tnop", 688 [(SPcmpfcc FPRegs:$src1, FPRegs:$src2)]>; 689 def FCMPD : F3_3<2, 0b110101, 0b001010010, 690 (outs), (ins DFPRegs:$src1, DFPRegs:$src2), 691 "fcmpd $src1, $src2\n\tnop", 692 [(SPcmpfcc DFPRegs:$src1, DFPRegs:$src2)]>; 693 } 694 695 //===----------------------------------------------------------------------===// 696 // V9 Instructions 697 //===----------------------------------------------------------------------===// 698 699 // V9 Conditional Moves. 700 let Predicates = [HasV9], Constraints = "$T = $dst" in { 701 // Move Integer Register on Condition (MOVcc) p. 194 of the V9 manual. 702 // FIXME: Add instruction encodings for the JIT some day. 703 let Uses = [ICC] in { 704 def MOVICCrr 705 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, CCOp:$cc), 706 "mov$cc %icc, $F, $dst", 707 [(set IntRegs:$dst, 708 (SPselecticc IntRegs:$F, IntRegs:$T, imm:$cc))]>; 709 def MOVICCri 710 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, i32imm:$F, CCOp:$cc), 711 "mov$cc %icc, $F, $dst", 712 [(set IntRegs:$dst, 713 (SPselecticc simm11:$F, IntRegs:$T, imm:$cc))]>; 714 } 715 716 let Uses = [FCC] in { 717 def MOVFCCrr 718 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, CCOp:$cc), 719 "mov$cc %fcc0, $F, $dst", 720 [(set IntRegs:$dst, 721 (SPselectfcc IntRegs:$F, IntRegs:$T, imm:$cc))]>; 722 def MOVFCCri 723 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, i32imm:$F, CCOp:$cc), 724 "mov$cc %fcc0, $F, $dst", 725 [(set IntRegs:$dst, 726 (SPselectfcc simm11:$F, IntRegs:$T, imm:$cc))]>; 727 } 728 729 let Uses = [ICC] in { 730 def FMOVS_ICC 731 : Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, CCOp:$cc), 732 "fmovs$cc %icc, $F, $dst", 733 [(set FPRegs:$dst, 734 (SPselecticc FPRegs:$F, FPRegs:$T, imm:$cc))]>; 735 def FMOVD_ICC 736 : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$T, DFPRegs:$F, CCOp:$cc), 737 "fmovd$cc %icc, $F, $dst", 738 [(set DFPRegs:$dst, 739 (SPselecticc DFPRegs:$F, DFPRegs:$T, imm:$cc))]>; 740 } 741 742 let Uses = [FCC] in { 743 def FMOVS_FCC 744 : Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, CCOp:$cc), 745 "fmovs$cc %fcc0, $F, $dst", 746 [(set FPRegs:$dst, 747 (SPselectfcc FPRegs:$F, FPRegs:$T, imm:$cc))]>; 748 def FMOVD_FCC 749 : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$T, DFPRegs:$F, CCOp:$cc), 750 "fmovd$cc %fcc0, $F, $dst", 751 [(set DFPRegs:$dst, 752 (SPselectfcc DFPRegs:$F, DFPRegs:$T, imm:$cc))]>; 753 } 754 755 } 756 757 // Floating-Point Move Instructions, p. 164 of the V9 manual. 758 let Predicates = [HasV9] in { 759 def FMOVD : F3_3<2, 0b110100, 0b000000010, 760 (outs DFPRegs:$dst), (ins DFPRegs:$src), 761 "fmovd $src, $dst", []>; 762 def FNEGD : F3_3<2, 0b110100, 0b000000110, 763 (outs DFPRegs:$dst), (ins DFPRegs:$src), 764 "fnegd $src, $dst", 765 [(set DFPRegs:$dst, (fneg DFPRegs:$src))]>; 766 def FABSD : F3_3<2, 0b110100, 0b000001010, 767 (outs DFPRegs:$dst), (ins DFPRegs:$src), 768 "fabsd $src, $dst", 769 [(set DFPRegs:$dst, (fabs DFPRegs:$src))]>; 770 } 771 772 // POPCrr - This does a ctpop of a 64-bit register. As such, we have to clear 773 // the top 32-bits before using it. To do this clearing, we use a SLLri X,0. 774 def POPCrr : F3_1<2, 0b101110, 775 (outs IntRegs:$dst), (ins IntRegs:$src), 776 "popc $src, $dst", []>, Requires<[HasV9]>; 777 def : Pat<(ctpop IntRegs:$src), 778 (POPCrr (SLLri IntRegs:$src, 0))>; 779 780 //===----------------------------------------------------------------------===// 781 // Non-Instruction Patterns 782 //===----------------------------------------------------------------------===// 783 784 // Small immediates. 785 def : Pat<(i32 simm13:$val), 786 (ORri G0, imm:$val)>; 787 // Arbitrary immediates. 788 def : Pat<(i32 imm:$val), 789 (ORri (SETHIi (HI22 imm:$val)), (LO10 imm:$val))>; 790 791 // subc 792 def : Pat<(subc IntRegs:$b, IntRegs:$c), 793 (SUBCCrr IntRegs:$b, IntRegs:$c)>; 794 def : Pat<(subc IntRegs:$b, simm13:$val), 795 (SUBCCri IntRegs:$b, imm:$val)>; 796 797 // Global addresses, constant pool entries 798 def : Pat<(SPhi tglobaladdr:$in), (SETHIi tglobaladdr:$in)>; 799 def : Pat<(SPlo tglobaladdr:$in), (ORri G0, tglobaladdr:$in)>; 800 def : Pat<(SPhi tconstpool:$in), (SETHIi tconstpool:$in)>; 801 def : Pat<(SPlo tconstpool:$in), (ORri G0, tconstpool:$in)>; 802 803 // Add reg, lo. This is used when taking the addr of a global/constpool entry. 804 def : Pat<(add IntRegs:$r, (SPlo tglobaladdr:$in)), 805 (ADDri IntRegs:$r, tglobaladdr:$in)>; 806 def : Pat<(add IntRegs:$r, (SPlo tconstpool:$in)), 807 (ADDri IntRegs:$r, tconstpool:$in)>; 808 809 // Calls: 810 def : Pat<(call tglobaladdr:$dst), 811 (CALL tglobaladdr:$dst)>; 812 def : Pat<(call texternalsym:$dst), 813 (CALL texternalsym:$dst)>; 814 815 // Map integer extload's to zextloads. 816 def : Pat<(i32 (extloadi1 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>; 817 def : Pat<(i32 (extloadi1 ADDRri:$src)), (LDUBri ADDRri:$src)>; 818 def : Pat<(i32 (extloadi8 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>; 819 def : Pat<(i32 (extloadi8 ADDRri:$src)), (LDUBri ADDRri:$src)>; 820 def : Pat<(i32 (extloadi16 ADDRrr:$src)), (LDUHrr ADDRrr:$src)>; 821 def : Pat<(i32 (extloadi16 ADDRri:$src)), (LDUHri ADDRri:$src)>; 822 823 // zextload bool -> zextload byte 824 def : Pat<(i32 (zextloadi1 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>; 825 def : Pat<(i32 (zextloadi1 ADDRri:$src)), (LDUBri ADDRri:$src)>; 826
