1 //===- SystemZRegisterInfo.td - The PowerPC Register File ------*- tablegen -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // 11 //===----------------------------------------------------------------------===// 12 13 class SystemZReg<string n> : Register<n> { 14 let Namespace = "SystemZ"; 15 } 16 17 class SystemZRegWithSubregs<string n, list<Register> subregs> 18 : RegisterWithSubRegs<n, subregs> { 19 let Namespace = "SystemZ"; 20 } 21 22 // We identify all our registers with a 4-bit ID, for consistency's sake. 23 24 // GPR32 - Lower 32 bits of one of the 16 64-bit general-purpose registers 25 class GPR32<bits<4> num, string n> : SystemZReg<n> { 26 field bits<4> Num = num; 27 } 28 29 // GPR64 - One of the 16 64-bit general-purpose registers 30 class GPR64<bits<4> num, string n, list<Register> subregs, 31 list<Register> aliases = []> 32 : SystemZRegWithSubregs<n, subregs> { 33 field bits<4> Num = num; 34 let Aliases = aliases; 35 } 36 37 // GPR128 - 8 even-odd register pairs 38 class GPR128<bits<4> num, string n, list<Register> subregs, 39 list<Register> aliases = []> 40 : SystemZRegWithSubregs<n, subregs> { 41 field bits<4> Num = num; 42 let Aliases = aliases; 43 } 44 45 // FPRS - Lower 32 bits of one of the 16 64-bit floating-point registers 46 class FPRS<bits<4> num, string n> : SystemZReg<n> { 47 field bits<4> Num = num; 48 } 49 50 // FPRL - One of the 16 64-bit floating-point registers 51 class FPRL<bits<4> num, string n, list<Register> subregs> 52 : SystemZRegWithSubregs<n, subregs> { 53 field bits<4> Num = num; 54 } 55 56 let Namespace = "SystemZ" in { 57 def subreg_32bit : SubRegIndex; 58 def subreg_odd32 : SubRegIndex; 59 def subreg_even : SubRegIndex; 60 def subreg_odd : SubRegIndex; 61 } 62 63 // General-purpose registers 64 def R0W : GPR32< 0, "r0">; 65 def R1W : GPR32< 1, "r1">; 66 def R2W : GPR32< 2, "r2">; 67 def R3W : GPR32< 3, "r3">; 68 def R4W : GPR32< 4, "r4">; 69 def R5W : GPR32< 5, "r5">; 70 def R6W : GPR32< 6, "r6">; 71 def R7W : GPR32< 7, "r7">; 72 def R8W : GPR32< 8, "r8">; 73 def R9W : GPR32< 9, "r9">; 74 def R10W : GPR32<10, "r10">; 75 def R11W : GPR32<11, "r11">; 76 def R12W : GPR32<12, "r12">; 77 def R13W : GPR32<13, "r13">; 78 def R14W : GPR32<14, "r14">; 79 def R15W : GPR32<15, "r15">; 80 81 let SubRegIndices = [subreg_32bit] in { 82 def R0D : GPR64< 0, "r0", [R0W]>, DwarfRegNum<[0]>; 83 def R1D : GPR64< 1, "r1", [R1W]>, DwarfRegNum<[1]>; 84 def R2D : GPR64< 2, "r2", [R2W]>, DwarfRegNum<[2]>; 85 def R3D : GPR64< 3, "r3", [R3W]>, DwarfRegNum<[3]>; 86 def R4D : GPR64< 4, "r4", [R4W]>, DwarfRegNum<[4]>; 87 def R5D : GPR64< 5, "r5", [R5W]>, DwarfRegNum<[5]>; 88 def R6D : GPR64< 6, "r6", [R6W]>, DwarfRegNum<[6]>; 89 def R7D : GPR64< 7, "r7", [R7W]>, DwarfRegNum<[7]>; 90 def R8D : GPR64< 8, "r8", [R8W]>, DwarfRegNum<[8]>; 91 def R9D : GPR64< 9, "r9", [R9W]>, DwarfRegNum<[9]>; 92 def R10D : GPR64<10, "r10", [R10W]>, DwarfRegNum<[10]>; 93 def R11D : GPR64<11, "r11", [R11W]>, DwarfRegNum<[11]>; 94 def R12D : GPR64<12, "r12", [R12W]>, DwarfRegNum<[12]>; 95 def R13D : GPR64<13, "r13", [R13W]>, DwarfRegNum<[13]>; 96 def R14D : GPR64<14, "r14", [R14W]>, DwarfRegNum<[14]>; 97 def R15D : GPR64<15, "r15", [R15W]>, DwarfRegNum<[15]>; 98 } 99 100 // Register pairs 101 let SubRegIndices = [subreg_32bit, subreg_odd32] in { 102 def R0P : GPR64< 0, "r0", [R0W, R1W], [R0D, R1D]>; 103 def R2P : GPR64< 2, "r2", [R2W, R3W], [R2D, R3D]>; 104 def R4P : GPR64< 4, "r4", [R4W, R5W], [R4D, R5D]>; 105 def R6P : GPR64< 6, "r6", [R6W, R7W], [R6D, R7D]>; 106 def R8P : GPR64< 8, "r8", [R8W, R9W], [R8D, R9D]>; 107 def R10P : GPR64<10, "r10", [R10W, R11W], [R10D, R11D]>; 108 def R12P : GPR64<12, "r12", [R12W, R13W], [R12D, R13D]>; 109 def R14P : GPR64<14, "r14", [R14W, R15W], [R14D, R15D]>; 110 } 111 112 let SubRegIndices = [subreg_even, subreg_odd], 113 CompositeIndices = [(subreg_odd32 subreg_odd, subreg_32bit)] in { 114 def R0Q : GPR128< 0, "r0", [R0D, R1D], [R0P]>; 115 def R2Q : GPR128< 2, "r2", [R2D, R3D], [R2P]>; 116 def R4Q : GPR128< 4, "r4", [R4D, R5D], [R4P]>; 117 def R6Q : GPR128< 6, "r6", [R6D, R7D], [R6P]>; 118 def R8Q : GPR128< 8, "r8", [R8D, R9D], [R8P]>; 119 def R10Q : GPR128<10, "r10", [R10D, R11D], [R10P]>; 120 def R12Q : GPR128<12, "r12", [R12D, R13D], [R12P]>; 121 def R14Q : GPR128<14, "r14", [R14D, R15D], [R14P]>; 122 } 123 124 // Floating-point registers 125 def F0S : FPRS< 0, "f0">, DwarfRegNum<[16]>; 126 def F1S : FPRS< 1, "f1">, DwarfRegNum<[17]>; 127 def F2S : FPRS< 2, "f2">, DwarfRegNum<[18]>; 128 def F3S : FPRS< 3, "f3">, DwarfRegNum<[19]>; 129 def F4S : FPRS< 4, "f4">, DwarfRegNum<[20]>; 130 def F5S : FPRS< 5, "f5">, DwarfRegNum<[21]>; 131 def F6S : FPRS< 6, "f6">, DwarfRegNum<[22]>; 132 def F7S : FPRS< 7, "f7">, DwarfRegNum<[23]>; 133 def F8S : FPRS< 8, "f8">, DwarfRegNum<[24]>; 134 def F9S : FPRS< 9, "f9">, DwarfRegNum<[25]>; 135 def F10S : FPRS<10, "f10">, DwarfRegNum<[26]>; 136 def F11S : FPRS<11, "f11">, DwarfRegNum<[27]>; 137 def F12S : FPRS<12, "f12">, DwarfRegNum<[28]>; 138 def F13S : FPRS<13, "f13">, DwarfRegNum<[29]>; 139 def F14S : FPRS<14, "f14">, DwarfRegNum<[30]>; 140 def F15S : FPRS<15, "f15">, DwarfRegNum<[31]>; 141 142 let SubRegIndices = [subreg_32bit] in { 143 def F0L : FPRL< 0, "f0", [F0S]>; 144 def F1L : FPRL< 1, "f1", [F1S]>; 145 def F2L : FPRL< 2, "f2", [F2S]>; 146 def F3L : FPRL< 3, "f3", [F3S]>; 147 def F4L : FPRL< 4, "f4", [F4S]>; 148 def F5L : FPRL< 5, "f5", [F5S]>; 149 def F6L : FPRL< 6, "f6", [F6S]>; 150 def F7L : FPRL< 7, "f7", [F7S]>; 151 def F8L : FPRL< 8, "f8", [F8S]>; 152 def F9L : FPRL< 9, "f9", [F9S]>; 153 def F10L : FPRL<10, "f10", [F10S]>; 154 def F11L : FPRL<11, "f11", [F11S]>; 155 def F12L : FPRL<12, "f12", [F12S]>; 156 def F13L : FPRL<13, "f13", [F13S]>; 157 def F14L : FPRL<14, "f14", [F14S]>; 158 def F15L : FPRL<15, "f15", [F15S]>; 159 } 160 161 // Status register 162 def PSW : SystemZReg<"psw">; 163 164 /// Register classes. 165 /// Allocate the callee-saved R6-R12 backwards. That way they can be saved 166 /// together with R14 and R15 in one prolog instruction. 167 def GR32 : RegisterClass<"SystemZ", [i32], 32, (add (sequence "R%uW", 0, 5), 168 (sequence "R%uW", 15, 6))>; 169 170 /// Registers used to generate address. Everything except R0. 171 def ADDR32 : RegisterClass<"SystemZ", [i32], 32, (sub GR32, R0W)>; 172 173 def GR64 : RegisterClass<"SystemZ", [i64], 64, (add (sequence "R%uD", 0, 5), 174 (sequence "R%uD", 15, 6))> { 175 let SubRegClasses = [(GR32 subreg_32bit)]; 176 } 177 178 def ADDR64 : RegisterClass<"SystemZ", [i64], 64, (sub GR64, R0D)> { 179 let SubRegClasses = [(ADDR32 subreg_32bit)]; 180 } 181 182 // Even-odd register pairs 183 def GR64P : RegisterClass<"SystemZ", [v2i32], 64, (add R0P, R2P, R4P, 184 R12P, R10P, R8P, R6P, 185 R14P)> { 186 let SubRegClasses = [(GR32 subreg_32bit, subreg_odd32)]; 187 } 188 189 def GR128 : RegisterClass<"SystemZ", [v2i64], 128, (add R0Q, R2Q, R4Q, 190 R12Q, R10Q, R8Q, R6Q, 191 R14Q)> { 192 let SubRegClasses = [(GR32 subreg_32bit, subreg_odd32), 193 (GR64 subreg_even, subreg_odd)]; 194 } 195 196 def FP32 : RegisterClass<"SystemZ", [f32], 32, (sequence "F%uS", 0, 15)>; 197 198 def FP64 : RegisterClass<"SystemZ", [f64], 64, (sequence "F%uL", 0, 15)> { 199 let SubRegClasses = [(FP32 subreg_32bit)]; 200 } 201 202 // Status flags registers. 203 def CCR : RegisterClass<"SystemZ", [i64], 64, (add PSW)> { 204 let CopyCost = -1; // Don't allow copying of status registers. 205 } 206
