Home | History | Annotate | Download | only in TableGen 
      1 // RUN: llvm-tblgen %s | grep {\\\[(set} | count 2
      2 // RUN: llvm-tblgen %s | grep {\\\[\\\]} | count 2
      3 // XFAIL: vg_leak
      4 
      5 class ValueType<int size, int value> {
      6   int Size = size;
      7   int Value = value;
      8 }
      9 
     10 def f32  : ValueType<32, 1>;   //  2 x i64 vector value
     11 
     12 class Intrinsic<string name> {
     13   string Name = name;
     14 }
     15 
     16 class Inst<bits<8> opcode, dag oopnds, dag iopnds, string asmstr, 
     17            list<dag> pattern> {
     18   bits<8> Opcode = opcode;
     19   dag OutOperands = oopnds;
     20   dag InOperands = iopnds;
     21   string AssemblyString = asmstr;
     22   list<dag> Pattern = pattern;
     23 }
     24 
     25 def ops;
     26 def outs;
     27 def ins;
     28 
     29 def set;
     30 
     31 // Define registers
     32 class Register<string n> {
     33   string Name = n;
     34 }
     35 
     36 class RegisterClass<list<ValueType> regTypes, list<Register> regList> {
     37   list<ValueType> RegTypes = regTypes;
     38   list<Register> MemberList = regList;
     39 }
     40 
     41 def XMM0: Register<"xmm0">;
     42 def XMM1: Register<"xmm1">;
     43 def XMM2: Register<"xmm2">;
     44 def XMM3: Register<"xmm3">;
     45 def XMM4: Register<"xmm4">;
     46 def XMM5: Register<"xmm5">;
     47 def XMM6: Register<"xmm6">;
     48 def XMM7: Register<"xmm7">;
     49 def XMM8:  Register<"xmm8">;
     50 def XMM9:  Register<"xmm9">;
     51 def XMM10: Register<"xmm10">;
     52 def XMM11: Register<"xmm11">;
     53 def XMM12: Register<"xmm12">;
     54 def XMM13: Register<"xmm13">;
     55 def XMM14: Register<"xmm14">;
     56 def XMM15: Register<"xmm15">;
     57 
     58 def FR32 : RegisterClass<[f32],
     59                          [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
     60                           XMM8, XMM9, XMM10, XMM11,
     61                           XMM12, XMM13, XMM14, XMM15]>;
     62 
     63 class SDNode {}
     64 def not : SDNode;
     65 
     66 multiclass scalar<bits<8> opcode, string asmstr = "", list<list<dag>> patterns = []> {
     67   def SSrr : Inst<opcode, (outs FR32:$dst), (ins FR32:$src),
     68                   !strconcat(asmstr, "\t$dst, $src"),
     69                   !if(!empty(patterns),[]<dag>,patterns[0])>;
     70   def SSrm : Inst<opcode, (outs FR32:$dst), (ins FR32:$src),
     71                   !strconcat(asmstr, "\t$dst, $src"),
     72                   !if(!empty(patterns),[]<dag>,!if(!empty(!tail(patterns)),patterns[0],patterns[1]))>;
     73 }
     74 
     75 multiclass vscalar<bits<8> opcode, string asmstr = "", list<list<dag>> patterns = []> {
     76   def V#NAME#SSrr : Inst<opcode, (outs FR32:$dst), (ins FR32:$src),
     77                   !strconcat(asmstr, "\t$dst, $src"),
     78                   !if(!empty(patterns),[]<dag>,patterns[0])>;
     79   def V#NAME#SSrm : Inst<opcode, (outs FR32:$dst), (ins FR32:$src),
     80                   !strconcat(asmstr, "\t$dst, $src"),
     81                   !if(!empty(patterns),[]<dag>,!if(!empty(!tail(patterns)),patterns[0],patterns[1]))>;
     82 }
     83 
     84 multiclass myscalar<bits<8> opcode, string asmstr = "", list<list<dag>> patterns = []> :
     85   scalar<opcode, asmstr, patterns>,
     86   vscalar<opcode, asmstr, patterns>;
     87 
     88 defm NOT : myscalar<0x10, "not", [[], [(set FR32:$dst, (f32 (not FR32:$src)))]]>;
     89