1 //===- X86RecognizableInstr.h - Disassembler instruction spec ----*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file is part of the X86 Disassembler Emitter. 11 // It contains the interface of a single recognizable instruction. 12 // Documentation for the disassembler emitter in general can be found in 13 // X86DisasemblerEmitter.h. 14 // 15 //===----------------------------------------------------------------------===// 16 17 #ifndef X86RECOGNIZABLEINSTR_H 18 #define X86RECOGNIZABLEINSTR_H 19 20 #include "X86DisassemblerTables.h" 21 22 #include "CodeGenTarget.h" 23 24 #include "llvm/TableGen/Record.h" 25 #include "llvm/Support/DataTypes.h" 26 #include "llvm/ADT/SmallVector.h" 27 28 namespace llvm { 29 30 namespace X86Disassembler { 31 32 /// RecognizableInstr - Encapsulates all information required to decode a single 33 /// instruction, as extracted from the LLVM instruction tables. Has methods 34 /// to interpret the information available in the LLVM tables, and to emit the 35 /// instruction into DisassemblerTables. 36 class RecognizableInstr { 37 private: 38 /// The opcode of the instruction, as used in an MCInst 39 InstrUID UID; 40 /// The record from the .td files corresponding to this instruction 41 const Record* Rec; 42 /// The prefix field from the record 43 uint8_t Prefix; 44 /// The opcode field from the record; this is the opcode used in the Intel 45 /// encoding and therefore distinct from the UID 46 uint8_t Opcode; 47 /// The form field from the record 48 uint8_t Form; 49 /// The segment override field from the record 50 uint8_t SegOvr; 51 /// The hasOpSizePrefix field from the record 52 bool HasOpSizePrefix; 53 /// The hasREX_WPrefix field from the record 54 bool HasREX_WPrefix; 55 /// The hasVEXPrefix field from the record 56 bool HasVEXPrefix; 57 /// The hasVEX_4VPrefix field from the record 58 bool HasVEX_4VPrefix; 59 /// The hasVEX_4VOp3Prefix field from the record 60 bool HasVEX_4VOp3Prefix; 61 /// The hasVEX_WPrefix field from the record 62 bool HasVEX_WPrefix; 63 /// Inferred from the operands; indicates whether the L bit in the VEX prefix is set 64 bool HasVEX_LPrefix; 65 // The ignoreVEX_L field from the record 66 bool IgnoresVEX_L; 67 /// The hasLockPrefix field from the record 68 bool HasLockPrefix; 69 /// The isCodeGenOnly filed from the record 70 bool IsCodeGenOnly; 71 // Whether the instruction has the predicate "In64BitMode" 72 bool Is64Bit; 73 // Whether the instruction has the predicate "In32BitMode" 74 bool Is32Bit; 75 76 /// The instruction name as listed in the tables 77 std::string Name; 78 /// The AT&T AsmString for the instruction 79 std::string AsmString; 80 81 /// Indicates whether the instruction is SSE 82 bool IsSSE; 83 /// Indicates whether the instruction has FR operands - MOVs with FR operands 84 /// are typically ignored 85 bool HasFROperands; 86 /// Indicates whether the instruction should be emitted into the decode 87 /// tables; regardless, it will be emitted into the instruction info table 88 bool ShouldBeEmitted; 89 90 /// The operands of the instruction, as listed in the CodeGenInstruction. 91 /// They are not one-to-one with operands listed in the MCInst; for example, 92 /// memory operands expand to 5 operands in the MCInst 93 const std::vector<CGIOperandList::OperandInfo>* Operands; 94 95 /// The description of the instruction that is emitted into the instruction 96 /// info table 97 InstructionSpecifier* Spec; 98 99 /// insnContext - Returns the primary context in which the instruction is 100 /// valid. 101 /// 102 /// @return - The context in which the instruction is valid. 103 InstructionContext insnContext() const; 104 105 enum filter_ret { 106 FILTER_STRONG, // instruction has no place in the instruction tables 107 FILTER_WEAK, // instruction may conflict, and should be eliminated if 108 // it does 109 FILTER_NORMAL // instruction should have high priority and generate an 110 // error if it conflcits with any other FILTER_NORMAL 111 // instruction 112 }; 113 114 /// filter - Determines whether the instruction should be decodable. Some 115 /// instructions are pure intrinsics and use unencodable operands; many 116 /// synthetic instructions are duplicates of other instructions; other 117 /// instructions only differ in the logical way in which they are used, and 118 /// have the same decoding. Because these would cause decode conflicts, 119 /// they must be filtered out. 120 /// 121 /// @return - The degree of filtering to be applied (see filter_ret). 122 filter_ret filter() const; 123 124 /// hasFROperands - Returns true if any operand is a FR operand. 125 bool hasFROperands() const; 126 127 /// has256BitOperands - Returns true if any operand is a 256-bit SSE operand. 128 bool has256BitOperands() const; 129 130 /// typeFromString - Translates an operand type from the string provided in 131 /// the LLVM tables to an OperandType for use in the operand specifier. 132 /// 133 /// @param s - The string, as extracted by calling Rec->getName() 134 /// on a CodeGenInstruction::OperandInfo. 135 /// @param isSSE - Indicates whether the instruction is an SSE 136 /// instruction. For SSE instructions, immediates are 137 /// fixed-size rather than being affected by the 138 /// mandatory OpSize prefix. 139 /// @param hasREX_WPrefix - Indicates whether the instruction has a REX.W 140 /// prefix. If it does, 32-bit register operands stay 141 /// 32-bit regardless of the operand size. 142 /// @param hasOpSizePrefix- Indicates whether the instruction has an OpSize 143 /// prefix. If it does not, then 16-bit register 144 /// operands stay 16-bit. 145 /// @return - The operand's type. 146 static OperandType typeFromString(const std::string& s, 147 bool isSSE, 148 bool hasREX_WPrefix, 149 bool hasOpSizePrefix); 150 151 /// immediateEncodingFromString - Translates an immediate encoding from the 152 /// string provided in the LLVM tables to an OperandEncoding for use in 153 /// the operand specifier. 154 /// 155 /// @param s - See typeFromString(). 156 /// @param hasOpSizePrefix - Indicates whether the instruction has an OpSize 157 /// prefix. If it does not, then 16-bit immediate 158 /// operands stay 16-bit. 159 /// @return - The operand's encoding. 160 static OperandEncoding immediateEncodingFromString(const std::string &s, 161 bool hasOpSizePrefix); 162 163 /// rmRegisterEncodingFromString - Like immediateEncodingFromString, but 164 /// handles operands that are in the REG field of the ModR/M byte. 165 static OperandEncoding rmRegisterEncodingFromString(const std::string &s, 166 bool hasOpSizePrefix); 167 168 /// rmRegisterEncodingFromString - Like immediateEncodingFromString, but 169 /// handles operands that are in the REG field of the ModR/M byte. 170 static OperandEncoding roRegisterEncodingFromString(const std::string &s, 171 bool hasOpSizePrefix); 172 static OperandEncoding memoryEncodingFromString(const std::string &s, 173 bool hasOpSizePrefix); 174 static OperandEncoding relocationEncodingFromString(const std::string &s, 175 bool hasOpSizePrefix); 176 static OperandEncoding opcodeModifierEncodingFromString(const std::string &s, 177 bool hasOpSizePrefix); 178 static OperandEncoding vvvvRegisterEncodingFromString(const std::string &s, 179 bool HasOpSizePrefix); 180 181 /// handleOperand - Converts a single operand from the LLVM table format to 182 /// the emitted table format, handling any duplicate operands it encounters 183 /// and then one non-duplicate. 184 /// 185 /// @param optional - Determines whether to assert that the 186 /// operand exists. 187 /// @param operandIndex - The index into the generated operand table. 188 /// Incremented by this function one or more 189 /// times to reflect possible duplicate 190 /// operands). 191 /// @param physicalOperandIndex - The index of the current operand into the 192 /// set of non-duplicate ('physical') operands. 193 /// Incremented by this function once. 194 /// @param numPhysicalOperands - The number of non-duplicate operands in the 195 /// instructions. 196 /// @param operandMapping - The operand mapping, which has an entry for 197 /// each operand that indicates whether it is a 198 /// duplicate, and of what. 199 void handleOperand(bool optional, 200 unsigned &operandIndex, 201 unsigned &physicalOperandIndex, 202 unsigned &numPhysicalOperands, 203 unsigned *operandMapping, 204 OperandEncoding (*encodingFromString) 205 (const std::string&, 206 bool hasOpSizePrefix)); 207 208 /// shouldBeEmitted - Returns the shouldBeEmitted field. Although filter() 209 /// filters out many instructions, at various points in decoding we 210 /// determine that the instruction should not actually be decodable. In 211 /// particular, MMX MOV instructions aren't emitted, but they're only 212 /// identified during operand parsing. 213 /// 214 /// @return - true if at this point we believe the instruction should be 215 /// emitted; false if not. This will return false if filter() returns false 216 /// once emitInstructionSpecifier() has been called. 217 bool shouldBeEmitted() const { 218 return ShouldBeEmitted; 219 } 220 221 /// emitInstructionSpecifier - Loads the instruction specifier for the current 222 /// instruction into a DisassemblerTables. 223 /// 224 /// @arg tables - The DisassemblerTables to populate with the specifier for 225 /// the current instruction. 226 void emitInstructionSpecifier(DisassemblerTables &tables); 227 228 /// emitDecodePath - Populates the proper fields in the decode tables 229 /// corresponding to the decode paths for this instruction. 230 /// 231 /// @arg tables - The DisassemblerTables to populate with the decode 232 /// decode information for the current instruction. 233 void emitDecodePath(DisassemblerTables &tables) const; 234 235 /// Constructor - Initializes a RecognizableInstr with the appropriate fields 236 /// from a CodeGenInstruction. 237 /// 238 /// @arg tables - The DisassemblerTables that the specifier will be added to. 239 /// @arg insn - The CodeGenInstruction to extract information from. 240 /// @arg uid - The unique ID of the current instruction. 241 RecognizableInstr(DisassemblerTables &tables, 242 const CodeGenInstruction &insn, 243 InstrUID uid); 244 public: 245 /// processInstr - Accepts a CodeGenInstruction and loads decode information 246 /// for it into a DisassemblerTables if appropriate. 247 /// 248 /// @arg tables - The DiassemblerTables to be populated with decode 249 /// information. 250 /// @arg insn - The CodeGenInstruction to be used as a source for this 251 /// information. 252 /// @uid - The unique ID of the instruction. 253 static void processInstr(DisassemblerTables &tables, 254 const CodeGenInstruction &insn, 255 InstrUID uid); 256 }; 257 258 } // namespace X86Disassembler 259 260 } // namespace llvm 261 262 #endif 263
