1 /* 2 * Tiny Code Generator for QEMU 3 * 4 * Copyright (c) 2008 Fabrice Bellard 5 * Copyright (c) 2008 Andrzej Zaborowski 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 */ 25 #define TCG_TARGET_ARM 1 26 27 #define TCG_TARGET_REG_BITS 32 28 #undef TCG_TARGET_WORDS_BIGENDIAN 29 #undef TCG_TARGET_STACK_GROWSUP 30 31 enum { 32 TCG_REG_R0 = 0, 33 TCG_REG_R1, 34 TCG_REG_R2, 35 TCG_REG_R3, 36 TCG_REG_R4, 37 TCG_REG_R5, 38 TCG_REG_R6, 39 TCG_REG_R7, 40 TCG_REG_R8, 41 TCG_REG_R9, 42 TCG_REG_R10, 43 TCG_REG_R11, 44 TCG_REG_R12, 45 TCG_REG_R13, 46 TCG_REG_R14, 47 TCG_REG_PC, 48 }; 49 50 #define TCG_TARGET_NB_REGS 16 51 52 #define TCG_CT_CONST_ARM 0x100 53 54 /* used for function call generation */ 55 #define TCG_REG_CALL_STACK TCG_REG_R13 56 #define TCG_TARGET_STACK_ALIGN 8 57 #define TCG_TARGET_CALL_ALIGN_ARGS 1 58 #define TCG_TARGET_CALL_STACK_OFFSET 0 59 60 /* optional instructions */ 61 #define TCG_TARGET_HAS_ext8s_i32 62 #define TCG_TARGET_HAS_ext16s_i32 63 #undef TCG_TARGET_HAS_ext8u_i32 /* and r0, r1, #0xff */ 64 #define TCG_TARGET_HAS_ext16u_i32 65 #define TCG_TARGET_HAS_bswap16_i32 66 #define TCG_TARGET_HAS_bswap32_i32 67 #define TCG_TARGET_HAS_not_i32 68 #define TCG_TARGET_HAS_neg_i32 69 #define TCG_TARGET_HAS_rot_i32 70 #define TCG_TARGET_HAS_andc_i32 71 // #define TCG_TARGET_HAS_orc_i32 72 // #define TCG_TARGET_HAS_eqv_i32 73 // #define TCG_TARGET_HAS_nand_i32 74 // #define TCG_TARGET_HAS_nor_i32 75 76 #define TCG_TARGET_HAS_GUEST_BASE 77 78 enum { 79 /* Note: must be synced with dyngen-exec.h */ 80 TCG_AREG0 = TCG_REG_R7, 81 }; 82 83 static inline void flush_icache_range(unsigned long start, unsigned long stop) 84 { 85 #if QEMU_GNUC_PREREQ(4, 1) 86 __builtin___clear_cache((char *) start, (char *) stop); 87 #else 88 register unsigned long _beg __asm ("a1") = start; 89 register unsigned long _end __asm ("a2") = stop; 90 register unsigned long _flg __asm ("a3") = 0; 91 __asm __volatile__ ("swi 0x9f0002" : : "r" (_beg), "r" (_end), "r" (_flg)); 92 #endif 93 } 94
